2 * (C) Copyright 2009 Faraday Technology
3 * Po-Yu Chuang <ratbert@faraday-tech.com>
5 * Configuation settings for the Faraday A320 board.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <asm/arch/a320.h>
28 * Linux kernel tagged list
30 #define CONFIG_CMDLINE_TAG
31 #define CONFIG_SETUP_MEMORY_TAGS
34 * CPU and Board Configuration Options
36 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
38 #undef CONFIG_SKIP_LOWLEVEL_INIT
41 * Power Management Unit
43 #define CONFIG_FTPMU010_POWER
48 #define CONFIG_SYS_HZ 1000 /* timer ticks per second */
53 #define CONFIG_RTC_FTRTC010
56 * Serial console configuration
59 /* FTUART is a high speed NS 16C550A compatible UART */
60 #define CONFIG_BAUDRATE 38400
61 #define CONFIG_CONS_INDEX 1
62 #define CONFIG_SYS_NS16550
63 #define CONFIG_SYS_NS16550_SERIAL
64 #define CONFIG_SYS_NS16550_COM1 0x98200000
65 #define CONFIG_SYS_NS16550_REG_SIZE -4
66 #define CONFIG_SYS_NS16550_CLK 18432000
69 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
74 #define CONFIG_FTMAC100
76 #define CONFIG_BOOTDELAY 3
79 * Command line configuration.
81 #include <config_cmd_default.h>
83 #define CONFIG_CMD_CACHE
84 #define CONFIG_CMD_DATE
85 #define CONFIG_CMD_PING
88 * Miscellaneous configurable options
90 #define CONFIG_SYS_LONGHELP /* undef to save memory */
91 #define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */
92 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
94 /* Print Buffer Size */
95 #define CONFIG_SYS_PBSIZE \
96 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
98 /* max number of command args */
99 #define CONFIG_SYS_MAXARGS 16
101 /* Boot Argument Buffer Size */
102 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
107 * The stack sizes are set up in start.S using the settings below
109 #define CONFIG_STACKSIZE (128 * 1024) /* regular stack */
110 #ifdef CONFIG_USE_IRQ
111 #define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */
112 #define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */
116 * Size of malloc() pool
118 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
121 * SDRAM controller configuration
123 #define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \
124 FTSDMC020_TP0_TRP(1) | \
125 FTSDMC020_TP0_TRCD(1) | \
126 FTSDMC020_TP0_TRF(3) | \
127 FTSDMC020_TP0_TWR(1) | \
128 FTSDMC020_TP0_TCL(2))
130 #define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \
131 FTSDMC020_TP1_INI_REFT(8) | \
132 FTSDMC020_TP1_REF_INTV(0x180))
134 #define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \
135 FTSDMC020_BANK_DDW_X16 | \
136 FTSDMC020_BANK_DSZ_256M | \
137 FTSDMC020_BANK_MBW_32 | \
138 FTSDMC020_BANK_SIZE_64M)
141 * Physical Memory Map
143 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
144 #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
145 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
147 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
148 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
149 GENERATED_GBL_DATA_SIZE)
152 * Load address and memory test area should agree with
153 * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself.
155 #define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x2000000)
157 /* memtest works on 63 MB in DRAM */
158 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
159 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x3F00000)
161 #define CONFIG_SYS_TEXT_BASE 0
164 * Static memory controller configuration
167 #define CONFIG_FTSMC020
168 #include <faraday/ftsmc020.h>
170 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
171 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
172 FTSMC020_BANK_SIZE_1M | \
175 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \
176 FTSMC020_TPR_AST(3) | \
177 FTSMC020_TPR_CTW(3) | \
178 FTSMC020_TPR_ATI(0xf) | \
179 FTSMC020_TPR_AT2(3) | \
180 FTSMC020_TPR_WTC(3) | \
181 FTSMC020_TPR_AHT(3) | \
182 FTSMC020_TPR_TRNA(0xf))
184 #define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \
185 FTSMC020_BANK_BASE(PHYS_FLASH_2) | \
186 FTSMC020_BANK_SIZE_32M | \
187 FTSMC020_BANK_MBW_32)
189 #define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \
190 FTSMC020_TPR_CTW(3) | \
191 FTSMC020_TPR_ATI(0xf) | \
192 FTSMC020_TPR_AT2(3) | \
193 FTSMC020_TPR_WTC(3) | \
194 FTSMC020_TPR_AHT(3) | \
195 FTSMC020_TPR_TRNA(0xf))
197 #define CONFIG_SYS_FTSMC020_CONFIGS { \
198 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
199 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
203 * FLASH and environment organization
206 /* use CFI framework */
207 #define CONFIG_SYS_FLASH_CFI
208 #define CONFIG_FLASH_CFI_DRIVER
211 #define CONFIG_FLASH_CFI_LEGACY
212 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
214 #define PHYS_FLASH_1 0x00000000
215 #define PHYS_FLASH_2 0x00400000
216 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
217 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, }
219 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
221 /* max number of memory banks */
222 #define CONFIG_SYS_MAX_FLASH_BANKS 2
224 /* max number of sectors on one chip */
225 #define CONFIG_SYS_MAX_FLASH_SECT 512
227 #undef CONFIG_SYS_FLASH_EMPTY_INFO
230 #define CONFIG_ENV_IS_IN_FLASH
231 #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000)
232 #define CONFIG_ENV_SIZE 0x20000
234 #endif /* __CONFIG_H */