Convert CONFIG_CONS_INDEX et al to Kconfig
[platform/kernel/u-boot.git] / include / configs / T102xRDB.h
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2014 Freescale Semiconductor, Inc.
4  * Copyright 2020-2021 NXP
5  */
6
7 /*
8  * T1024/T1023 RDB board configuration file
9  */
10
11 #ifndef __T1024RDB_H
12 #define __T1024RDB_H
13
14 #include <linux/stringify.h>
15
16 /* High Level Configuration Options */
17 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
18 #define CONFIG_ENABLE_36BIT_PHYS
19
20 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
21 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
22
23 /* support deep sleep */
24 #ifdef CONFIG_ARCH_T1024
25 #define CONFIG_DEEP_SLEEP
26 #endif
27
28 #ifdef CONFIG_RAMBOOT_PBL
29 #define CONFIG_SPL_FLUSH_IMAGE
30 #define CONFIG_SPL_PAD_TO               0x40000
31 #define CONFIG_SPL_MAX_SIZE             0x28000
32 #define RESET_VECTOR_OFFSET             0x27FFC
33 #define BOOT_PAGE_OFFSET                0x27000
34 #ifdef CONFIG_SPL_BUILD
35 #define CONFIG_SPL_SKIP_RELOCATE
36 #define CONFIG_SPL_COMMON_INIT_DDR
37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
38 #endif
39
40 #ifdef CONFIG_MTD_RAW_NAND
41 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
42 #define CONFIG_SYS_NAND_U_BOOT_DST      0x30000000
43 #define CONFIG_SYS_NAND_U_BOOT_START    0x30000000
44 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
45 #endif
46
47 #ifdef CONFIG_SPIFLASH
48 #define CONFIG_RESET_VECTOR_ADDRESS             0x30000FFC
49 #define CONFIG_SPL_SPI_FLASH_MINIMAL
50 #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE        (768 << 10)
51 #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST         (0x30000000)
52 #define CONFIG_SYS_SPI_FLASH_U_BOOT_START       (0x30000000)
53 #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS        (256 << 10)
54 #ifndef CONFIG_SPL_BUILD
55 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
56 #endif
57 #endif
58
59 #ifdef CONFIG_SDCARD
60 #define CONFIG_RESET_VECTOR_ADDRESS     0x30000FFC
61 #define CONFIG_SYS_MMC_U_BOOT_SIZE      (768 << 10)
62 #define CONFIG_SYS_MMC_U_BOOT_DST       (0x30000000)
63 #define CONFIG_SYS_MMC_U_BOOT_START     (0x30000000)
64 #define CONFIG_SYS_MMC_U_BOOT_OFFS      (260 << 10)
65 #ifndef CONFIG_SPL_BUILD
66 #define CONFIG_SYS_MPC85XX_NO_RESETVEC
67 #endif
68 #endif
69
70 #endif /* CONFIG_RAMBOOT_PBL */
71
72 #ifndef CONFIG_RESET_VECTOR_ADDRESS
73 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
74 #endif
75
76 /* PCIe Boot - Master */
77 #define CONFIG_SRIO_PCIE_BOOT_MASTER
78 /*
79  * for slave u-boot IMAGE instored in master memory space,
80  * PHYS must be aligned based on the SIZE
81  */
82 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
83 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE     0x100000 /* 1M */
84 #ifdef CONFIG_PHYS_64BIT
85 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
86 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
87 #else
88 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
89 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
90 #endif
91 /*
92  * for slave UCODE and ENV instored in master memory space,
93  * PHYS must be aligned based on the SIZE
94  */
95 #ifdef CONFIG_PHYS_64BIT
96 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
97 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0x3ffe00000ull
98 #else
99 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
100 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS  0xffe00000
101 #endif
102 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE    0x40000 /* 256K */
103 /* slave core release by master*/
104 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET        0xe00e4
105 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK      0x00000001 /* release core 0 */
106
107 /* PCIe Boot - Slave */
108 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
109 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
110 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
111                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
112 /* Set 1M boot space for PCIe boot */
113 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
114 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS       \
115                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
116 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
117 #endif
118
119 #ifndef __ASSEMBLY__
120 unsigned long get_board_sys_clk(void);
121 #endif
122
123 #define CONFIG_SYS_CLK_FREQ     100000000
124
125 /*
126  * These can be toggled for performance analysis, otherwise use default.
127  */
128 #define CONFIG_SYS_CACHE_STASHING
129 #define CONFIG_BACKSIDE_L2_CACHE
130 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
131 #define CONFIG_BTB                      /* toggle branch predition */
132 #ifdef CONFIG_DDR_ECC
133 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
134 #endif
135
136 /*
137  *  Config the L3 Cache as L3 SRAM
138  */
139 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
140 #define CONFIG_SYS_L3_SIZE              (256 << 10)
141 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
142 #define SPL_ENV_ADDR                    (CONFIG_SPL_GD_ADDR + 4 * 1024)
143 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
144 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
145 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
146
147 #ifdef CONFIG_PHYS_64BIT
148 #define CONFIG_SYS_DCSRBAR              0xf0000000
149 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
150 #endif
151
152 /* EEPROM */
153 #define CONFIG_SYS_I2C_EEPROM_NXID
154 #define CONFIG_SYS_EEPROM_BUS_NUM       0
155
156 /*
157  * DDR Setup
158  */
159 #define CONFIG_VERY_BIG_RAM
160 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
161 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
162 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
163 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
164 #if defined(CONFIG_TARGET_T1024RDB)
165 #define CONFIG_SYS_SPD_BUS_NUM  0
166 #define SPD_EEPROM_ADDRESS      0x51
167 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
168 #elif defined(CONFIG_TARGET_T1023RDB)
169 #define CONFIG_SYS_DDR_RAW_TIMING
170 #define CONFIG_SYS_SDRAM_SIZE   2048
171 #endif
172
173 /*
174  * IFC Definitions
175  */
176 #define CONFIG_SYS_FLASH_BASE   0xe8000000
177 #ifdef CONFIG_PHYS_64BIT
178 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
179 #else
180 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
181 #endif
182
183 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
184 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
185                                 CSPR_PORT_SIZE_16 | \
186                                 CSPR_MSEL_NOR | \
187                                 CSPR_V)
188 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
189
190 /* NOR Flash Timing Params */
191 #if defined(CONFIG_TARGET_T1024RDB)
192 #define CONFIG_SYS_NOR_CSOR     CSOR_NAND_TRHZ_80
193 #elif defined(CONFIG_TARGET_T1023RDB)
194 #define CONFIG_SYS_NOR_CSOR    (CSOR_NOR_ADM_SHIFT(0) | \
195                                 CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
196 #endif
197 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x4) | \
198                                 FTIM0_NOR_TEADC(0x5) | \
199                                 FTIM0_NOR_TEAHC(0x5))
200 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
201                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
202                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
203 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x4) | \
204                                 FTIM2_NOR_TCH(0x4) | \
205                                 FTIM2_NOR_TWPH(0x0E) | \
206                                 FTIM2_NOR_TWP(0x1c))
207 #define CONFIG_SYS_NOR_FTIM3    0x0
208
209 #define CONFIG_SYS_FLASH_QUIET_TEST
210 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
211
212 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
213 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
214 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
215 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
216
217 #define CONFIG_SYS_FLASH_EMPTY_INFO
218 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
219
220 #ifdef CONFIG_TARGET_T1024RDB
221 /* CPLD on IFC */
222 #define CONFIG_SYS_CPLD_BASE            0xffdf0000
223 #define CONFIG_SYS_CPLD_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
224 #define CONFIG_SYS_CSPR2_EXT            (0xf)
225 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
226                                                 | CSPR_PORT_SIZE_8 \
227                                                 | CSPR_MSEL_GPCM \
228                                                 | CSPR_V)
229 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
230 #define CONFIG_SYS_CSOR2                0x0
231
232 /* CPLD Timing parameters for IFC CS2 */
233 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
234                                                 FTIM0_GPCM_TEADC(0x0e) | \
235                                                 FTIM0_GPCM_TEAHC(0x0e))
236 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
237                                                 FTIM1_GPCM_TRAD(0x1f))
238 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
239                                                 FTIM2_GPCM_TCH(0x8) | \
240                                                 FTIM2_GPCM_TWP(0x1f))
241 #define CONFIG_SYS_CS2_FTIM3            0x0
242 #endif
243
244 /* NAND Flash on IFC */
245 #define CONFIG_SYS_NAND_BASE            0xff800000
246 #ifdef CONFIG_PHYS_64BIT
247 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
248 #else
249 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
250 #endif
251 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
252 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
253                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
254                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
255                                 | CSPR_V)
256 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
257
258 #if defined(CONFIG_TARGET_T1024RDB)
259 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
260                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
261                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
262                                 | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
263                                 | CSOR_NAND_PGS_4K      /* Page Size = 4K */ \
264                                 | CSOR_NAND_SPRZ_224    /* Spare size = 224 */ \
265                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
266 #elif defined(CONFIG_TARGET_T1023RDB)
267 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
268                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
269                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
270                                 | CSOR_NAND_RAL_3       /* RAL 3Bytes */ \
271                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
272                                 | CSOR_NAND_SPRZ_128    /* Spare size = 128 */ \
273                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
274 #endif
275
276 /* ONFI NAND Flash mode0 Timing Params */
277 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
278                                         FTIM0_NAND_TWP(0x18)   | \
279                                         FTIM0_NAND_TWCHT(0x07) | \
280                                         FTIM0_NAND_TWH(0x0a))
281 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
282                                         FTIM1_NAND_TWBE(0x39)  | \
283                                         FTIM1_NAND_TRR(0x0e)   | \
284                                         FTIM1_NAND_TRP(0x18))
285 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
286                                         FTIM2_NAND_TREH(0x0a) | \
287                                         FTIM2_NAND_TWHRE(0x1e))
288 #define CONFIG_SYS_NAND_FTIM3           0x0
289
290 #define CONFIG_SYS_NAND_DDR_LAW         11
291 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
292 #define CONFIG_SYS_MAX_NAND_DEVICE      1
293
294 #if defined(CONFIG_MTD_RAW_NAND)
295 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
296 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
297 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
298 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
299 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
300 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
301 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
302 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
303 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR0_CSPR_EXT
304 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR0_CSPR
305 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
306 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
307 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
308 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
309 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
310 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
311 #else
312 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
313 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
314 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
315 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
316 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
317 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
318 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
319 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
320 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NAND_CSPR_EXT
321 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
322 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
323 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
324 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
325 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
326 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
327 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
328 #endif
329
330 #ifdef CONFIG_SPL_BUILD
331 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SPL_TEXT_BASE
332 #else
333 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
334 #endif
335
336 #if defined(CONFIG_RAMBOOT_PBL)
337 #define CONFIG_SYS_RAMBOOT
338 #endif
339
340 #define CONFIG_HWCONFIG
341
342 /* define to use L1 as initial stack */
343 #define CONFIG_L1_INIT_RAM
344 #define CONFIG_SYS_INIT_RAM_LOCK
345 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
346 #ifdef CONFIG_PHYS_64BIT
347 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
348 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
349 /* The assembler doesn't like typecast */
350 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
351         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
352           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
353 #else
354 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
355 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
356 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
357 #endif
358 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
359
360 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
361                                         GENERATED_GBL_DATA_SIZE)
362 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
363
364 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
365
366 /* Serial Port */
367 #define CONFIG_SYS_NS16550_SERIAL
368 #define CONFIG_SYS_NS16550_REG_SIZE     1
369 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
370
371 #define CONFIG_SYS_BAUDRATE_TABLE       \
372         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
373
374 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
375 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
376 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
377 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
378
379 /* Video */
380 #undef CONFIG_FSL_DIU_FB        /* RDB doesn't support DIU */
381 #ifdef CONFIG_FSL_DIU_FB
382 #define CONFIG_SYS_DIU_ADDR     (CONFIG_SYS_CCSRBAR + 0x180000)
383 #define CONFIG_VIDEO_LOGO
384 #define CONFIG_VIDEO_BMP_LOGO
385 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
386 /*
387  * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
388  * disable empty flash sector detection, which is I/O-intensive.
389  */
390 #undef CONFIG_SYS_FLASH_EMPTY_INFO
391 #endif
392
393 /* I2C */
394
395 #define I2C_PCA6408_BUS_NUM             1
396 #define I2C_PCA6408_ADDR                0x20
397
398 /* I2C bus multiplexer */
399 #define I2C_MUX_CH_DEFAULT      0x8
400
401 /*
402  * RTC configuration
403  */
404 #define RTC
405 #define CONFIG_RTC_DS1337       1
406 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
407
408 /*
409  * eSPI - Enhanced SPI
410  */
411
412 /*
413  * General PCIe
414  * Memory space is mapped 1-1, but I/O space must start from 0.
415  */
416 #define CONFIG_PCIE1            /* PCIE controller 1 */
417 #define CONFIG_PCIE2            /* PCIE controller 2 */
418 #define CONFIG_PCIE3            /* PCIE controller 3 */
419 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
420
421 #ifdef CONFIG_PCI
422 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
423 #ifdef CONFIG_PCIE1
424 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
425 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
426 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
427 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
428 #endif
429
430 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
431 #ifdef CONFIG_PCIE2
432 #define CONFIG_SYS_PCIE2_MEM_VIRT       0x90000000
433 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc10000000ull
434 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
435 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
436 #endif
437
438 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
439 #ifdef CONFIG_PCIE3
440 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
441 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
442 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
443 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
444 #endif
445
446 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
447 #endif  /* CONFIG_PCI */
448
449 /*
450  * USB
451  */
452 #define CONFIG_HAS_FSL_DR_USB
453
454 #ifdef CONFIG_HAS_FSL_DR_USB
455 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
456 #endif
457
458 /*
459  * SDHC
460  */
461 #ifdef CONFIG_MMC
462 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
463 #endif
464
465 /* Qman/Bman */
466 #ifndef CONFIG_NOBQFMAN
467 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
468 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
469 #ifdef CONFIG_PHYS_64BIT
470 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
471 #else
472 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
473 #endif
474 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
475 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
476 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
477 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
478 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
479 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
480                                         CONFIG_SYS_BMAN_CENA_SIZE)
481 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
482 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
483 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
484 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
485 #ifdef CONFIG_PHYS_64BIT
486 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
487 #else
488 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
489 #endif
490 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
491 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
492 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
493 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
494 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
495 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
496                                         CONFIG_SYS_QMAN_CENA_SIZE)
497 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
498 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
499
500 #define CONFIG_SYS_DPAA_FMAN
501
502 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
503 #endif /* CONFIG_NOBQFMAN */
504
505 #ifdef CONFIG_SYS_DPAA_FMAN
506 #if defined(CONFIG_TARGET_T1024RDB)
507 #define RGMII_PHY1_ADDR         0x2
508 #define RGMII_PHY2_ADDR         0x6
509 #define SGMII_AQR_PHY_ADDR      0x2
510 #define FM1_10GEC1_PHY_ADDR     0x1
511 #elif defined(CONFIG_TARGET_T1023RDB)
512 #define RGMII_PHY1_ADDR         0x1
513 #define SGMII_RTK_PHY_ADDR      0x3
514 #define SGMII_AQR_PHY_ADDR      0x2
515 #endif
516 #endif
517
518 #ifdef CONFIG_FMAN_ENET
519 #define CONFIG_ETHPRIME         "FM1@DTSEC4"
520 #endif
521
522 /*
523  * Dynamic MTD Partition support with mtdparts
524  */
525
526 /*
527  * Environment
528  */
529 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
530 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
531
532 /*
533  * Miscellaneous configurable options
534  */
535
536 /*
537  * For booting Linux, the board info and command line data
538  * have to be in the first 64 MB of memory, since this is
539  * the maximum mapped by the Linux kernel during initialization.
540  */
541 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
542 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
543
544 /*
545  * Environment Configuration
546  */
547 #define CONFIG_ROOTPATH         "/opt/nfsroot"
548 #define CONFIG_BOOTFILE         "uImage"
549 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
550 #define __USB_PHY_TYPE          utmi
551
552 #ifdef CONFIG_ARCH_T1024
553 #define CONFIG_BOARDNAME t1024rdb
554 #define BANK_INTLV cs0_cs1
555 #else
556 #define CONFIG_BOARDNAME t1023rdb
557 #define BANK_INTLV  null
558 #endif
559
560 #define CONFIG_EXTRA_ENV_SETTINGS                               \
561         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
562         "bank_intlv=" __stringify(BANK_INTLV) "\0"              \
563         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"  \
564         "ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
565         "fdtfile=" __stringify(CONFIG_BOARDNAME) "/"            \
566         __stringify(CONFIG_BOARDNAME) ".dtb\0"                  \
567         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"             \
568         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"     \
569         "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
570         "netdev=eth0\0"                                         \
571         "tftpflash=tftpboot $loadaddr $uboot && "               \
572         "protect off $ubootaddr +$filesize && "                 \
573         "erase $ubootaddr +$filesize && "                       \
574         "cp.b $loadaddr $ubootaddr $filesize && "               \
575         "protect on $ubootaddr +$filesize && "                  \
576         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
577         "consoledev=ttyS0\0"                                    \
578         "ramdiskaddr=2000000\0"                                 \
579         "fdtaddr=1e00000\0"                                     \
580         "bdev=sda3\0"
581
582 #include <asm/fsl_secure_boot.h>
583
584 #endif  /* __T1024RDB_H */