include/configs/P2041RDB.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   4  * Copyright 2020-2021 NXP
   5  */
   6
   7 /*
   8  * P2041 RDB board configuration file
   9  * Also supports P2040 RDB
  10  */
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #ifdef CONFIG_RAMBOOT_PBL
  15 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_TEXT_BASE
  16 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  17 #endif
  18
  19 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  20 /* Set 1M boot space */
  21 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
  22 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  23                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  24 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  25 #endif
  26
  27 /* High Level Configuration Options */
  28
  29 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  30 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  31 #endif
  32
  33 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  34
  35 #define CONFIG_SYS_SRIO
  36 #define CONFIG_SRIO1                    /* SRIO port 1 */
  37 #define CONFIG_SRIO2                    /* SRIO port 2 */
  38 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  39 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  40
  41 #ifndef __ASSEMBLY__
  42 #include <linux/stringify.h>
  43 #endif
  44
  45 /*
  46  * These can be toggled for performance analysis, otherwise use default.
  47  */
  48 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  49
  50 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
  51
  52 /*
  53  *  Config the L3 Cache as L3 SRAM
  54  */
  55 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  56 #ifdef CONFIG_PHYS_64BIT
  57 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  58                 CONFIG_RAMBOOT_TEXT_BASE)
  59 #else
  60 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    CONFIG_SYS_INIT_L3_ADDR
  61 #endif
  62
  63 #ifdef CONFIG_PHYS_64BIT
  64 #define CONFIG_SYS_DCSRBAR              0xf0000000
  65 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  66 #endif
  67
  68 /*
  69  * DDR Setup
  70  */
  71 #define CONFIG_VERY_BIG_RAM
  72 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  73 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  74
  75 #define SPD_EEPROM_ADDRESS      0x52
  76 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  77
  78 /*
  79  * Local Bus Definitions
  80  */
  81
  82 /* Set the local bus clock 1/8 of platform clock */
  83 #define CONFIG_SYS_LBC_LCRR             LCRR_CLKDIV_8
  84
  85 /*
  86  * This board doesn't have a promjet connector.
  87  * However, it uses commone corenet board LAW and TLB.
  88  * It is necessary to use the same start address with proper offset.
  89  */
  90 #define CONFIG_SYS_FLASH_BASE           0xe0000000
  91 #ifdef CONFIG_PHYS_64BIT
  92 #define CONFIG_SYS_FLASH_BASE_PHYS      0xfe0000000ull
  93 #else
  94 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
  95 #endif
  96
  97 #define CONFIG_FSL_CPLD
  98 #define CPLD_BASE               0xffdf0000      /* CPLD registers */
  99 #ifdef CONFIG_PHYS_64BIT
 100 #define CPLD_BASE_PHYS          0xfffdf0000ull
 101 #else
 102 #define CPLD_BASE_PHYS          CPLD_BASE
 103 #endif
 104
 105 #define PIXIS_LBMAP_SWITCH      7
 106 #define PIXIS_LBMAP_MASK        0xf0
 107 #define PIXIS_LBMAP_SHIFT       4
 108 #define PIXIS_LBMAP_ALTBANK     0x40
 109
 110 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 111
 112 /* Nand Flash */
 113 #ifdef CONFIG_NAND_FSL_ELBC
 114 #define CONFIG_SYS_NAND_BASE            0xffa00000
 115 #ifdef CONFIG_PHYS_64BIT
 116 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 117 #else
 118 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 119 #endif
 120
 121 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 122
 123 /* NAND flash config */
 124 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 125                                | (2<<BR_DECC_SHIFT)    /* Use HW ECC */ \
 126                                | BR_PS_8               /* Port Size = 8 bit */ \
 127                                | BR_MS_FCM             /* MSEL = FCM */ \
 128                                | BR_V)                 /* valid */
 129 #define CONFIG_SYS_NAND_OR_PRELIM  (0xFFFC0000        /* length 256K */ \
 130                                | OR_FCM_PGS            /* Large Page*/ \
 131                                | OR_FCM_CSCT \
 132                                | OR_FCM_CST \
 133                                | OR_FCM_CHT \
 134                                | OR_FCM_SCY_1 \
 135                                | OR_FCM_TRLX \
 136                                | OR_FCM_EHTR)
 137 #endif /* CONFIG_NAND_FSL_ELBC */
 138
 139 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 140
 141 #define CONFIG_HWCONFIG
 142
 143 /* define to use L1 as initial stack */
 144 #define CONFIG_L1_INIT_RAM
 145 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 146 #ifdef CONFIG_PHYS_64BIT
 147 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 148 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 149 /* The assembler doesn't like typecast */
 150 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 151         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 152           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 153 #else
 154 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 155 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 156 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 157 #endif
 158 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 159
 160 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 161
 162 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 163
 164 /* Serial Port - controlled on board with jumper J8
 165  * open - index 2
 166  * shorted - index 1
 167  */
 168 #define CONFIG_SYS_NS16550_SERIAL
 169 #define CONFIG_SYS_NS16550_REG_SIZE     1
 170 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 171
 172 #define CONFIG_SYS_BAUDRATE_TABLE       \
 173         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 174
 175 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 176 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 177 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 178 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 179
 180 /* I2C */
 181
 182
 183 /*
 184  * RapidIO
 185  */
 186 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 187 #ifdef CONFIG_PHYS_64BIT
 188 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 189 #else
 190 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 191 #endif
 192 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 193
 194 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 195 #ifdef CONFIG_PHYS_64BIT
 196 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 197 #else
 198 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 199 #endif
 200 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 201
 202 /*
 203  * for slave u-boot IMAGE instored in master memory space,
 204  * PHYS must be aligned based on the SIZE
 205  */
 206 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 207 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 208 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 209 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 210 /*
 211  * for slave UCODE and ENV instored in master memory space,
 212  * PHYS must be aligned based on the SIZE
 213  */
 214 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 215 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 216 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 217
 218 /* slave core release by master*/
 219 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 220 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 221
 222 /*
 223  * SRIO_PCIE_BOOT - SLAVE
 224  */
 225 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 226 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 227 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 228                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 229 #endif
 230
 231 /*
 232  * eSPI - Enhanced SPI
 233  */
 234
 235 /*
 236  * General PCI
 237  * Memory space is mapped 1-1, but I/O space must start from 0.
 238  */
 239
 240 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 241 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 242 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 243 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 244 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 245
 246 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 247 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 248 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xc20000000ull
 249 #define CONFIG_SYS_PCIE2_IO_VIRT        0xf8010000
 250 #define CONFIG_SYS_PCIE2_IO_PHYS        0xff8010000ull
 251
 252 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 253 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xc0000000
 254 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc40000000ull
 255 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8020000
 256 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8020000ull
 257
 258 /* Qman/Bman */
 259 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 260 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 261 #ifdef CONFIG_PHYS_64BIT
 262 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 263 #else
 264 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 265 #endif
 266 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 267 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 268 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 269 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 270 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 271 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 272                                         CONFIG_SYS_BMAN_CENA_SIZE)
 273 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 274 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 275 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 276 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 277 #ifdef CONFIG_PHYS_64BIT
 278 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 279 #else
 280 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 281 #endif
 282 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 283 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 284 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 285 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 286 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 287 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 288                                         CONFIG_SYS_QMAN_CENA_SIZE)
 289 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 290 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 291
 292 #define CONFIG_SYS_DPAA_FMAN
 293 #define CONFIG_SYS_DPAA_PME
 294
 295 #ifdef CONFIG_FMAN_ENET
 296 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR  0x2
 297 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR  0x3
 298 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR  0x4
 299 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR  0x1
 300 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x0
 301
 302 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 303 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 304 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 305 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 306
 307 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR  0
 308
 309 #define CONFIG_SYS_TBIPA_VALUE  8
 310 #endif
 311
 312 #ifdef CONFIG_MMC
 313 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 314 #endif
 315
 316 /*
 317  * Miscellaneous configurable options
 318  */
 319
 320 /*
 321  * For booting Linux, the board info and command line data
 322  * have to be in the first 64 MB of memory, since this is
 323  * the maximum mapped by the Linux kernel during initialization.
 324  */
 325 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 326
 327 /*
 328  * Environment Configuration
 329  */
 330 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 331 #define CONFIG_UBOOTPATH        u-boot.bin
 332
 333 #define __USB_PHY_TYPE  utmi
 334
 335 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 336         "hwconfig=fsl_ddr:ctlr_intlv=cacheline,"                \
 337         "bank_intlv=cs0_cs1\0"                                  \
 338         "netdev=eth0\0"                                         \
 339         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 340         "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0"         \
 341         "tftpflash=tftpboot $loadaddr $uboot && "               \
 342         "protect off $ubootaddr +$filesize && "                 \
 343         "erase $ubootaddr +$filesize && "                       \
 344         "cp.b $loadaddr $ubootaddr $filesize && "               \
 345         "protect on $ubootaddr +$filesize && "                  \
 346         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 347         "consoledev=ttyS0\0"                                    \
 348         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 349         "usb_dr_mode=host\0"                                    \
 350         "ramdiskaddr=2000000\0"                                 \
 351         "ramdiskfile=p2041rdb/ramdisk.uboot\0"                  \
 352         "fdtaddr=1e00000\0"                                     \
 353         "fdtfile=p2041rdb/p2041rdb.dtb\0"                       \
 354         "bdev=sda3\0"
 355
 356 #include <asm/fsl_secure_boot.h>
 357
 358 #endif  /* __CONFIG_H */