2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
8 * P2041 RDB board configuration file
9 * Also supports P2040 RDB
14 #define CONFIG_P2041RDB
15 #define CONFIG_PHYS_64BIT
16 #define CONFIG_SYS_GENERIC_BOARD
17 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_PPC_P2041
20 #ifdef CONFIG_RAMBOOT_PBL
21 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
22 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
23 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
24 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
27 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
28 /* Set 1M boot space */
29 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
30 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
31 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
32 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
33 #define CONFIG_SYS_NO_FLASH
36 /* High Level Configuration Options */
38 #define CONFIG_E500 /* BOOKE e500 family */
39 #define CONFIG_E500MC /* BOOKE e500mc family */
40 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
41 #define CONFIG_MP /* support multiple processors */
43 #ifndef CONFIG_SYS_TEXT_BASE
44 #define CONFIG_SYS_TEXT_BASE 0xeff40000
47 #ifndef CONFIG_RESET_VECTOR_ADDRESS
48 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
51 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
52 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
53 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
54 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
55 #define CONFIG_PCI /* Enable PCI/PCIE */
56 #define CONFIG_PCIE1 /* PCIE controler 1 */
57 #define CONFIG_PCIE2 /* PCIE controler 2 */
58 #define CONFIG_PCIE3 /* PCIE controler 3 */
59 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
60 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
62 #define CONFIG_SYS_SRIO
63 #define CONFIG_SRIO1 /* SRIO port 1 */
64 #define CONFIG_SRIO2 /* SRIO port 2 */
65 #define CONFIG_SRIO_PCIE_BOOT_MASTER
66 #define CONFIG_SYS_DPAA_RMAN /* RMan */
68 #define CONFIG_FSL_LAW /* Use common FSL init code */
70 #define CONFIG_ENV_OVERWRITE
72 #ifdef CONFIG_SYS_NO_FLASH
73 #if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
74 #define CONFIG_ENV_IS_NOWHERE
77 #define CONFIG_FLASH_CFI_DRIVER
78 #define CONFIG_SYS_FLASH_CFI
79 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
82 #if defined(CONFIG_SPIFLASH)
83 #define CONFIG_SYS_EXTRA_ENV_RELOC
84 #define CONFIG_ENV_IS_IN_SPI_FLASH
85 #define CONFIG_ENV_SPI_BUS 0
86 #define CONFIG_ENV_SPI_CS 0
87 #define CONFIG_ENV_SPI_MAX_HZ 10000000
88 #define CONFIG_ENV_SPI_MODE 0
89 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
90 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
91 #define CONFIG_ENV_SECT_SIZE 0x10000
92 #elif defined(CONFIG_SDCARD)
93 #define CONFIG_SYS_EXTRA_ENV_RELOC
94 #define CONFIG_ENV_IS_IN_MMC
95 #define CONFIG_FSL_FIXED_MMC_LOCATION
96 #define CONFIG_SYS_MMC_ENV_DEV 0
97 #define CONFIG_ENV_SIZE 0x2000
98 #define CONFIG_ENV_OFFSET (512 * 1658)
99 #elif defined(CONFIG_NAND)
100 #define CONFIG_SYS_EXTRA_ENV_RELOC
101 #define CONFIG_ENV_IS_IN_NAND
102 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
103 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
104 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
105 #define CONFIG_ENV_IS_IN_REMOTE
106 #define CONFIG_ENV_ADDR 0xffe20000
107 #define CONFIG_ENV_SIZE 0x2000
108 #elif defined(CONFIG_ENV_IS_NOWHERE)
109 #define CONFIG_ENV_SIZE 0x2000
111 #define CONFIG_ENV_IS_IN_FLASH
112 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
113 - CONFIG_ENV_SECT_SIZE)
114 #define CONFIG_ENV_SIZE 0x2000
115 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
119 unsigned long get_board_sys_clk(unsigned long dummy);
121 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
124 * These can be toggled for performance analysis, otherwise use default.
126 #define CONFIG_SYS_CACHE_STASHING
127 #define CONFIG_BACKSIDE_L2_CACHE
128 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
129 #define CONFIG_BTB /* toggle branch predition */
131 #define CONFIG_ENABLE_36BIT_PHYS
133 #ifdef CONFIG_PHYS_64BIT
134 #define CONFIG_ADDR_MAP
135 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
138 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
140 #define CONFIG_SYS_MEMTEST_END 0x00400000
141 #define CONFIG_SYS_ALT_MEMTEST
142 #define CONFIG_PANIC_HANG /* do not reset board on panic */
145 * Config the L3 Cache as L3 SRAM
147 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
148 #ifdef CONFIG_PHYS_64BIT
149 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
150 CONFIG_RAMBOOT_TEXT_BASE)
152 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
154 #define CONFIG_SYS_L3_SIZE (1024 << 10)
155 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
157 #ifdef CONFIG_PHYS_64BIT
158 #define CONFIG_SYS_DCSRBAR 0xf0000000
159 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
163 #define CONFIG_ID_EEPROM
164 #define CONFIG_SYS_I2C_EEPROM_NXID
165 #define CONFIG_SYS_EEPROM_BUS_NUM 0
166 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
167 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
172 #define CONFIG_VERY_BIG_RAM
173 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
174 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
176 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
177 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
179 #define CONFIG_DDR_SPD
180 #define CONFIG_SYS_FSL_DDR3
182 #define CONFIG_SYS_SPD_BUS_NUM 0
183 #define SPD_EEPROM_ADDRESS 0x52
184 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
187 * Local Bus Definitions
190 /* Set the local bus clock 1/8 of platform clock */
191 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
194 * This board doesn't have a promjet connector.
195 * However, it uses commone corenet board LAW and TLB.
196 * It is necessary to use the same start address with proper offset.
198 #define CONFIG_SYS_FLASH_BASE 0xe0000000
199 #ifdef CONFIG_PHYS_64BIT
200 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
202 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
205 #define CONFIG_SYS_FLASH_BR_PRELIM \
206 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
208 #define CONFIG_SYS_FLASH_OR_PRELIM \
209 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
210 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
212 #define CONFIG_FSL_CPLD
213 #define CPLD_BASE 0xffdf0000 /* CPLD registers */
214 #ifdef CONFIG_PHYS_64BIT
215 #define CPLD_BASE_PHYS 0xfffdf0000ull
217 #define CPLD_BASE_PHYS CPLD_BASE
220 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
221 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
223 #define PIXIS_LBMAP_SWITCH 7
224 #define PIXIS_LBMAP_MASK 0xf0
225 #define PIXIS_LBMAP_SHIFT 4
226 #define PIXIS_LBMAP_ALTBANK 0x40
228 #define CONFIG_SYS_FLASH_QUIET_TEST
229 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
231 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
232 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
233 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
234 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
236 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
238 #if defined(CONFIG_RAMBOOT_PBL)
239 #define CONFIG_SYS_RAMBOOT
242 #define CONFIG_NAND_FSL_ELBC
244 #ifdef CONFIG_NAND_FSL_ELBC
245 #define CONFIG_SYS_NAND_BASE 0xffa00000
246 #ifdef CONFIG_PHYS_64BIT
247 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
249 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
252 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
253 #define CONFIG_SYS_MAX_NAND_DEVICE 1
254 #define CONFIG_CMD_NAND
255 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
257 /* NAND flash config */
258 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
259 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
260 | BR_PS_8 /* Port Size = 8 bit */ \
261 | BR_MS_FCM /* MSEL = FCM */ \
263 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
264 | OR_FCM_PGS /* Large Page*/ \
273 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
274 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
275 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
276 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
278 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
279 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
280 #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
281 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
284 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
285 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
286 #endif /* CONFIG_NAND_FSL_ELBC */
288 #define CONFIG_SYS_FLASH_EMPTY_INFO
289 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
290 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
292 #define CONFIG_BOARD_EARLY_INIT_F
293 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
294 #define CONFIG_MISC_INIT_R
296 #define CONFIG_HWCONFIG
298 /* define to use L1 as initial stack */
299 #define CONFIG_L1_INIT_RAM
300 #define CONFIG_SYS_INIT_RAM_LOCK
301 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
302 #ifdef CONFIG_PHYS_64BIT
303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
304 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
305 /* The assembler doesn't like typecast */
306 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
307 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
308 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
312 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
314 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
316 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
317 GENERATED_GBL_DATA_SIZE)
318 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
320 #define CONFIG_SYS_MONITOR_LEN (768 * 1024)
321 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
323 /* Serial Port - controlled on board with jumper J8
327 #define CONFIG_CONS_INDEX 1
328 #define CONFIG_SYS_NS16550
329 #define CONFIG_SYS_NS16550_SERIAL
330 #define CONFIG_SYS_NS16550_REG_SIZE 1
331 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
333 #define CONFIG_SYS_BAUDRATE_TABLE \
334 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
336 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
337 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
338 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
339 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
341 /* Use the HUSH parser */
342 #define CONFIG_SYS_HUSH_PARSER
344 /* pass open firmware flat tree */
345 #define CONFIG_OF_LIBFDT
346 #define CONFIG_OF_BOARD_SETUP
347 #define CONFIG_OF_STDOUT_VIA_ALIAS
349 /* new uImage format support */
351 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
354 #define CONFIG_SYS_I2C
355 #define CONFIG_SYS_I2C_FSL
356 #define CONFIG_SYS_FSL_I2C_SPEED 400000
357 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
358 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
359 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
360 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
361 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
366 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
367 #ifdef CONFIG_PHYS_64BIT
368 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
370 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
372 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
374 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
375 #ifdef CONFIG_PHYS_64BIT
376 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
378 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
380 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
383 * for slave u-boot IMAGE instored in master memory space,
384 * PHYS must be aligned based on the SIZE
386 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
387 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
388 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
389 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
391 * for slave UCODE and ENV instored in master memory space,
392 * PHYS must be aligned based on the SIZE
394 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
395 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
396 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
398 /* slave core release by master*/
399 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
400 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
403 * SRIO_PCIE_BOOT - SLAVE
405 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
406 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
407 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
408 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
412 * eSPI - Enhanced SPI
414 #define CONFIG_FSL_ESPI
415 #define CONFIG_SPI_FLASH_SPANSION
416 #define CONFIG_CMD_SF
417 #define CONFIG_SF_DEFAULT_SPEED 10000000
418 #define CONFIG_SF_DEFAULT_MODE 0
422 * Memory space is mapped 1-1, but I/O space must start from 0.
425 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
426 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
427 #ifdef CONFIG_PHYS_64BIT
428 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
429 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
431 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
432 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
434 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
435 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
436 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
437 #ifdef CONFIG_PHYS_64BIT
438 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
440 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
442 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
444 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
445 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
446 #ifdef CONFIG_PHYS_64BIT
447 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
448 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
450 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
451 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
453 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
454 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
455 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
456 #ifdef CONFIG_PHYS_64BIT
457 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
459 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
461 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
463 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
464 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
465 #ifdef CONFIG_PHYS_64BIT
466 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
467 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
469 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
470 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
472 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
473 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
474 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
475 #ifdef CONFIG_PHYS_64BIT
476 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
478 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
480 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
483 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
484 #define CONFIG_SYS_BMAN_NUM_PORTALS 10
485 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
486 #ifdef CONFIG_PHYS_64BIT
487 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
489 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
491 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
492 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
493 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
494 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
495 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
496 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
497 CONFIG_SYS_BMAN_CENA_SIZE)
498 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
499 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
500 #define CONFIG_SYS_QMAN_NUM_PORTALS 10
501 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
502 #ifdef CONFIG_PHYS_64BIT
503 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
505 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
507 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
508 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
509 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
510 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
511 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
512 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
513 CONFIG_SYS_QMAN_CENA_SIZE)
514 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
515 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
517 #define CONFIG_SYS_DPAA_FMAN
518 #define CONFIG_SYS_DPAA_PME
519 /* Default address of microcode for the Linux Fman driver */
520 #if defined(CONFIG_SPIFLASH)
522 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
523 * env, so we got 0x110000.
525 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
526 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
527 #elif defined(CONFIG_SDCARD)
529 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
530 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
531 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
533 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
534 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
535 #elif defined(CONFIG_NAND)
536 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
537 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
538 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
540 * Slave has no ucode locally, it can fetch this from remote. When implementing
541 * in two corenet boards, slave's ucode could be stored in master's memory
542 * space, the address can be mapped from slave TLB->slave LAW->
543 * slave SRIO or PCIE outbound window->master inbound window->
544 * master LAW->the ucode address in master's memory space.
546 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
547 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
549 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
550 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
552 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
553 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
555 #ifdef CONFIG_SYS_DPAA_FMAN
556 #define CONFIG_FMAN_ENET
557 #define CONFIG_PHYLIB_10G
558 #define CONFIG_PHY_VITESSE
559 #define CONFIG_PHY_TERANETICS
563 #define CONFIG_PCI_INDIRECT_BRIDGE
564 #define CONFIG_PCI_PNP /* do pci plug-and-play */
566 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
567 #define CONFIG_DOS_PARTITION
568 #endif /* CONFIG_PCI */
571 #define CONFIG_FSL_SATA_V2
573 #ifdef CONFIG_FSL_SATA_V2
574 #define CONFIG_FSL_SATA
575 #define CONFIG_LIBATA
577 #define CONFIG_SYS_SATA_MAX_DEVICE 2
579 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
580 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
582 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
583 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
586 #define CONFIG_CMD_SATA
587 #define CONFIG_DOS_PARTITION
588 #define CONFIG_CMD_EXT2
591 #ifdef CONFIG_FMAN_ENET
592 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
593 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
594 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
595 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
596 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
598 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
599 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
600 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
601 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
603 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
605 #define CONFIG_SYS_TBIPA_VALUE 8
606 #define CONFIG_MII /* MII PHY management */
607 #define CONFIG_ETHPRIME "FM1@DTSEC1"
608 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
614 #define CONFIG_LOADS_ECHO /* echo on for serial download */
615 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
618 * Command line configuration.
620 #define CONFIG_CMD_DHCP
621 #define CONFIG_CMD_ELF
622 #define CONFIG_CMD_ERRATA
623 #define CONFIG_CMD_GREPENV
624 #define CONFIG_CMD_IRQ
625 #define CONFIG_CMD_I2C
626 #define CONFIG_CMD_MII
627 #define CONFIG_CMD_PING
630 #define CONFIG_CMD_PCI
636 #define CONFIG_HAS_FSL_DR_USB
637 #define CONFIG_HAS_FSL_MPH_USB
639 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
640 #define CONFIG_CMD_USB
641 #define CONFIG_USB_STORAGE
642 #define CONFIG_USB_EHCI
643 #define CONFIG_USB_EHCI_FSL
644 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
647 #define CONFIG_CMD_EXT2
652 #define CONFIG_FSL_ESDHC
653 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
654 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
655 #define CONFIG_CMD_MMC
656 #define CONFIG_GENERIC_MMC
657 #define CONFIG_CMD_EXT2
658 #define CONFIG_CMD_FAT
659 #define CONFIG_DOS_PARTITION
662 /* Hash command with SHA acceleration supported in hardware */
663 #ifdef CONFIG_FSL_CAAM
664 #define CONFIG_CMD_HASH
665 #define CONFIG_SHA_HW_ACCEL
669 * Miscellaneous configurable options
671 #define CONFIG_SYS_LONGHELP /* undef to save memory */
672 #define CONFIG_CMDLINE_EDITING /* Command-line editing */
673 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */
674 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
675 #ifdef CONFIG_CMD_KGDB
676 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
678 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
680 /* Print Buffer Size */
681 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
682 sizeof(CONFIG_SYS_PROMPT)+16)
683 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
684 /* Boot Argument Buffer Size */
685 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
688 * For booting Linux, the board info and command line data
689 * have to be in the first 64 MB of memory, since this is
690 * the maximum mapped by the Linux kernel during initialization.
692 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
693 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
695 #ifdef CONFIG_CMD_KGDB
696 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
700 * Environment Configuration
702 #define CONFIG_ROOTPATH "/opt/nfsroot"
703 #define CONFIG_BOOTFILE "uImage"
704 #define CONFIG_UBOOTPATH u-boot.bin
706 /* default location for tftp and bootm */
707 #define CONFIG_LOADADDR 1000000
709 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
711 #define CONFIG_BAUDRATE 115200
713 #define __USB_PHY_TYPE utmi
715 #define CONFIG_EXTRA_ENV_SETTINGS \
716 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
717 "bank_intlv=cs0_cs1\0" \
719 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
720 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
721 "tftpflash=tftpboot $loadaddr $uboot && " \
722 "protect off $ubootaddr +$filesize && " \
723 "erase $ubootaddr +$filesize && " \
724 "cp.b $loadaddr $ubootaddr $filesize && " \
725 "protect on $ubootaddr +$filesize && " \
726 "cmp.b $loadaddr $ubootaddr $filesize\0" \
727 "consoledev=ttyS0\0" \
728 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
729 "usb_dr_mode=host\0" \
730 "ramdiskaddr=2000000\0" \
731 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
733 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
736 #define CONFIG_HDBOOT \
737 "setenv bootargs root=/dev/$bdev rw " \
738 "console=$consoledev,$baudrate $othbootargs;" \
739 "tftp $loadaddr $bootfile;" \
740 "tftp $fdtaddr $fdtfile;" \
741 "bootm $loadaddr - $fdtaddr"
743 #define CONFIG_NFSBOOTCOMMAND \
744 "setenv bootargs root=/dev/nfs rw " \
745 "nfsroot=$serverip:$rootpath " \
746 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
747 "console=$consoledev,$baudrate $othbootargs;" \
748 "tftp $loadaddr $bootfile;" \
749 "tftp $fdtaddr $fdtfile;" \
750 "bootm $loadaddr - $fdtaddr"
752 #define CONFIG_RAMBOOTCOMMAND \
753 "setenv bootargs root=/dev/ram rw " \
754 "console=$consoledev,$baudrate $othbootargs;" \
755 "tftp $ramdiskaddr $ramdiskfile;" \
756 "tftp $loadaddr $bootfile;" \
757 "tftp $fdtaddr $fdtfile;" \
758 "bootm $loadaddr $ramdiskaddr $fdtaddr"
760 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
762 #include <asm/fsl_secure_boot.h>
764 #ifdef CONFIG_SECURE_BOOT
765 #define CONFIG_CMD_BLOB
768 #endif /* __CONFIG_H */