include/configs/MPC8349EMDS.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2006-2010
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  */
   6
   7 /*
   8  * mpc8349emds board configuration file
   9  *
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  */
  18 #define CONFIG_E300             1       /* E300 Family */
  19
  20 #define CONFIG_SYS_IMMR         0xE0000000
  21
  22 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
  23 #define CONFIG_SYS_MEMTEST_START        0x00000000      /* memtest region */
  24 #define CONFIG_SYS_MEMTEST_END          0x00100000
  25
  26 /*
  27  * DDR Setup
  28  */
  29 #define CONFIG_DDR_ECC                  /* support DDR ECC function */
  30 #define CONFIG_DDR_ECC_CMD              /* use DDR ECC user commands */
  31 #define CONFIG_SPD_EEPROM               /* use SPD EEPROM for DDR setup*/
  32
  33 /*
  34  * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
  35  * unselect it to use old spd_sdram.c
  36  */
  37 #define CONFIG_SYS_SPD_BUS_NUM  0
  38 #define SPD_EEPROM_ADDRESS1     0x52
  39 #define SPD_EEPROM_ADDRESS2     0x51
  40 #define CONFIG_DIMM_SLOTS_PER_CTLR      2
  41 #define CONFIG_CHIP_SELECTS_PER_CTRL    (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  42 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  43 #define CONFIG_MEM_INIT_VALUE   0xDeadBeef
  44
  45 /*
  46  * 32-bit data path mode.
  47  *
  48  * Please note that using this mode for devices with the real density of 64-bit
  49  * effectively reduces the amount of available memory due to the effect of
  50  * wrapping around while translating address to row/columns, for example in the
  51  * 256MB module the upper 128MB get aliased with contents of the lower
  52  * 128MB); normally this define should be used for devices with real 32-bit
  53  * data path.
  54  */
  55 #undef CONFIG_DDR_32BIT
  56
  57 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory*/
  58 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  59 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  60 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN \
  61                                         | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  62 #undef  CONFIG_DDR_2T_TIMING
  63
  64 /*
  65  * DDRCDR - DDR Control Driver Register
  66  */
  67 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
  68
  69 #if defined(CONFIG_SPD_EEPROM)
  70 /*
  71  * Determine DDR configuration from I2C interface.
  72  */
  73 #define SPD_EEPROM_ADDRESS      0x51            /* DDR DIMM */
  74 #else
  75 /*
  76  * Manually set up DDR parameters
  77  */
  78 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  79 #if defined(CONFIG_DDR_II)
  80 #define CONFIG_SYS_DDRCDR               0x80080001
  81 #define CONFIG_SYS_DDR_CS2_BNDS         0x0000000f
  82 #define CONFIG_SYS_DDR_CS2_CONFIG       0x80330102
  83 #define CONFIG_SYS_DDR_TIMING_0         0x00220802
  84 #define CONFIG_SYS_DDR_TIMING_1         0x38357322
  85 #define CONFIG_SYS_DDR_TIMING_2         0x2f9048c8
  86 #define CONFIG_SYS_DDR_TIMING_3         0x00000000
  87 #define CONFIG_SYS_DDR_CLK_CNTL         0x02000000
  88 #define CONFIG_SYS_DDR_MODE             0x47d00432
  89 #define CONFIG_SYS_DDR_MODE2            0x8000c000
  90 #define CONFIG_SYS_DDR_INTERVAL         0x03cf0080
  91 #define CONFIG_SYS_DDR_SDRAM_CFG        0x43000000
  92 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  93 #else
  94 #define CONFIG_SYS_DDR_CS2_CONFIG       (CSCONFIG_EN \
  95                                 | CSCONFIG_ROW_BIT_13 \
  96                                 | CSCONFIG_COL_BIT_10)
  97 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
  98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800      /* P9-45,may need tuning */
  99 #define CONFIG_SYS_DDR_CONTROL  0xc2000000      /* unbuffered,no DYN_PWR */
 100 #define CONFIG_SYS_DDR_INTERVAL 0x04060100      /* autocharge,no open page */
 101
 102 #if defined(CONFIG_DDR_32BIT)
 103 /* set burst length to 8 for 32-bit data path */
 104                                 /* DLL,normal,seq,4/2.5, 8 burst len */
 105 #define CONFIG_SYS_DDR_MODE     0x00000023
 106 #else
 107 /* the default burst length is 4 - for 64-bit data path */
 108                                 /* DLL,normal,seq,4/2.5, 4 burst len */
 109 #define CONFIG_SYS_DDR_MODE     0x00000022
 110 #endif
 111 #endif
 112 #endif
 113
 114 /*
 115  * SDRAM on the Local Bus
 116  */
 117 #define CONFIG_SYS_LBC_SDRAM_BASE       0xF0000000      /* Localbus SDRAM */
 118 #define CONFIG_SYS_LBC_SDRAM_SIZE       64              /* LBC SDRAM is 64MB */
 119
 120 /*
 121  * FLASH on the Local Bus
 122  */
 123 #define CONFIG_SYS_FLASH_BASE           0xFE000000      /* start of FLASH   */
 124 #define CONFIG_SYS_FLASH_SIZE           32      /* max flash size in MB */
 125
 126 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 127                                 | BR_PS_16      /* 16 bit port  */ \
 128                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 129                                 | BR_V)         /* valid */
 130 #define CONFIG_SYS_OR0_PRELIM   (OR_AM_32MB \
 131                                 | OR_UPM_XAM \
 132                                 | OR_GPCM_CSNT \
 133                                 | OR_GPCM_ACS_DIV2 \
 134                                 | OR_GPCM_XACS \
 135                                 | OR_GPCM_SCY_15 \
 136                                 | OR_GPCM_TRLX_SET \
 137                                 | OR_GPCM_EHTR_SET \
 138                                 | OR_GPCM_EAD)
 139
 140 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 141 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max sectors per device */
 142
 143 #undef CONFIG_SYS_FLASH_CHECKSUM
 144 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 145 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 146
 147 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 148
 149 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 150 #define CONFIG_SYS_RAMBOOT
 151 #else
 152 #undef  CONFIG_SYS_RAMBOOT
 153 #endif
 154
 155 /*
 156  * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
 157  */
 158 #define CONFIG_SYS_BCSR                 0xE2400000
 159                                         /* Access window base at BCSR base */
 160 #define CONFIG_SYS_BR1_PRELIM           (CONFIG_SYS_BCSR \
 161                                         | BR_PS_8 \
 162                                         | BR_MS_GPCM \
 163                                         | BR_V)
 164                                         /* 0x00000801 */
 165 #define CONFIG_SYS_OR1_PRELIM           (OR_AM_32KB \
 166                                         | OR_GPCM_XAM \
 167                                         | OR_GPCM_CSNT \
 168                                         | OR_GPCM_SCY_15 \
 169                                         | OR_GPCM_TRLX_CLEAR \
 170                                         | OR_GPCM_EHTR_CLEAR)
 171                                         /* 0xFFFFE8F0 */
 172
 173 #define CONFIG_SYS_INIT_RAM_LOCK        1
 174 #define CONFIG_SYS_INIT_RAM_ADDR        0xFD000000      /* Initial RAM addr */
 175 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000  /* Size of used area in RAM*/
 176
 177 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 178                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 179 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 180
 181 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 182 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 183
 184 /*
 185  * Local Bus LCRR and LBCR regs
 186  *    LCRR:  DLL bypass, Clock divider is 4
 187  * External Local Bus rate is
 188  *    CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
 189  */
 190 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 191 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 192 #define CONFIG_SYS_LBC_LBCR     0x00000000
 193
 194 /*
 195  * Serial Port
 196  */
 197 #define CONFIG_SYS_NS16550_SERIAL
 198 #define CONFIG_SYS_NS16550_REG_SIZE    1
 199 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 200
 201 #define CONFIG_SYS_BAUDRATE_TABLE  \
 202                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 203
 204 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_IMMR+0x4500)
 205 #define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_IMMR+0x4600)
 206
 207 /* I2C */
 208 #define CONFIG_SYS_I2C
 209 #define CONFIG_SYS_I2C_FSL
 210 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 211 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 212 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 213 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 214 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 215 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 216 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x69} }
 217
 218 /* SPI */
 219 #undef CONFIG_SOFT_SPI                  /* SPI bit-banged */
 220
 221 /* GPIOs.  Used as SPI chip selects */
 222 #define CONFIG_SYS_GPIO1_PRELIM
 223 #define CONFIG_SYS_GPIO1_DIR            0xC0000000  /* SPI CS on 0, LED on 1 */
 224 #define CONFIG_SYS_GPIO1_DAT            0xC0000000  /* Both are active LOW */
 225
 226 /* TSEC */
 227 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 228 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 229 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
 230 #define CONFIG_SYS_TSEC2        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
 231
 232 /* USB */
 233 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY       1 /* Use SYS board PHY */
 234
 235 /*
 236  * General PCI
 237  * Addresses are mapped 1-1.
 238  */
 239 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 240 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 241 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 242 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 243 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 244 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 245 #define CONFIG_SYS_PCI1_IO_BASE         0x00000000
 246 #define CONFIG_SYS_PCI1_IO_PHYS         0xE2000000
 247 #define CONFIG_SYS_PCI1_IO_SIZE         0x00100000      /* 1M */
 248
 249 #define CONFIG_SYS_PCI2_MEM_BASE        0xA0000000
 250 #define CONFIG_SYS_PCI2_MEM_PHYS        CONFIG_SYS_PCI2_MEM_BASE
 251 #define CONFIG_SYS_PCI2_MEM_SIZE        0x10000000      /* 256M */
 252 #define CONFIG_SYS_PCI2_MMIO_BASE       0xB0000000
 253 #define CONFIG_SYS_PCI2_MMIO_PHYS       CONFIG_SYS_PCI2_MMIO_BASE
 254 #define CONFIG_SYS_PCI2_MMIO_SIZE       0x10000000      /* 256M */
 255 #define CONFIG_SYS_PCI2_IO_BASE         0x00000000
 256 #define CONFIG_SYS_PCI2_IO_PHYS         0xE2100000
 257 #define CONFIG_SYS_PCI2_IO_SIZE         0x00100000      /* 1M */
 258
 259 #if defined(CONFIG_PCI)
 260
 261 #define CONFIG_83XX_PCI_STREAMING
 262
 263 #undef CONFIG_EEPRO100
 264 #undef CONFIG_TULIP
 265
 266 #if !defined(CONFIG_PCI_PNP)
 267         #define PCI_ENET0_IOADDR        0xFIXME
 268         #define PCI_ENET0_MEMADDR       0xFIXME
 269         #define PCI_IDSEL_NUMBER        0x0c    /* slot0->3(IDSEL)=12->15 */
 270 #endif
 271
 272 #undef CONFIG_PCI_SCAN_SHOW             /* show pci devices on startup */
 273 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 274
 275 #endif  /* CONFIG_PCI */
 276
 277 /*
 278  * TSEC configuration
 279  */
 280
 281 #if defined(CONFIG_TSEC_ENET)
 282
 283 #define CONFIG_GMII             1       /* MII PHY management */
 284 #define CONFIG_TSEC1            1
 285 #define CONFIG_TSEC1_NAME       "TSEC0"
 286 #define CONFIG_TSEC2            1
 287 #define CONFIG_TSEC2_NAME       "TSEC1"
 288 #define TSEC1_PHY_ADDR          0
 289 #define TSEC2_PHY_ADDR          1
 290 #define TSEC1_PHYIDX            0
 291 #define TSEC2_PHYIDX            0
 292 #define TSEC1_FLAGS             TSEC_GIGABIT
 293 #define TSEC2_FLAGS             TSEC_GIGABIT
 294
 295 /* Options are: TSEC[0-1] */
 296 #define CONFIG_ETHPRIME         "TSEC0"
 297
 298 #endif  /* CONFIG_TSEC_ENET */
 299
 300 /*
 301  * Configure on-board RTC
 302  */
 303 #define CONFIG_RTC_DS1374               /* use ds1374 rtc via i2c */
 304 #define CONFIG_SYS_I2C_RTC_ADDR 0x68    /* at address 0x68 */
 305
 306 /*
 307  * Environment
 308  */
 309 #ifndef CONFIG_SYS_RAMBOOT
 310         #define CONFIG_ENV_ADDR         \
 311                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 312         #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 313         #define CONFIG_ENV_SIZE         0x2000
 314
 315 /* Address and size of Redundant Environment Sector     */
 316 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 317 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 318
 319 #else
 320         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 321         #define CONFIG_ENV_SIZE         0x2000
 322 #endif
 323
 324 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 325 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 326
 327 /*
 328  * BOOTP options
 329  */
 330 #define CONFIG_BOOTP_BOOTFILESIZE
 331
 332 /*
 333  * Command line configuration.
 334  */
 335
 336 #undef CONFIG_WATCHDOG                  /* watchdog disabled */
 337
 338 /*
 339  * Miscellaneous configurable options
 340  */
 341 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 342
 343 /*
 344  * For booting Linux, the board info and command line data
 345  * have to be in the first 256 MB of memory, since this is
 346  * the maximum mapped by the Linux kernel during initialization.
 347  */
 348                                 /* Initial Memory map for Linux*/
 349 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20)
 350 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 351
 352 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST  */
 353
 354 /*
 355  * System performance
 356  */
 357 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
 358 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
 359 #define CONFIG_SYS_SPCR_TSEC1EP 3       /* TSEC1 emergency priority (0-3) */
 360 #define CONFIG_SYS_SPCR_TSEC2EP 3       /* TSEC2 emergency priority (0-3) */
 361 #define CONFIG_SYS_SCCR_TSEC1CM 1       /* TSEC1 clock mode (0-3) */
 362 #define CONFIG_SYS_SCCR_TSEC2CM 1       /* TSEC2 & I2C0 clock mode (0-3) */
 363
 364 /* System IO Config */
 365 #define CONFIG_SYS_SICRH 0
 366 #define CONFIG_SYS_SICRL SICRL_LDP_A
 367
 368 #define CONFIG_SYS_HID0_INIT    0x000000000
 369 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK \
 370                                 | HID0_ENABLE_INSTRUCTION_CACHE)
 371
 372 /* #define CONFIG_SYS_HID0_FINAL        (\
 373         HID0_ENABLE_INSTRUCTION_CACHE |\
 374         HID0_ENABLE_M_BIT |\
 375         HID0_ENABLE_ADDRESS_BROADCAST) */
 376
 377 #define CONFIG_SYS_HID2 HID2_HBE
 378
 379 #ifdef CONFIG_PCI
 380 #define CONFIG_PCI_INDIRECT_BRIDGE
 381 #endif
 382
 383 #if defined(CONFIG_CMD_KGDB)
 384 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 385 #endif
 386
 387 /*
 388  * Environment Configuration
 389  */
 390 #define CONFIG_ENV_OVERWRITE
 391
 392 #if defined(CONFIG_TSEC_ENET)
 393 #define CONFIG_HAS_ETH1
 394 #define CONFIG_HAS_ETH0
 395 #endif
 396
 397 #define CONFIG_HOSTNAME         "mpc8349emds"
 398 #define CONFIG_ROOTPATH         "/nfsroot/rootfs"
 399 #define CONFIG_BOOTFILE         "uImage"
 400
 401 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 402
 403 #define CONFIG_PREBOOT  "echo;" \
 404         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 405         "echo"
 406
 407 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 408         "netdev=eth0\0"                                                 \
 409         "hostname=mpc8349emds\0"                                        \
 410         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 411                 "nfsroot=${serverip}:${rootpath}\0"                     \
 412         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 413         "addip=setenv bootargs ${bootargs} "                            \
 414                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 415                 ":${hostname}:${netdev}:off panic=1\0"                  \
 416         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 417         "flash_nfs=run nfsargs addip addtty;"                           \
 418                 "bootm ${kernel_addr}\0"                                \
 419         "flash_self=run ramargs addip addtty;"                          \
 420                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 421         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 422                 "bootm\0"                                               \
 423         "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0"           \
 424         "update=protect off fe000000 fe03ffff; "                        \
 425                 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
 426         "upd=run load update\0"                                         \
 427         "fdtaddr=780000\0"                                              \
 428         "fdtfile=mpc834x_mds.dtb\0"                                     \
 429         ""
 430
 431 #define CONFIG_NFSBOOTCOMMAND                                           \
 432         "setenv bootargs root=/dev/nfs rw "                             \
 433                 "nfsroot=$serverip:$rootpath "                          \
 434                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"   \
 435                                                         "$netdev:off "  \
 436                 "console=$consoledev,$baudrate $othbootargs;"           \
 437         "tftp $loadaddr $bootfile;"                                     \
 438         "tftp $fdtaddr $fdtfile;"                                       \
 439         "bootm $loadaddr - $fdtaddr"
 440
 441 #define CONFIG_RAMBOOTCOMMAND                                           \
 442         "setenv bootargs root=/dev/ram rw "                             \
 443                 "console=$consoledev,$baudrate $othbootargs;"           \
 444         "tftp $ramdiskaddr $ramdiskfile;"                               \
 445         "tftp $loadaddr $bootfile;"                                     \
 446         "tftp $fdtaddr $fdtfile;"                                       \
 447         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 448
 449 #define CONFIG_BOOTCOMMAND      "run flash_self"
 450
 451 #endif  /* __CONFIG_H */