1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2006-2010
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 * mpc8349emds board configuration file
16 * High Level Configuration Options
18 #define CONFIG_E300 1 /* E300 Family */
20 #define CONFIG_SYS_IMMR 0xE0000000
22 #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
23 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
24 #define CONFIG_SYS_MEMTEST_END 0x00100000
29 #define CONFIG_DDR_ECC /* support DDR ECC function */
30 #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */
31 #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/
34 * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver
35 * unselect it to use old spd_sdram.c
37 #define CONFIG_SYS_SPD_BUS_NUM 0
38 #define SPD_EEPROM_ADDRESS1 0x52
39 #define SPD_EEPROM_ADDRESS2 0x51
40 #define CONFIG_DIMM_SLOTS_PER_CTLR 2
41 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
42 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
43 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
46 * 32-bit data path mode.
48 * Please note that using this mode for devices with the real density of 64-bit
49 * effectively reduces the amount of available memory due to the effect of
50 * wrapping around while translating address to row/columns, for example in the
51 * 256MB module the upper 128MB get aliased with contents of the lower
52 * 128MB); normally this define should be used for devices with real 32-bit
55 #undef CONFIG_DDR_32BIT
57 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
58 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
59 #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
60 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
61 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
62 #undef CONFIG_DDR_2T_TIMING
65 * DDRCDR - DDR Control Driver Register
67 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
69 #if defined(CONFIG_SPD_EEPROM)
71 * Determine DDR configuration from I2C interface.
73 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
76 * Manually set up DDR parameters
78 #define CONFIG_SYS_DDR_SIZE 256 /* MB */
79 #if defined(CONFIG_DDR_II)
80 #define CONFIG_SYS_DDRCDR 0x80080001
81 #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f
82 #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102
83 #define CONFIG_SYS_DDR_TIMING_0 0x00220802
84 #define CONFIG_SYS_DDR_TIMING_1 0x38357322
85 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8
86 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
87 #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000
88 #define CONFIG_SYS_DDR_MODE 0x47d00432
89 #define CONFIG_SYS_DDR_MODE2 0x8000c000
90 #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080
91 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
92 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
94 #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \
95 | CSCONFIG_ROW_BIT_13 \
96 | CSCONFIG_COL_BIT_10)
97 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
99 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
100 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
102 #if defined(CONFIG_DDR_32BIT)
103 /* set burst length to 8 for 32-bit data path */
104 /* DLL,normal,seq,4/2.5, 8 burst len */
105 #define CONFIG_SYS_DDR_MODE 0x00000023
107 /* the default burst length is 4 - for 64-bit data path */
108 /* DLL,normal,seq,4/2.5, 4 burst len */
109 #define CONFIG_SYS_DDR_MODE 0x00000022
115 * SDRAM on the Local Bus
117 #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */
118 #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
121 * FLASH on the Local Bus
123 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */
124 #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */
126 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
127 | BR_PS_16 /* 16 bit port */ \
128 | BR_MS_GPCM /* MSEL = GPCM */ \
130 #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
140 /* window base at flash base */
141 #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
142 #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
144 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
145 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
147 #undef CONFIG_SYS_FLASH_CHECKSUM
148 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
149 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
151 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
153 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
154 #define CONFIG_SYS_RAMBOOT
156 #undef CONFIG_SYS_RAMBOOT
160 * BCSR register on local bus 32KB, 8-bit wide for MDS config reg
162 #define CONFIG_SYS_BCSR 0xE2400000
163 /* Access window base at BCSR base */
164 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
165 #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
166 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
171 #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
175 | OR_GPCM_TRLX_CLEAR \
176 | OR_GPCM_EHTR_CLEAR)
179 #define CONFIG_SYS_INIT_RAM_LOCK 1
180 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */
181 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
183 #define CONFIG_SYS_GBL_DATA_OFFSET \
184 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
185 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
187 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
188 #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
191 * Local Bus LCRR and LBCR regs
192 * LCRR: DLL bypass, Clock divider is 4
193 * External Local Bus rate is
194 * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV
196 #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
197 #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
198 #define CONFIG_SYS_LBC_LBCR 0x00000000
203 #define CONFIG_SYS_NS16550_SERIAL
204 #define CONFIG_SYS_NS16550_REG_SIZE 1
205 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
207 #define CONFIG_SYS_BAUDRATE_TABLE \
208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
210 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
211 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
214 #define CONFIG_SYS_I2C
215 #define CONFIG_SYS_I2C_FSL
216 #define CONFIG_SYS_FSL_I2C_SPEED 400000
217 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
218 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
219 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
220 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
221 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
222 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
225 #undef CONFIG_SOFT_SPI /* SPI bit-banged */
227 /* GPIOs. Used as SPI chip selects */
228 #define CONFIG_SYS_GPIO1_PRELIM
229 #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */
230 #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */
233 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
234 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
235 #define CONFIG_SYS_TSEC2_OFFSET 0x25000
236 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
239 #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */
243 * Addresses are mapped 1-1.
245 #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
246 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
247 #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
248 #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
249 #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
250 #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
251 #define CONFIG_SYS_PCI1_IO_BASE 0x00000000
252 #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
253 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
255 #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000
256 #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
257 #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */
258 #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000
259 #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE
260 #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */
261 #define CONFIG_SYS_PCI2_IO_BASE 0x00000000
262 #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000
263 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
265 #if defined(CONFIG_PCI)
267 #define CONFIG_83XX_PCI_STREAMING
269 #undef CONFIG_EEPRO100
272 #if !defined(CONFIG_PCI_PNP)
273 #define PCI_ENET0_IOADDR 0xFIXME
274 #define PCI_ENET0_MEMADDR 0xFIXME
275 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
278 #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
279 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
281 #endif /* CONFIG_PCI */
287 #if defined(CONFIG_TSEC_ENET)
289 #define CONFIG_GMII 1 /* MII PHY management */
290 #define CONFIG_TSEC1 1
291 #define CONFIG_TSEC1_NAME "TSEC0"
292 #define CONFIG_TSEC2 1
293 #define CONFIG_TSEC2_NAME "TSEC1"
294 #define TSEC1_PHY_ADDR 0
295 #define TSEC2_PHY_ADDR 1
296 #define TSEC1_PHYIDX 0
297 #define TSEC2_PHYIDX 0
298 #define TSEC1_FLAGS TSEC_GIGABIT
299 #define TSEC2_FLAGS TSEC_GIGABIT
301 /* Options are: TSEC[0-1] */
302 #define CONFIG_ETHPRIME "TSEC0"
304 #endif /* CONFIG_TSEC_ENET */
307 * Configure on-board RTC
309 #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
310 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
315 #ifndef CONFIG_SYS_RAMBOOT
316 #define CONFIG_ENV_ADDR \
317 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
318 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
319 #define CONFIG_ENV_SIZE 0x2000
321 /* Address and size of Redundant Environment Sector */
322 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
323 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
326 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
327 #define CONFIG_ENV_SIZE 0x2000
330 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
331 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
336 #define CONFIG_BOOTP_BOOTFILESIZE
339 * Command line configuration.
342 #undef CONFIG_WATCHDOG /* watchdog disabled */
345 * Miscellaneous configurable options
347 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
350 * For booting Linux, the board info and command line data
351 * have to be in the first 256 MB of memory, since this is
352 * the maximum mapped by the Linux kernel during initialization.
354 /* Initial Memory map for Linux*/
355 #define CONFIG_SYS_BOOTMAPSZ (256 << 20)
356 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
358 #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
363 #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
364 #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
365 #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */
366 #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */
367 #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */
368 #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */
370 /* System IO Config */
371 #define CONFIG_SYS_SICRH 0
372 #define CONFIG_SYS_SICRL SICRL_LDP_A
374 #define CONFIG_SYS_HID0_INIT 0x000000000
375 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
376 | HID0_ENABLE_INSTRUCTION_CACHE)
378 /* #define CONFIG_SYS_HID0_FINAL (\
379 HID0_ENABLE_INSTRUCTION_CACHE |\
381 HID0_ENABLE_ADDRESS_BROADCAST) */
383 #define CONFIG_SYS_HID2 HID2_HBE
384 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
386 /* DDR @ 0x00000000 */
387 #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
390 #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
395 /* PCI @ 0x80000000 */
397 #define CONFIG_PCI_INDIRECT_BRIDGE
398 #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \
401 #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \
405 #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \
407 | BATL_CACHEINHIBIT \
408 | BATL_GUARDEDSTORAGE)
409 #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \
414 #define CONFIG_SYS_IBAT1L (0)
415 #define CONFIG_SYS_IBAT1U (0)
416 #define CONFIG_SYS_IBAT2L (0)
417 #define CONFIG_SYS_IBAT2U (0)
420 #ifdef CONFIG_MPC83XX_PCI2
421 #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \
424 #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \
428 #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \
430 | BATL_CACHEINHIBIT \
431 | BATL_GUARDEDSTORAGE)
432 #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \
437 #define CONFIG_SYS_IBAT3L (0)
438 #define CONFIG_SYS_IBAT3U (0)
439 #define CONFIG_SYS_IBAT4L (0)
440 #define CONFIG_SYS_IBAT4U (0)
443 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
444 #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
446 | BATL_CACHEINHIBIT \
447 | BATL_GUARDEDSTORAGE)
448 #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
453 /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
454 #define CONFIG_SYS_IBAT6L (0xF0000000 \
456 | BATL_MEMCOHERENCE \
457 | BATL_GUARDEDSTORAGE)
458 #define CONFIG_SYS_IBAT6U (0xF0000000 \
463 #define CONFIG_SYS_IBAT7L (0)
464 #define CONFIG_SYS_IBAT7U (0)
466 #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
467 #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
468 #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
469 #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
470 #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
471 #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
472 #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
473 #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
474 #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
475 #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
476 #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
477 #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
478 #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
479 #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
480 #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
481 #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
483 #if defined(CONFIG_CMD_KGDB)
484 #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
488 * Environment Configuration
490 #define CONFIG_ENV_OVERWRITE
492 #if defined(CONFIG_TSEC_ENET)
493 #define CONFIG_HAS_ETH1
494 #define CONFIG_HAS_ETH0
497 #define CONFIG_HOSTNAME "mpc8349emds"
498 #define CONFIG_ROOTPATH "/nfsroot/rootfs"
499 #define CONFIG_BOOTFILE "uImage"
501 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
503 #define CONFIG_PREBOOT "echo;" \
504 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
507 #define CONFIG_EXTRA_ENV_SETTINGS \
509 "hostname=mpc8349emds\0" \
510 "nfsargs=setenv bootargs root=/dev/nfs rw " \
511 "nfsroot=${serverip}:${rootpath}\0" \
512 "ramargs=setenv bootargs root=/dev/ram rw\0" \
513 "addip=setenv bootargs ${bootargs} " \
514 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
515 ":${hostname}:${netdev}:off panic=1\0" \
516 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
517 "flash_nfs=run nfsargs addip addtty;" \
518 "bootm ${kernel_addr}\0" \
519 "flash_self=run ramargs addip addtty;" \
520 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
521 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
523 "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \
524 "update=protect off fe000000 fe03ffff; " \
525 "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\
526 "upd=run load update\0" \
528 "fdtfile=mpc834x_mds.dtb\0" \
531 #define CONFIG_NFSBOOTCOMMAND \
532 "setenv bootargs root=/dev/nfs rw " \
533 "nfsroot=$serverip:$rootpath " \
534 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
536 "console=$consoledev,$baudrate $othbootargs;" \
537 "tftp $loadaddr $bootfile;" \
538 "tftp $fdtaddr $fdtfile;" \
539 "bootm $loadaddr - $fdtaddr"
541 #define CONFIG_RAMBOOTCOMMAND \
542 "setenv bootargs root=/dev/ram rw " \
543 "console=$consoledev,$baudrate $othbootargs;" \
544 "tftp $ramdiskaddr $ramdiskfile;" \
545 "tftp $loadaddr $bootfile;" \
546 "tftp $fdtaddr $fdtfile;" \
547 "bootm $loadaddr $ramdiskaddr $fdtaddr"
549 #define CONFIG_BOOTCOMMAND "run flash_self"
551 #endif /* __CONFIG_H */