include/configs/MPC8323ERDB.h

   1 /*
   2  * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published
   6  * by the Free Software Foundation.
   7  */
   8
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 /*
  13  * High Level Configuration Options
  14  */
  15 #define CONFIG_E300             1       /* E300 family */
  16 #define CONFIG_QE               1       /* Has QE */
  17
  18 /*
  19  * System IO Config
  20  */
  21 #define CONFIG_SYS_SICRL                0x00000000
  22
  23 /*
  24  * IMMR new address
  25  */
  26 #define CONFIG_SYS_IMMR         0xE0000000
  27
  28 /*
  29  * System performance
  30  */
  31 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* Arbiter pipeline depth (0-3) */
  32 #define CONFIG_SYS_ACR_RPTCNT   3       /* Arbiter repeat count (0-7) */
  33 /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
  34 #define CONFIG_SYS_SPCR_OPT     1
  35
  36 /*
  37  * DDR Setup
  38  */
  39 #define CONFIG_SYS_DDR_BASE     0x00000000      /* DDR is system memory */
  40 #define CONFIG_SYS_SDRAM_BASE   CONFIG_SYS_DDR_BASE
  41 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  42
  43 #undef CONFIG_SPD_EEPROM
  44 #if defined(CONFIG_SPD_EEPROM)
  45 /* Determine DDR configuration from I2C interface
  46  */
  47 #define SPD_EEPROM_ADDRESS      0x51    /* DDR SODIMM */
  48 #else
  49 /* Manually set up DDR parameters
  50  */
  51 #define CONFIG_SYS_DDR_SIZE     64      /* MB */
  52 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  53                                 | CSCONFIG_ROW_BIT_13 \
  54                                 | CSCONFIG_COL_BIT_9)
  55                                 /* 0x80010101 */
  56 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  57                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  58                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  59                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  60                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  61                                 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  62                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  63                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  64                                 /* 0x00220802 */
  65 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  66                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  67                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  68                                 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
  69                                 | (3 << TIMING_CFG1_REFREC_SHIFT) \
  70                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  71                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  72                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  73                                 /* 0x26253222 */
  74 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
  75                                 | (31 << TIMING_CFG2_CPO_SHIFT) \
  76                                 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  77                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  78                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  79                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  80                                 | (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
  81                                 /* 0x1f9048c7 */
  82 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
  83 #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  84                                 /* 0x02000000 */
  85 #define CONFIG_SYS_DDR_MODE     ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
  86                                 | (0x0232 << SDRAM_MODE_SD_SHIFT))
  87                                 /* 0x44480232 */
  88 #define CONFIG_SYS_DDR_MODE2    0x8000c000
  89 #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
  90                                 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  91                                 /* 0x03200064 */
  92 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
  93 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  94                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  95                                 | SDRAM_CFG_32_BE)
  96                                 /* 0x43080000 */
  97 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
  98 #endif
  99
 100 /*
 101  * Memory test
 102  */
 103 #undef CONFIG_SYS_DRAM_TEST             /* memory test, takes time */
 104 #define CONFIG_SYS_MEMTEST_START        0x00030000      /* memtest region */
 105 #define CONFIG_SYS_MEMTEST_END          0x03f00000
 106
 107 /*
 108  * The reserved memory
 109  */
 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 111
 112 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 113 #define CONFIG_SYS_RAMBOOT
 114 #else
 115 #undef  CONFIG_SYS_RAMBOOT
 116 #endif
 117
 118 /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
 119 #define CONFIG_SYS_MONITOR_LEN  (512 * 1024)    /* Reserve 512 kB for Mon */
 120 #define CONFIG_SYS_MALLOC_LEN   (256 * 1024)    /* Reserved for malloc */
 121
 122 /*
 123  * Initial RAM Base Address Setup
 124  */
 125 #define CONFIG_SYS_INIT_RAM_LOCK        1
 126 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 127 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 128 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 129                         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 130
 131 /*
 132  * Local Bus Configuration & Clock Setup
 133  */
 134 #define CONFIG_SYS_LCRR_DBYP            LCRR_DBYP
 135 #define CONFIG_SYS_LCRR_CLKDIV          LCRR_CLKDIV_2
 136 #define CONFIG_SYS_LBC_LBCR             0x00000000
 137
 138 /*
 139  * FLASH on the Local Bus
 140  */
 141 #define CONFIG_SYS_FLASH_BASE   0xFE000000      /* FLASH base address */
 142 #define CONFIG_SYS_FLASH_SIZE           16      /* FLASH size is 16M */
 143
 144                                         /* Window base at flash base */
 145 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 146 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_32MB)
 147
 148 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE \
 149                                 | BR_PS_16      /* 16 bit port */ \
 150                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 151                                 | BR_V)         /* valid */
 152 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
 153                                 | OR_GPCM_XAM \
 154                                 | OR_GPCM_CSNT \
 155                                 | OR_GPCM_ACS_DIV2 \
 156                                 | OR_GPCM_XACS \
 157                                 | OR_GPCM_SCY_15 \
 158                                 | OR_GPCM_TRLX_SET \
 159                                 | OR_GPCM_EHTR_SET \
 160                                 | OR_GPCM_EAD)
 161                                 /* 0xFE006FF7 */
 162
 163 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 164 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* sectors per device */
 165
 166 #undef CONFIG_SYS_FLASH_CHECKSUM
 167
 168 /*
 169  * Serial Port
 170  */
 171 #define CONFIG_SYS_NS16550_SERIAL
 172 #define CONFIG_SYS_NS16550_REG_SIZE     1
 173 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 174
 175 #define CONFIG_SYS_BAUDRATE_TABLE  \
 176                 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 177
 178 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 179 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 180
 181 /* I2C */
 182 #define CONFIG_SYS_I2C
 183 #define CONFIG_SYS_I2C_FSL
 184 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 185 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 186 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 187 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x51} }
 188
 189 /*
 190  * Config on-board EEPROM
 191  */
 192 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50
 193 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 194 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 195 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 196
 197 /*
 198  * General PCI
 199  * Addresses are mapped 1-1.
 200  */
 201 #define CONFIG_SYS_PCI1_MEM_BASE        0x80000000
 202 #define CONFIG_SYS_PCI1_MEM_PHYS        CONFIG_SYS_PCI1_MEM_BASE
 203 #define CONFIG_SYS_PCI1_MEM_SIZE        0x10000000      /* 256M */
 204 #define CONFIG_SYS_PCI1_MMIO_BASE       0x90000000
 205 #define CONFIG_SYS_PCI1_MMIO_PHYS       CONFIG_SYS_PCI1_MMIO_BASE
 206 #define CONFIG_SYS_PCI1_MMIO_SIZE       0x10000000      /* 256M */
 207 #define CONFIG_SYS_PCI1_IO_BASE         0xd0000000
 208 #define CONFIG_SYS_PCI1_IO_PHYS         CONFIG_SYS_PCI1_IO_BASE
 209 #define CONFIG_SYS_PCI1_IO_SIZE         0x04000000      /* 64M */
 210
 211 #ifdef CONFIG_PCI
 212 #define CONFIG_PCI_INDIRECT_BRIDGE
 213 #define CONFIG_PCI_SKIP_HOST_BRIDGE
 214
 215 #undef CONFIG_EEPRO100
 216 #undef CONFIG_PCI_SCAN_SHOW     /* show pci devices on startup */
 217 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  0x1957  /* Freescale */
 218
 219 #endif  /* CONFIG_PCI */
 220
 221 /*
 222  * QE UEC ethernet configuration
 223  */
 224 #define CONFIG_UEC_ETH
 225 #define CONFIG_ETHPRIME         "UEC0"
 226
 227 #define CONFIG_UEC_ETH1         /* ETH3 */
 228
 229 #ifdef CONFIG_UEC_ETH1
 230 #define CONFIG_SYS_UEC1_UCC_NUM 2       /* UCC3 */
 231 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK9
 232 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK10
 233 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 234 #define CONFIG_SYS_UEC1_PHY_ADDR        4
 235 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 236 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 237 #endif
 238
 239 #define CONFIG_UEC_ETH2         /* ETH4 */
 240
 241 #ifdef CONFIG_UEC_ETH2
 242 #define CONFIG_SYS_UEC2_UCC_NUM 1       /* UCC2 */
 243 #define CONFIG_SYS_UEC2_RX_CLK          QE_CLK16
 244 #define CONFIG_SYS_UEC2_TX_CLK          QE_CLK3
 245 #define CONFIG_SYS_UEC2_ETH_TYPE        FAST_ETH
 246 #define CONFIG_SYS_UEC2_PHY_ADDR        0
 247 #define CONFIG_SYS_UEC2_INTERFACE_TYPE  PHY_INTERFACE_MODE_MII
 248 #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
 249 #endif
 250
 251 /*
 252  * Environment
 253  */
 254 #ifndef CONFIG_SYS_RAMBOOT
 255         #define CONFIG_ENV_ADDR         \
 256                         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 257         #define CONFIG_ENV_SECT_SIZE    0x20000
 258         #define CONFIG_ENV_SIZE         0x2000
 259 #else
 260         #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 261         #define CONFIG_ENV_SIZE         0x2000
 262 #endif
 263
 264 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 265 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 266
 267 /*
 268  * BOOTP options
 269  */
 270 #define CONFIG_BOOTP_BOOTFILESIZE
 271
 272 /*
 273  * Command line configuration.
 274  */
 275
 276 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 277
 278 /*
 279  * Miscellaneous configurable options
 280  */
 281 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 282
 283 /*
 284  * For booting Linux, the board info and command line data
 285  * have to be in the first 256 MB of memory, since this is
 286  * the maximum mapped by the Linux kernel during initialization.
 287  */
 288                                         /* Initial Memory map for Linux */
 289 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 290 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 291
 292 /*
 293  * Core HID Setup
 294  */
 295 #define CONFIG_SYS_HID0_INIT    0x000000000
 296 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | \
 297                                  HID0_ENABLE_INSTRUCTION_CACHE)
 298 #define CONFIG_SYS_HID2         HID2_HBE
 299
 300 /*
 301  * MMU Setup
 302  */
 303 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 304
 305 /* DDR: cache cacheable */
 306 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE \
 307                                 | BATL_PP_RW \
 308                                 | BATL_MEMCOHERENCE)
 309 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE \
 310                                 | BATU_BL_256M \
 311                                 | BATU_VS \
 312                                 | BATU_VP)
 313 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 314 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 315
 316 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 317 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR \
 318                                 | BATL_PP_RW \
 319                                 | BATL_CACHEINHIBIT \
 320                                 | BATL_GUARDEDSTORAGE)
 321 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR \
 322                                 | BATU_BL_4M \
 323                                 | BATU_VS \
 324                                 | BATU_VP)
 325 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 326 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 327
 328 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 329 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_FLASH_BASE \
 330                                 | BATL_PP_RW \
 331                                 | BATL_MEMCOHERENCE)
 332 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_FLASH_BASE \
 333                                 | BATU_BL_32M \
 334                                 | BATU_VS \
 335                                 | BATU_VP)
 336 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_FLASH_BASE \
 337                                 | BATL_PP_RW \
 338                                 | BATL_CACHEINHIBIT \
 339                                 | BATL_GUARDEDSTORAGE)
 340 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 341
 342 #define CONFIG_SYS_IBAT3L       (0)
 343 #define CONFIG_SYS_IBAT3U       (0)
 344 #define CONFIG_SYS_DBAT3L       CONFIG_SYS_IBAT3L
 345 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 346
 347 /* Stack in dcache: cacheable, no memory coherence */
 348 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 349 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR \
 350                                 | BATU_BL_128K \
 351                                 | BATU_VS \
 352                                 | BATU_VP)
 353 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 354 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 355
 356 #ifdef CONFIG_PCI
 357 /* PCI MEM space: cacheable */
 358 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PCI1_MEM_PHYS \
 359                                 | BATL_PP_RW \
 360                                 | BATL_MEMCOHERENCE)
 361 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PCI1_MEM_PHYS \
 362                                 | BATU_BL_256M \
 363                                 | BATU_VS \
 364                                 | BATU_VP)
 365 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 366 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 367 /* PCI MMIO space: cache-inhibit and guarded */
 368 #define CONFIG_SYS_IBAT6L       (CONFIG_SYS_PCI1_MMIO_PHYS \
 369                                 | BATL_PP_RW \
 370                                 | BATL_CACHEINHIBIT \
 371                                 | BATL_GUARDEDSTORAGE)
 372 #define CONFIG_SYS_IBAT6U       (CONFIG_SYS_PCI1_MMIO_PHYS \
 373                                 | BATU_BL_256M \
 374                                 | BATU_VS \
 375                                 | BATU_VP)
 376 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 377 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 378 #else
 379 #define CONFIG_SYS_IBAT5L       (0)
 380 #define CONFIG_SYS_IBAT5U       (0)
 381 #define CONFIG_SYS_IBAT6L       (0)
 382 #define CONFIG_SYS_IBAT6U       (0)
 383 #define CONFIG_SYS_DBAT5L       CONFIG_SYS_IBAT5L
 384 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 385 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 386 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 387 #endif
 388
 389 /* Nothing in BAT7 */
 390 #define CONFIG_SYS_IBAT7L       (0)
 391 #define CONFIG_SYS_IBAT7U       (0)
 392 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 393 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 394
 395 #if (CONFIG_CMD_KGDB)
 396 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 397 #endif
 398
 399 /*
 400  * Environment Configuration
 401  */
 402 #define CONFIG_ENV_OVERWRITE
 403
 404 #define CONFIG_HAS_ETH0         /* add support for "ethaddr" */
 405 #define CONFIG_HAS_ETH1         /* add support for "eth1addr" */
 406
 407 /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 408  * (see CONFIG_SYS_I2C_EEPROM) */
 409                                         /* MAC address offset in I2C EEPROM */
 410 #define CONFIG_SYS_I2C_MAC_OFFSET       0x7f00
 411
 412 #define CONFIG_NETDEV           "eth1"
 413
 414 #define CONFIG_HOSTNAME         "mpc8323erdb"
 415 #define CONFIG_ROOTPATH         "/nfsroot"
 416 #define CONFIG_BOOTFILE         "uImage"
 417                                 /* U-Boot image on TFTP server */
 418 #define CONFIG_UBOOTPATH        "u-boot.bin"
 419 #define CONFIG_FDTFILE          "mpc832x_rdb.dtb"
 420 #define CONFIG_RAMDISKFILE      "rootfs.ext2.gz.uboot"
 421
 422                                 /* default location for tftp and bootm */
 423 #define CONFIG_LOADADDR         800000
 424
 425 #define CONFIG_EXTRA_ENV_SETTINGS \
 426         "netdev=" CONFIG_NETDEV "\0"                                    \
 427         "uboot=" CONFIG_UBOOTPATH "\0"                                  \
 428         "tftpflash=tftp $loadaddr $uboot;"                              \
 429                 "protect off " __stringify(CONFIG_SYS_TEXT_BASE)        \
 430                         " +$filesize; " \
 431                 "erase " __stringify(CONFIG_SYS_TEXT_BASE)              \
 432                         " +$filesize; " \
 433                 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)     \
 434                         " $filesize; "  \
 435                 "protect on " __stringify(CONFIG_SYS_TEXT_BASE)         \
 436                         " +$filesize; " \
 437                 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)    \
 438                         " $filesize\0"  \
 439         "fdtaddr=780000\0"                                              \
 440         "fdtfile=" CONFIG_FDTFILE "\0"                                  \
 441         "ramdiskaddr=1000000\0"                                         \
 442         "ramdiskfile=" CONFIG_RAMDISKFILE "\0"                          \
 443         "console=ttyS0\0"                                               \
 444         "setbootargs=setenv bootargs "                                  \
 445                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
 446         "setipargs=setenv bootargs nfsroot=$serverip:$rootpath "        \
 447                 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
 448                                                                 "$netdev:off "\
 449                 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
 450
 451 #define CONFIG_NFSBOOTCOMMAND                                           \
 452         "setenv rootdev /dev/nfs;"                                      \
 453         "run setbootargs;"                                              \
 454         "run setipargs;"                                                \
 455         "tftp $loadaddr $bootfile;"                                     \
 456         "tftp $fdtaddr $fdtfile;"                                       \
 457         "bootm $loadaddr - $fdtaddr"
 458
 459 #define CONFIG_RAMBOOTCOMMAND                                           \
 460         "setenv rootdev /dev/ram;"                                      \
 461         "run setbootargs;"                                              \
 462         "tftp $ramdiskaddr $ramdiskfile;"                               \
 463         "tftp $loadaddr $bootfile;"                                     \
 464         "tftp $fdtaddr $fdtfile;"                                       \
 465         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 466
 467 #endif  /* __CONFIG_H */