1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011,
5 Free Software Foundation, Inc.
7 This file is part of GAS, the GNU Assembler.
9 GAS is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GAS is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GAS; see the file COPYING. If not, write to the Free
21 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
24 /* Intel 80386 machine specific gas.
25 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
26 x86_64 support by Jan Hubicka (jh@suse.cz)
27 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
28 Bugs & suggestions are completely welcome. This is free software.
29 Please help us make it better. */
32 #include "safe-ctype.h"
34 #include "dwarf2dbg.h"
35 #include "dw2gencfi.h"
36 #include "elf/x86-64.h"
37 #include "opcodes/i386-init.h"
39 #ifndef REGISTER_WARNINGS
40 #define REGISTER_WARNINGS 1
43 #ifndef INFER_ADDR_PREFIX
44 #define INFER_ADDR_PREFIX 1
48 #define DEFAULT_ARCH "i386"
53 #define INLINE __inline__
59 /* Prefixes will be emitted in the order defined below.
60 WAIT_PREFIX must be the first prefix since FWAIT is really is an
61 instruction, and so must come before any prefixes.
62 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
63 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
69 #define HLE_PREFIX REP_PREFIX
70 #define BND_PREFIX REP_PREFIX
72 #define REX_PREFIX 6 /* must come last. */
73 #define MAX_PREFIXES 7 /* max prefixes per opcode */
75 /* we define the syntax here (modulo base,index,scale syntax) */
76 #define REGISTER_PREFIX '%'
77 #define IMMEDIATE_PREFIX '$'
78 #define ABSOLUTE_PREFIX '*'
80 /* these are the instruction mnemonic suffixes in AT&T syntax or
81 memory operand size in Intel syntax. */
82 #define WORD_MNEM_SUFFIX 'w'
83 #define BYTE_MNEM_SUFFIX 'b'
84 #define SHORT_MNEM_SUFFIX 's'
85 #define LONG_MNEM_SUFFIX 'l'
86 #define QWORD_MNEM_SUFFIX 'q'
87 #define XMMWORD_MNEM_SUFFIX 'x'
88 #define YMMWORD_MNEM_SUFFIX 'y'
89 #define ZMMWORD_MNEM_SUFFIX 'z'
90 /* Intel Syntax. Use a non-ascii letter since since it never appears
92 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
94 #define END_OF_INSN '\0'
97 'templates' is for grouping together 'template' structures for opcodes
98 of the same name. This is only used for storing the insns in the grand
99 ole hash table of insns.
100 The templates themselves start at START and range up to (but not including)
105 const insn_template *start;
106 const insn_template *end;
110 /* 386 operand encoding bytes: see 386 book for details of this. */
113 unsigned int regmem; /* codes register or memory operand */
114 unsigned int reg; /* codes register operand (or extended opcode) */
115 unsigned int mode; /* how to interpret regmem & reg */
119 /* x86-64 extension prefix. */
120 typedef int rex_byte;
122 /* 386 opcode byte to code indirect addressing. */
131 /* x86 arch names, types and features */
134 const char *name; /* arch name */
135 unsigned int len; /* arch string length */
136 enum processor_type type; /* arch type */
137 i386_cpu_flags flags; /* cpu feature flags */
138 unsigned int skip; /* show_arch should skip this. */
139 unsigned int negated; /* turn off indicated flags. */
143 static void update_code_flag (int, int);
144 static void set_code_flag (int);
145 static void set_16bit_gcc_code_flag (int);
146 static void set_intel_syntax (int);
147 static void set_intel_mnemonic (int);
148 static void set_allow_index_reg (int);
149 static void set_check (int);
150 static void set_cpu_arch (int);
152 static void pe_directive_secrel (int);
154 static void signed_cons (int);
155 static char *output_invalid (int c);
156 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
158 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
160 static int i386_att_operand (char *);
161 static int i386_intel_operand (char *, int);
162 static int i386_intel_simplify (expressionS *);
163 static int i386_intel_parse_name (const char *, expressionS *);
164 static const reg_entry *parse_register (char *, char **);
165 static char *parse_insn (char *, char *);
166 static char *parse_operands (char *, const char *);
167 static void swap_operands (void);
168 static void swap_2_operands (int, int);
169 static void optimize_imm (void);
170 static void optimize_disp (void);
171 static const insn_template *match_template (void);
172 static int check_string (void);
173 static int process_suffix (void);
174 static int check_byte_reg (void);
175 static int check_long_reg (void);
176 static int check_qword_reg (void);
177 static int check_word_reg (void);
178 static int finalize_imm (void);
179 static int process_operands (void);
180 static const seg_entry *build_modrm_byte (void);
181 static void output_insn (void);
182 static void output_imm (fragS *, offsetT);
183 static void output_disp (fragS *, offsetT);
185 static void s_bss (int);
187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
188 static void handle_large_common (int small ATTRIBUTE_UNUSED);
191 static const char *default_arch = DEFAULT_ARCH;
193 /* This struct describes rounding control and SAE in the instruction. */
207 static struct RC_Operation rc_op;
209 /* The struct describes masking, applied to OPERAND in the instruction.
210 MASK is a pointer to the corresponding mask register. ZEROING tells
211 whether merging or zeroing mask is used. */
212 struct Mask_Operation
214 const reg_entry *mask;
215 unsigned int zeroing;
216 /* The operand where this operation is associated. */
220 static struct Mask_Operation mask_op;
222 /* The struct describes broadcasting, applied to OPERAND. FACTOR is
224 struct Broadcast_Operation
226 /* Type of broadcast: no broadcast, {1to8}, or {1to16}. */
229 /* Index of broadcasted operand. */
233 static struct Broadcast_Operation broadcast_op;
238 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
239 unsigned char bytes[4];
241 /* Destination or source register specifier. */
242 const reg_entry *register_specifier;
245 /* 'md_assemble ()' gathers together information and puts it into a
252 const reg_entry *regs;
257 operand_size_mismatch,
258 operand_type_mismatch,
259 register_type_mismatch,
260 number_of_operands_mismatch,
261 invalid_instruction_suffix,
264 unsupported_with_intel_mnemonic,
267 invalid_vsib_address,
268 invalid_vector_register_set,
269 unsupported_vector_index_register,
270 unsupported_broadcast,
271 broadcast_not_on_src_operand,
274 mask_not_on_destination,
277 rc_sae_operand_not_last_imm,
278 invalid_register_operand,
284 /* TM holds the template for the insn were currently assembling. */
287 /* SUFFIX holds the instruction size suffix for byte, word, dword
288 or qword, if given. */
291 /* OPERANDS gives the number of given operands. */
292 unsigned int operands;
294 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
295 of given register, displacement, memory operands and immediate
297 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
299 /* TYPES [i] is the type (see above #defines) which tells us how to
300 use OP[i] for the corresponding operand. */
301 i386_operand_type types[MAX_OPERANDS];
303 /* Displacement expression, immediate expression, or register for each
305 union i386_op op[MAX_OPERANDS];
307 /* Flags for operands. */
308 unsigned int flags[MAX_OPERANDS];
309 #define Operand_PCrel 1
311 /* Relocation type for operand */
312 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
314 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
315 the base index byte below. */
316 const reg_entry *base_reg;
317 const reg_entry *index_reg;
318 unsigned int log2_scale_factor;
320 /* SEG gives the seg_entries of this insn. They are zero unless
321 explicit segment overrides are given. */
322 const seg_entry *seg[2];
324 /* PREFIX holds all the given prefix opcodes (usually null).
325 PREFIXES is the number of prefix opcodes. */
326 unsigned int prefixes;
327 unsigned char prefix[MAX_PREFIXES];
329 /* RM and SIB are the modrm byte and the sib byte where the
330 addressing modes of this insn are encoded. */
337 /* Masking attributes. */
338 struct Mask_Operation *mask;
340 /* Rounding control and SAE attributes. */
341 struct RC_Operation *rounding;
343 /* Broadcasting attributes. */
344 struct Broadcast_Operation *broadcast;
346 /* Compressed disp8*N attribute. */
347 unsigned int memshift;
349 /* Swap operand in encoding. */
350 unsigned int swap_operand;
352 /* Prefer 8bit or 32bit displacement in encoding. */
355 disp_encoding_default = 0,
361 const char *rep_prefix;
364 const char *hle_prefix;
366 /* Have BND prefix. */
367 const char *bnd_prefix;
369 /* Need VREX to support upper 16 registers. */
373 enum i386_error error;
376 typedef struct _i386_insn i386_insn;
378 /* Link RC type with corresponding string, that'll be looked for in
387 static const struct RC_name RC_NamesTable[] =
389 { rne, STRING_COMMA_LEN ("rn-sae") },
390 { rd, STRING_COMMA_LEN ("rd-sae") },
391 { ru, STRING_COMMA_LEN ("ru-sae") },
392 { rz, STRING_COMMA_LEN ("rz-sae") },
393 { saeonly, STRING_COMMA_LEN ("sae") },
396 /* List of chars besides those in app.c:symbol_chars that can start an
397 operand. Used to prevent the scrubber eating vital white-space. */
398 const char extra_symbol_chars[] = "*%-([{"
407 #if (defined (TE_I386AIX) \
408 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
409 && !defined (TE_GNU) \
410 && !defined (TE_LINUX) \
411 && !defined (TE_NACL) \
412 && !defined (TE_NETWARE) \
413 && !defined (TE_FreeBSD) \
414 && !defined (TE_DragonFly) \
415 && !defined (TE_NetBSD)))
416 /* This array holds the chars that always start a comment. If the
417 pre-processor is disabled, these aren't very useful. The option
418 --divide will remove '/' from this list. */
419 const char *i386_comment_chars = "#/";
420 #define SVR4_COMMENT_CHARS 1
421 #define PREFIX_SEPARATOR '\\'
424 const char *i386_comment_chars = "#";
425 #define PREFIX_SEPARATOR '/'
428 /* This array holds the chars that only start a comment at the beginning of
429 a line. If the line seems to have the form '# 123 filename'
430 .line and .file directives will appear in the pre-processed output.
431 Note that input_file.c hand checks for '#' at the beginning of the
432 first line of the input file. This is because the compiler outputs
433 #NO_APP at the beginning of its output.
434 Also note that comments started like this one will always work if
435 '/' isn't otherwise defined. */
436 const char line_comment_chars[] = "#/";
438 const char line_separator_chars[] = ";";
440 /* Chars that can be used to separate mant from exp in floating point
442 const char EXP_CHARS[] = "eE";
444 /* Chars that mean this number is a floating point constant
447 const char FLT_CHARS[] = "fFdDxX";
449 /* Tables for lexical analysis. */
450 static char mnemonic_chars[256];
451 static char register_chars[256];
452 static char operand_chars[256];
453 static char identifier_chars[256];
454 static char digit_chars[256];
456 /* Lexical macros. */
457 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
458 #define is_operand_char(x) (operand_chars[(unsigned char) x])
459 #define is_register_char(x) (register_chars[(unsigned char) x])
460 #define is_space_char(x) ((x) == ' ')
461 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
462 #define is_digit_char(x) (digit_chars[(unsigned char) x])
464 /* All non-digit non-letter characters that may occur in an operand. */
465 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
467 /* md_assemble() always leaves the strings it's passed unaltered. To
468 effect this we maintain a stack of saved characters that we've smashed
469 with '\0's (indicating end of strings for various sub-fields of the
470 assembler instruction). */
471 static char save_stack[32];
472 static char *save_stack_p;
473 #define END_STRING_AND_SAVE(s) \
474 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
475 #define RESTORE_END_STRING(s) \
476 do { *(s) = *--save_stack_p; } while (0)
478 /* The instruction we're assembling. */
481 /* Possible templates for current insn. */
482 static const templates *current_templates;
484 /* Per instruction expressionS buffers: max displacements & immediates. */
485 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
486 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
488 /* Current operand we are working on. */
489 static int this_operand = -1;
491 /* We support four different modes. FLAG_CODE variable is used to distinguish
499 static enum flag_code flag_code;
500 static unsigned int object_64bit;
501 static unsigned int disallow_64bit_reloc;
502 static int use_rela_relocations = 0;
504 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
505 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
506 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
508 /* The ELF ABI to use. */
516 static enum x86_elf_abi x86_elf_abi = I386_ABI;
519 /* 1 for intel syntax,
521 static int intel_syntax = 0;
523 /* 1 for intel mnemonic,
524 0 if att mnemonic. */
525 static int intel_mnemonic = !SYSV386_COMPAT;
527 /* 1 if support old (<= 2.8.1) versions of gcc. */
528 static int old_gcc = OLDGCC_COMPAT;
530 /* 1 if pseudo registers are permitted. */
531 static int allow_pseudo_reg = 0;
533 /* 1 if register prefix % not required. */
534 static int allow_naked_reg = 0;
536 /* 1 if the assembler should add BND prefix for all control-tranferring
537 instructions supporting it, even if this prefix wasn't specified
539 static int add_bnd_prefix = 0;
541 /* 1 if pseudo index register, eiz/riz, is allowed . */
542 static int allow_index_reg = 0;
544 static enum check_kind
550 sse_check, operand_check = check_warning;
552 /* Register prefix used for error message. */
553 static const char *register_prefix = "%";
555 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
556 leave, push, and pop instructions so that gcc has the same stack
557 frame as in 32 bit mode. */
558 static char stackop_size = '\0';
560 /* Non-zero to optimize code alignment. */
561 int optimize_align_code = 1;
563 /* Non-zero to quieten some warnings. */
564 static int quiet_warnings = 0;
567 static const char *cpu_arch_name = NULL;
568 static char *cpu_sub_arch_name = NULL;
570 /* CPU feature flags. */
571 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
573 /* If we have selected a cpu we are generating instructions for. */
574 static int cpu_arch_tune_set = 0;
576 /* Cpu we are generating instructions for. */
577 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
579 /* CPU feature flags of cpu we are generating instructions for. */
580 static i386_cpu_flags cpu_arch_tune_flags;
582 /* CPU instruction set architecture used. */
583 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
585 /* CPU feature flags of instruction set architecture used. */
586 i386_cpu_flags cpu_arch_isa_flags;
588 /* If set, conditional jumps are not automatically promoted to handle
589 larger than a byte offset. */
590 static unsigned int no_cond_jump_promotion = 0;
592 /* Encode SSE instructions with VEX prefix. */
593 static unsigned int sse2avx;
595 /* Encode scalar AVX instructions with specific vector length. */
602 /* Encode scalar EVEX LIG instructions with specific vector length. */
610 /* Encode EVEX WIG instructions with specific evex.w. */
617 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
618 static symbolS *GOT_symbol;
620 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
621 unsigned int x86_dwarf2_return_column;
623 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
624 int x86_cie_data_alignment;
626 /* Interface to relax_segment.
627 There are 3 major relax states for 386 jump insns because the
628 different types of jumps add different sizes to frags when we're
629 figuring out what sort of jump to choose to reach a given label. */
632 #define UNCOND_JUMP 0
634 #define COND_JUMP86 2
639 #define SMALL16 (SMALL | CODE16)
641 #define BIG16 (BIG | CODE16)
645 #define INLINE __inline__
651 #define ENCODE_RELAX_STATE(type, size) \
652 ((relax_substateT) (((type) << 2) | (size)))
653 #define TYPE_FROM_RELAX_STATE(s) \
655 #define DISP_SIZE_FROM_RELAX_STATE(s) \
656 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
658 /* This table is used by relax_frag to promote short jumps to long
659 ones where necessary. SMALL (short) jumps may be promoted to BIG
660 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
661 don't allow a short jump in a 32 bit code segment to be promoted to
662 a 16 bit offset jump because it's slower (requires data size
663 prefix), and doesn't work, unless the destination is in the bottom
664 64k of the code segment (The top 16 bits of eip are zeroed). */
666 const relax_typeS md_relax_table[] =
669 1) most positive reach of this state,
670 2) most negative reach of this state,
671 3) how many bytes this mode will have in the variable part of the frag
672 4) which index into the table to try if we can't fit into this one. */
674 /* UNCOND_JUMP states. */
675 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
676 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
677 /* dword jmp adds 4 bytes to frag:
678 0 extra opcode bytes, 4 displacement bytes. */
680 /* word jmp adds 2 byte2 to frag:
681 0 extra opcode bytes, 2 displacement bytes. */
684 /* COND_JUMP states. */
685 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
686 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
687 /* dword conditionals adds 5 bytes to frag:
688 1 extra opcode byte, 4 displacement bytes. */
690 /* word conditionals add 3 bytes to frag:
691 1 extra opcode byte, 2 displacement bytes. */
694 /* COND_JUMP86 states. */
695 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
696 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
697 /* dword conditionals adds 5 bytes to frag:
698 1 extra opcode byte, 4 displacement bytes. */
700 /* word conditionals add 4 bytes to frag:
701 1 displacement byte and a 3 byte long branch insn. */
705 static const arch_entry cpu_arch[] =
707 /* Do not replace the first two entries - i386_target_format()
708 relies on them being there in this order. */
709 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
710 CPU_GENERIC32_FLAGS, 0, 0 },
711 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
712 CPU_GENERIC64_FLAGS, 0, 0 },
713 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
714 CPU_NONE_FLAGS, 0, 0 },
715 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
716 CPU_I186_FLAGS, 0, 0 },
717 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
718 CPU_I286_FLAGS, 0, 0 },
719 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
720 CPU_I386_FLAGS, 0, 0 },
721 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
722 CPU_I486_FLAGS, 0, 0 },
723 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
724 CPU_I586_FLAGS, 0, 0 },
725 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
726 CPU_I686_FLAGS, 0, 0 },
727 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
728 CPU_I586_FLAGS, 0, 0 },
729 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
730 CPU_PENTIUMPRO_FLAGS, 0, 0 },
731 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
732 CPU_P2_FLAGS, 0, 0 },
733 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
734 CPU_P3_FLAGS, 0, 0 },
735 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
736 CPU_P4_FLAGS, 0, 0 },
737 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
738 CPU_CORE_FLAGS, 0, 0 },
739 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
740 CPU_NOCONA_FLAGS, 0, 0 },
741 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
742 CPU_CORE_FLAGS, 1, 0 },
743 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
744 CPU_CORE_FLAGS, 0, 0 },
745 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
746 CPU_CORE2_FLAGS, 1, 0 },
747 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
748 CPU_CORE2_FLAGS, 0, 0 },
749 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
750 CPU_COREI7_FLAGS, 0, 0 },
751 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
752 CPU_L1OM_FLAGS, 0, 0 },
753 { STRING_COMMA_LEN ("k1om"), PROCESSOR_K1OM,
754 CPU_K1OM_FLAGS, 0, 0 },
755 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
756 CPU_K6_FLAGS, 0, 0 },
757 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
758 CPU_K6_2_FLAGS, 0, 0 },
759 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
760 CPU_ATHLON_FLAGS, 0, 0 },
761 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
762 CPU_K8_FLAGS, 1, 0 },
763 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
764 CPU_K8_FLAGS, 0, 0 },
765 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
766 CPU_K8_FLAGS, 0, 0 },
767 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
768 CPU_AMDFAM10_FLAGS, 0, 0 },
769 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BD,
770 CPU_BDVER1_FLAGS, 0, 0 },
771 { STRING_COMMA_LEN ("bdver2"), PROCESSOR_BD,
772 CPU_BDVER2_FLAGS, 0, 0 },
773 { STRING_COMMA_LEN ("bdver3"), PROCESSOR_BD,
774 CPU_BDVER3_FLAGS, 0, 0 },
775 { STRING_COMMA_LEN ("bdver4"), PROCESSOR_BD,
776 CPU_BDVER4_FLAGS, 0, 0 },
777 { STRING_COMMA_LEN ("btver1"), PROCESSOR_BT,
778 CPU_BTVER1_FLAGS, 0, 0 },
779 { STRING_COMMA_LEN ("btver2"), PROCESSOR_BT,
780 CPU_BTVER2_FLAGS, 0, 0 },
781 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
782 CPU_8087_FLAGS, 0, 0 },
783 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
784 CPU_287_FLAGS, 0, 0 },
785 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
786 CPU_387_FLAGS, 0, 0 },
787 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
788 CPU_ANY87_FLAGS, 0, 1 },
789 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
790 CPU_MMX_FLAGS, 0, 0 },
791 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
792 CPU_3DNOWA_FLAGS, 0, 1 },
793 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
794 CPU_SSE_FLAGS, 0, 0 },
795 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
796 CPU_SSE2_FLAGS, 0, 0 },
797 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
798 CPU_SSE3_FLAGS, 0, 0 },
799 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
800 CPU_SSSE3_FLAGS, 0, 0 },
801 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
802 CPU_SSE4_1_FLAGS, 0, 0 },
803 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
804 CPU_SSE4_2_FLAGS, 0, 0 },
805 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
806 CPU_SSE4_2_FLAGS, 0, 0 },
807 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
808 CPU_ANY_SSE_FLAGS, 0, 1 },
809 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
810 CPU_AVX_FLAGS, 0, 0 },
811 { STRING_COMMA_LEN (".avx2"), PROCESSOR_UNKNOWN,
812 CPU_AVX2_FLAGS, 0, 0 },
813 { STRING_COMMA_LEN (".avx512f"), PROCESSOR_UNKNOWN,
814 CPU_AVX512F_FLAGS, 0, 0 },
815 { STRING_COMMA_LEN (".avx512cd"), PROCESSOR_UNKNOWN,
816 CPU_AVX512CD_FLAGS, 0, 0 },
817 { STRING_COMMA_LEN (".avx512er"), PROCESSOR_UNKNOWN,
818 CPU_AVX512ER_FLAGS, 0, 0 },
819 { STRING_COMMA_LEN (".avx512pf"), PROCESSOR_UNKNOWN,
820 CPU_AVX512PF_FLAGS, 0, 0 },
821 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
822 CPU_ANY_AVX_FLAGS, 0, 1 },
823 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
824 CPU_VMX_FLAGS, 0, 0 },
825 { STRING_COMMA_LEN (".vmfunc"), PROCESSOR_UNKNOWN,
826 CPU_VMFUNC_FLAGS, 0, 0 },
827 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
828 CPU_SMX_FLAGS, 0, 0 },
829 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
830 CPU_XSAVE_FLAGS, 0, 0 },
831 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
832 CPU_XSAVEOPT_FLAGS, 0, 0 },
833 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
834 CPU_AES_FLAGS, 0, 0 },
835 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
836 CPU_PCLMUL_FLAGS, 0, 0 },
837 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
838 CPU_PCLMUL_FLAGS, 1, 0 },
839 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
840 CPU_FSGSBASE_FLAGS, 0, 0 },
841 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
842 CPU_RDRND_FLAGS, 0, 0 },
843 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
844 CPU_F16C_FLAGS, 0, 0 },
845 { STRING_COMMA_LEN (".bmi2"), PROCESSOR_UNKNOWN,
846 CPU_BMI2_FLAGS, 0, 0 },
847 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
848 CPU_FMA_FLAGS, 0, 0 },
849 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
850 CPU_FMA4_FLAGS, 0, 0 },
851 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
852 CPU_XOP_FLAGS, 0, 0 },
853 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
854 CPU_LWP_FLAGS, 0, 0 },
855 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
856 CPU_MOVBE_FLAGS, 0, 0 },
857 { STRING_COMMA_LEN (".cx16"), PROCESSOR_UNKNOWN,
858 CPU_CX16_FLAGS, 0, 0 },
859 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
860 CPU_EPT_FLAGS, 0, 0 },
861 { STRING_COMMA_LEN (".lzcnt"), PROCESSOR_UNKNOWN,
862 CPU_LZCNT_FLAGS, 0, 0 },
863 { STRING_COMMA_LEN (".hle"), PROCESSOR_UNKNOWN,
864 CPU_HLE_FLAGS, 0, 0 },
865 { STRING_COMMA_LEN (".rtm"), PROCESSOR_UNKNOWN,
866 CPU_RTM_FLAGS, 0, 0 },
867 { STRING_COMMA_LEN (".invpcid"), PROCESSOR_UNKNOWN,
868 CPU_INVPCID_FLAGS, 0, 0 },
869 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
870 CPU_CLFLUSH_FLAGS, 0, 0 },
871 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
872 CPU_NOP_FLAGS, 0, 0 },
873 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
874 CPU_SYSCALL_FLAGS, 0, 0 },
875 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
876 CPU_RDTSCP_FLAGS, 0, 0 },
877 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
878 CPU_3DNOW_FLAGS, 0, 0 },
879 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
880 CPU_3DNOWA_FLAGS, 0, 0 },
881 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
882 CPU_PADLOCK_FLAGS, 0, 0 },
883 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
884 CPU_SVME_FLAGS, 1, 0 },
885 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
886 CPU_SVME_FLAGS, 0, 0 },
887 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
888 CPU_SSE4A_FLAGS, 0, 0 },
889 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
890 CPU_ABM_FLAGS, 0, 0 },
891 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
892 CPU_BMI_FLAGS, 0, 0 },
893 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
894 CPU_TBM_FLAGS, 0, 0 },
895 { STRING_COMMA_LEN (".adx"), PROCESSOR_UNKNOWN,
896 CPU_ADX_FLAGS, 0, 0 },
897 { STRING_COMMA_LEN (".rdseed"), PROCESSOR_UNKNOWN,
898 CPU_RDSEED_FLAGS, 0, 0 },
899 { STRING_COMMA_LEN (".prfchw"), PROCESSOR_UNKNOWN,
900 CPU_PRFCHW_FLAGS, 0, 0 },
901 { STRING_COMMA_LEN (".smap"), PROCESSOR_UNKNOWN,
902 CPU_SMAP_FLAGS, 0, 0 },
903 { STRING_COMMA_LEN (".mpx"), PROCESSOR_UNKNOWN,
904 CPU_MPX_FLAGS, 0, 0 },
905 { STRING_COMMA_LEN (".sha"), PROCESSOR_UNKNOWN,
906 CPU_SHA_FLAGS, 0, 0 },
910 /* Like s_lcomm_internal in gas/read.c but the alignment string
911 is allowed to be optional. */
914 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
921 && *input_line_pointer == ',')
923 align = parse_align (needs_align - 1);
925 if (align == (addressT) -1)
940 bss_alloc (symbolP, size, align);
945 pe_lcomm (int needs_align)
947 s_comm_internal (needs_align * 2, pe_lcomm_internal);
951 const pseudo_typeS md_pseudo_table[] =
953 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
954 {"align", s_align_bytes, 0},
956 {"align", s_align_ptwo, 0},
958 {"arch", set_cpu_arch, 0},
962 {"lcomm", pe_lcomm, 1},
964 {"ffloat", float_cons, 'f'},
965 {"dfloat", float_cons, 'd'},
966 {"tfloat", float_cons, 'x'},
968 {"slong", signed_cons, 4},
969 {"noopt", s_ignore, 0},
970 {"optim", s_ignore, 0},
971 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
972 {"code16", set_code_flag, CODE_16BIT},
973 {"code32", set_code_flag, CODE_32BIT},
974 {"code64", set_code_flag, CODE_64BIT},
975 {"intel_syntax", set_intel_syntax, 1},
976 {"att_syntax", set_intel_syntax, 0},
977 {"intel_mnemonic", set_intel_mnemonic, 1},
978 {"att_mnemonic", set_intel_mnemonic, 0},
979 {"allow_index_reg", set_allow_index_reg, 1},
980 {"disallow_index_reg", set_allow_index_reg, 0},
981 {"sse_check", set_check, 0},
982 {"operand_check", set_check, 1},
983 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
984 {"largecomm", handle_large_common, 0},
986 {"file", (void (*) (int)) dwarf2_directive_file, 0},
987 {"loc", dwarf2_directive_loc, 0},
988 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
991 {"secrel32", pe_directive_secrel, 0},
996 /* For interface with expression (). */
997 extern char *input_line_pointer;
999 /* Hash table for instruction mnemonic lookup. */
1000 static struct hash_control *op_hash;
1002 /* Hash table for register lookup. */
1003 static struct hash_control *reg_hash;
1006 i386_align_code (fragS *fragP, int count)
1008 /* Various efficient no-op patterns for aligning code labels.
1009 Note: Don't try to assemble the instructions in the comments.
1010 0L and 0w are not legal. */
1011 static const char f32_1[] =
1013 static const char f32_2[] =
1014 {0x66,0x90}; /* xchg %ax,%ax */
1015 static const char f32_3[] =
1016 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
1017 static const char f32_4[] =
1018 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1019 static const char f32_5[] =
1021 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
1022 static const char f32_6[] =
1023 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
1024 static const char f32_7[] =
1025 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1026 static const char f32_8[] =
1028 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
1029 static const char f32_9[] =
1030 {0x89,0xf6, /* movl %esi,%esi */
1031 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1032 static const char f32_10[] =
1033 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
1034 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1035 static const char f32_11[] =
1036 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
1037 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1038 static const char f32_12[] =
1039 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1040 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
1041 static const char f32_13[] =
1042 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
1043 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1044 static const char f32_14[] =
1045 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
1046 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
1047 static const char f16_3[] =
1048 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
1049 static const char f16_4[] =
1050 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1051 static const char f16_5[] =
1053 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
1054 static const char f16_6[] =
1055 {0x89,0xf6, /* mov %si,%si */
1056 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1057 static const char f16_7[] =
1058 {0x8d,0x74,0x00, /* lea 0(%si),%si */
1059 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1060 static const char f16_8[] =
1061 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
1062 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
1063 static const char jump_31[] =
1064 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
1065 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1066 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
1067 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
1068 static const char *const f32_patt[] = {
1069 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
1070 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
1072 static const char *const f16_patt[] = {
1073 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
1075 /* nopl (%[re]ax) */
1076 static const char alt_3[] =
1078 /* nopl 0(%[re]ax) */
1079 static const char alt_4[] =
1080 {0x0f,0x1f,0x40,0x00};
1081 /* nopl 0(%[re]ax,%[re]ax,1) */
1082 static const char alt_5[] =
1083 {0x0f,0x1f,0x44,0x00,0x00};
1084 /* nopw 0(%[re]ax,%[re]ax,1) */
1085 static const char alt_6[] =
1086 {0x66,0x0f,0x1f,0x44,0x00,0x00};
1087 /* nopl 0L(%[re]ax) */
1088 static const char alt_7[] =
1089 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1090 /* nopl 0L(%[re]ax,%[re]ax,1) */
1091 static const char alt_8[] =
1092 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1093 /* nopw 0L(%[re]ax,%[re]ax,1) */
1094 static const char alt_9[] =
1095 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1096 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1097 static const char alt_10[] =
1098 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1100 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1101 static const char alt_long_11[] =
1103 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1106 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1107 static const char alt_long_12[] =
1110 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1114 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1115 static const char alt_long_13[] =
1119 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1124 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1125 static const char alt_long_14[] =
1130 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1136 nopw %cs:0L(%[re]ax,%[re]ax,1) */
1137 static const char alt_long_15[] =
1143 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1144 /* nopl 0(%[re]ax,%[re]ax,1)
1145 nopw 0(%[re]ax,%[re]ax,1) */
1146 static const char alt_short_11[] =
1147 {0x0f,0x1f,0x44,0x00,0x00,
1148 0x66,0x0f,0x1f,0x44,0x00,0x00};
1149 /* nopw 0(%[re]ax,%[re]ax,1)
1150 nopw 0(%[re]ax,%[re]ax,1) */
1151 static const char alt_short_12[] =
1152 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1153 0x66,0x0f,0x1f,0x44,0x00,0x00};
1154 /* nopw 0(%[re]ax,%[re]ax,1)
1156 static const char alt_short_13[] =
1157 {0x66,0x0f,0x1f,0x44,0x00,0x00,
1158 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1161 static const char alt_short_14[] =
1162 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1163 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
1165 nopl 0L(%[re]ax,%[re]ax,1) */
1166 static const char alt_short_15[] =
1167 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1168 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1169 static const char *const alt_short_patt[] = {
1170 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1171 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1172 alt_short_14, alt_short_15
1174 static const char *const alt_long_patt[] = {
1175 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1176 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1177 alt_long_14, alt_long_15
1180 /* Only align for at least a positive non-zero boundary. */
1181 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1184 /* We need to decide which NOP sequence to use for 32bit and
1185 64bit. When -mtune= is used:
1187 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1188 PROCESSOR_GENERIC32, f32_patt will be used.
1189 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1190 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1191 PROCESSOR_GENERIC64, alt_long_patt will be used.
1192 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1193 PROCESSOR_AMDFAM10, PROCESSOR_BD and PROCESSOR_BT, alt_short_patt
1196 When -mtune= isn't used, alt_long_patt will be used if
1197 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1200 When -march= or .arch is used, we can't use anything beyond
1201 cpu_arch_isa_flags. */
1203 if (flag_code == CODE_16BIT)
1207 memcpy (fragP->fr_literal + fragP->fr_fix,
1209 /* Adjust jump offset. */
1210 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1213 memcpy (fragP->fr_literal + fragP->fr_fix,
1214 f16_patt[count - 1], count);
1218 const char *const *patt = NULL;
1220 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1222 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1223 switch (cpu_arch_tune)
1225 case PROCESSOR_UNKNOWN:
1226 /* We use cpu_arch_isa_flags to check if we SHOULD
1227 optimize with nops. */
1228 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1229 patt = alt_long_patt;
1233 case PROCESSOR_PENTIUM4:
1234 case PROCESSOR_NOCONA:
1235 case PROCESSOR_CORE:
1236 case PROCESSOR_CORE2:
1237 case PROCESSOR_COREI7:
1238 case PROCESSOR_L1OM:
1239 case PROCESSOR_K1OM:
1240 case PROCESSOR_GENERIC64:
1241 patt = alt_long_patt;
1244 case PROCESSOR_ATHLON:
1246 case PROCESSOR_AMDFAM10:
1249 patt = alt_short_patt;
1251 case PROCESSOR_I386:
1252 case PROCESSOR_I486:
1253 case PROCESSOR_PENTIUM:
1254 case PROCESSOR_PENTIUMPRO:
1255 case PROCESSOR_GENERIC32:
1262 switch (fragP->tc_frag_data.tune)
1264 case PROCESSOR_UNKNOWN:
1265 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1266 PROCESSOR_UNKNOWN. */
1270 case PROCESSOR_I386:
1271 case PROCESSOR_I486:
1272 case PROCESSOR_PENTIUM:
1274 case PROCESSOR_ATHLON:
1276 case PROCESSOR_AMDFAM10:
1279 case PROCESSOR_GENERIC32:
1280 /* We use cpu_arch_isa_flags to check if we CAN optimize
1282 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1283 patt = alt_short_patt;
1287 case PROCESSOR_PENTIUMPRO:
1288 case PROCESSOR_PENTIUM4:
1289 case PROCESSOR_NOCONA:
1290 case PROCESSOR_CORE:
1291 case PROCESSOR_CORE2:
1292 case PROCESSOR_COREI7:
1293 case PROCESSOR_L1OM:
1294 case PROCESSOR_K1OM:
1295 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1296 patt = alt_long_patt;
1300 case PROCESSOR_GENERIC64:
1301 patt = alt_long_patt;
1306 if (patt == f32_patt)
1308 /* If the padding is less than 15 bytes, we use the normal
1309 ones. Otherwise, we use a jump instruction and adjust
1313 /* For 64bit, the limit is 3 bytes. */
1314 if (flag_code == CODE_64BIT
1315 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1320 memcpy (fragP->fr_literal + fragP->fr_fix,
1321 patt[count - 1], count);
1324 memcpy (fragP->fr_literal + fragP->fr_fix,
1326 /* Adjust jump offset. */
1327 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1332 /* Maximum length of an instruction is 15 byte. If the
1333 padding is greater than 15 bytes and we don't use jump,
1334 we have to break it into smaller pieces. */
1335 int padding = count;
1336 while (padding > 15)
1339 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1344 memcpy (fragP->fr_literal + fragP->fr_fix,
1345 patt [padding - 1], padding);
1348 fragP->fr_var = count;
1352 operand_type_all_zero (const union i386_operand_type *x)
1354 switch (ARRAY_SIZE(x->array))
1363 return !x->array[0];
1370 operand_type_set (union i386_operand_type *x, unsigned int v)
1372 switch (ARRAY_SIZE(x->array))
1387 operand_type_equal (const union i386_operand_type *x,
1388 const union i386_operand_type *y)
1390 switch (ARRAY_SIZE(x->array))
1393 if (x->array[2] != y->array[2])
1396 if (x->array[1] != y->array[1])
1399 return x->array[0] == y->array[0];
1407 cpu_flags_all_zero (const union i386_cpu_flags *x)
1409 switch (ARRAY_SIZE(x->array))
1418 return !x->array[0];
1425 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1427 switch (ARRAY_SIZE(x->array))
1442 cpu_flags_equal (const union i386_cpu_flags *x,
1443 const union i386_cpu_flags *y)
1445 switch (ARRAY_SIZE(x->array))
1448 if (x->array[2] != y->array[2])
1451 if (x->array[1] != y->array[1])
1454 return x->array[0] == y->array[0];
1462 cpu_flags_check_cpu64 (i386_cpu_flags f)
1464 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1465 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1468 static INLINE i386_cpu_flags
1469 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1471 switch (ARRAY_SIZE (x.array))
1474 x.array [2] &= y.array [2];
1476 x.array [1] &= y.array [1];
1478 x.array [0] &= y.array [0];
1486 static INLINE i386_cpu_flags
1487 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1489 switch (ARRAY_SIZE (x.array))
1492 x.array [2] |= y.array [2];
1494 x.array [1] |= y.array [1];
1496 x.array [0] |= y.array [0];
1504 static INLINE i386_cpu_flags
1505 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1507 switch (ARRAY_SIZE (x.array))
1510 x.array [2] &= ~y.array [2];
1512 x.array [1] &= ~y.array [1];
1514 x.array [0] &= ~y.array [0];
1522 #define CPU_FLAGS_ARCH_MATCH 0x1
1523 #define CPU_FLAGS_64BIT_MATCH 0x2
1524 #define CPU_FLAGS_AES_MATCH 0x4
1525 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1526 #define CPU_FLAGS_AVX_MATCH 0x10
1528 #define CPU_FLAGS_32BIT_MATCH \
1529 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1530 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1531 #define CPU_FLAGS_PERFECT_MATCH \
1532 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1534 /* Return CPU flags match bits. */
1537 cpu_flags_match (const insn_template *t)
1539 i386_cpu_flags x = t->cpu_flags;
1540 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1542 x.bitfield.cpu64 = 0;
1543 x.bitfield.cpuno64 = 0;
1545 if (cpu_flags_all_zero (&x))
1547 /* This instruction is available on all archs. */
1548 match |= CPU_FLAGS_32BIT_MATCH;
1552 /* This instruction is available only on some archs. */
1553 i386_cpu_flags cpu = cpu_arch_flags;
1555 cpu.bitfield.cpu64 = 0;
1556 cpu.bitfield.cpuno64 = 0;
1557 cpu = cpu_flags_and (x, cpu);
1558 if (!cpu_flags_all_zero (&cpu))
1560 if (x.bitfield.cpuavx)
1562 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1563 if (cpu.bitfield.cpuavx)
1565 /* Check SSE2AVX. */
1566 if (!t->opcode_modifier.sse2avx|| sse2avx)
1568 match |= (CPU_FLAGS_ARCH_MATCH
1569 | CPU_FLAGS_AVX_MATCH);
1571 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1572 match |= CPU_FLAGS_AES_MATCH;
1574 if (!x.bitfield.cpupclmul
1575 || cpu.bitfield.cpupclmul)
1576 match |= CPU_FLAGS_PCLMUL_MATCH;
1580 match |= CPU_FLAGS_ARCH_MATCH;
1583 match |= CPU_FLAGS_32BIT_MATCH;
1589 static INLINE i386_operand_type
1590 operand_type_and (i386_operand_type x, i386_operand_type y)
1592 switch (ARRAY_SIZE (x.array))
1595 x.array [2] &= y.array [2];
1597 x.array [1] &= y.array [1];
1599 x.array [0] &= y.array [0];
1607 static INLINE i386_operand_type
1608 operand_type_or (i386_operand_type x, i386_operand_type y)
1610 switch (ARRAY_SIZE (x.array))
1613 x.array [2] |= y.array [2];
1615 x.array [1] |= y.array [1];
1617 x.array [0] |= y.array [0];
1625 static INLINE i386_operand_type
1626 operand_type_xor (i386_operand_type x, i386_operand_type y)
1628 switch (ARRAY_SIZE (x.array))
1631 x.array [2] ^= y.array [2];
1633 x.array [1] ^= y.array [1];
1635 x.array [0] ^= y.array [0];
1643 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1644 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1645 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1646 static const i386_operand_type inoutportreg
1647 = OPERAND_TYPE_INOUTPORTREG;
1648 static const i386_operand_type reg16_inoutportreg
1649 = OPERAND_TYPE_REG16_INOUTPORTREG;
1650 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1651 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1652 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1653 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1654 static const i386_operand_type anydisp
1655 = OPERAND_TYPE_ANYDISP;
1656 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1657 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1658 static const i386_operand_type regzmm = OPERAND_TYPE_REGZMM;
1659 static const i386_operand_type regmask = OPERAND_TYPE_REGMASK;
1660 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1661 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1662 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1663 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1664 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1665 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1666 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1667 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1668 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1669 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1670 static const i386_operand_type regbnd = OPERAND_TYPE_REGBND;
1671 static const i386_operand_type vec_disp8 = OPERAND_TYPE_VEC_DISP8;
1682 operand_type_check (i386_operand_type t, enum operand_type c)
1687 return (t.bitfield.reg8
1690 || t.bitfield.reg64);
1693 return (t.bitfield.imm8
1697 || t.bitfield.imm32s
1698 || t.bitfield.imm64);
1701 return (t.bitfield.disp8
1702 || t.bitfield.disp16
1703 || t.bitfield.disp32
1704 || t.bitfield.disp32s
1705 || t.bitfield.disp64);
1708 return (t.bitfield.disp8
1709 || t.bitfield.disp16
1710 || t.bitfield.disp32
1711 || t.bitfield.disp32s
1712 || t.bitfield.disp64
1713 || t.bitfield.baseindex);
1722 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1723 operand J for instruction template T. */
1726 match_reg_size (const insn_template *t, unsigned int j)
1728 return !((i.types[j].bitfield.byte
1729 && !t->operand_types[j].bitfield.byte)
1730 || (i.types[j].bitfield.word
1731 && !t->operand_types[j].bitfield.word)
1732 || (i.types[j].bitfield.dword
1733 && !t->operand_types[j].bitfield.dword)
1734 || (i.types[j].bitfield.qword
1735 && !t->operand_types[j].bitfield.qword));
1738 /* Return 1 if there is no conflict in any size on operand J for
1739 instruction template T. */
1742 match_mem_size (const insn_template *t, unsigned int j)
1744 return (match_reg_size (t, j)
1745 && !((i.types[j].bitfield.unspecified
1746 && !t->operand_types[j].bitfield.unspecified)
1747 || (i.types[j].bitfield.fword
1748 && !t->operand_types[j].bitfield.fword)
1749 || (i.types[j].bitfield.tbyte
1750 && !t->operand_types[j].bitfield.tbyte)
1751 || (i.types[j].bitfield.xmmword
1752 && !t->operand_types[j].bitfield.xmmword)
1753 || (i.types[j].bitfield.ymmword
1754 && !t->operand_types[j].bitfield.ymmword)
1755 || (i.types[j].bitfield.zmmword
1756 && !t->operand_types[j].bitfield.zmmword)));
1759 /* Return 1 if there is no size conflict on any operands for
1760 instruction template T. */
1763 operand_size_match (const insn_template *t)
1768 /* Don't check jump instructions. */
1769 if (t->opcode_modifier.jump
1770 || t->opcode_modifier.jumpbyte
1771 || t->opcode_modifier.jumpdword
1772 || t->opcode_modifier.jumpintersegment)
1775 /* Check memory and accumulator operand size. */
1776 for (j = 0; j < i.operands; j++)
1778 if (t->operand_types[j].bitfield.anysize)
1781 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1787 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1796 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1799 i.error = operand_size_mismatch;
1803 /* Check reverse. */
1804 gas_assert (i.operands == 2);
1807 for (j = 0; j < 2; j++)
1809 if (t->operand_types[j].bitfield.acc
1810 && !match_reg_size (t, j ? 0 : 1))
1813 if (i.types[j].bitfield.mem
1814 && !match_mem_size (t, j ? 0 : 1))
1822 operand_type_match (i386_operand_type overlap,
1823 i386_operand_type given)
1825 i386_operand_type temp = overlap;
1827 temp.bitfield.jumpabsolute = 0;
1828 temp.bitfield.unspecified = 0;
1829 temp.bitfield.byte = 0;
1830 temp.bitfield.word = 0;
1831 temp.bitfield.dword = 0;
1832 temp.bitfield.fword = 0;
1833 temp.bitfield.qword = 0;
1834 temp.bitfield.tbyte = 0;
1835 temp.bitfield.xmmword = 0;
1836 temp.bitfield.ymmword = 0;
1837 temp.bitfield.zmmword = 0;
1838 if (operand_type_all_zero (&temp))
1841 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1842 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1846 i.error = operand_type_mismatch;
1850 /* If given types g0 and g1 are registers they must be of the same type
1851 unless the expected operand type register overlap is null.
1852 Note that Acc in a template matches every size of reg. */
1855 operand_type_register_match (i386_operand_type m0,
1856 i386_operand_type g0,
1857 i386_operand_type t0,
1858 i386_operand_type m1,
1859 i386_operand_type g1,
1860 i386_operand_type t1)
1862 if (!operand_type_check (g0, reg))
1865 if (!operand_type_check (g1, reg))
1868 if (g0.bitfield.reg8 == g1.bitfield.reg8
1869 && g0.bitfield.reg16 == g1.bitfield.reg16
1870 && g0.bitfield.reg32 == g1.bitfield.reg32
1871 && g0.bitfield.reg64 == g1.bitfield.reg64)
1874 if (m0.bitfield.acc)
1876 t0.bitfield.reg8 = 1;
1877 t0.bitfield.reg16 = 1;
1878 t0.bitfield.reg32 = 1;
1879 t0.bitfield.reg64 = 1;
1882 if (m1.bitfield.acc)
1884 t1.bitfield.reg8 = 1;
1885 t1.bitfield.reg16 = 1;
1886 t1.bitfield.reg32 = 1;
1887 t1.bitfield.reg64 = 1;
1890 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1891 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1892 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1893 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1896 i.error = register_type_mismatch;
1901 static INLINE unsigned int
1902 register_number (const reg_entry *r)
1904 unsigned int nr = r->reg_num;
1906 if (r->reg_flags & RegRex)
1912 static INLINE unsigned int
1913 mode_from_disp_size (i386_operand_type t)
1915 if (t.bitfield.disp8 || t.bitfield.vec_disp8)
1917 else if (t.bitfield.disp16
1918 || t.bitfield.disp32
1919 || t.bitfield.disp32s)
1926 fits_in_signed_byte (offsetT num)
1928 return (num >= -128) && (num <= 127);
1932 fits_in_unsigned_byte (offsetT num)
1934 return (num & 0xff) == num;
1938 fits_in_unsigned_word (offsetT num)
1940 return (num & 0xffff) == num;
1944 fits_in_signed_word (offsetT num)
1946 return (-32768 <= num) && (num <= 32767);
1950 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1955 return (!(((offsetT) -1 << 31) & num)
1956 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1958 } /* fits_in_signed_long() */
1961 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1966 return (num & (((offsetT) 2 << 31) - 1)) == num;
1968 } /* fits_in_unsigned_long() */
1971 fits_in_vec_disp8 (offsetT num)
1973 int shift = i.memshift;
1979 mask = (1 << shift) - 1;
1981 /* Return 0 if NUM isn't properly aligned. */
1985 /* Check if NUM will fit in 8bit after shift. */
1986 return fits_in_signed_byte (num >> shift);
1990 fits_in_imm4 (offsetT num)
1992 return (num & 0xf) == num;
1995 static i386_operand_type
1996 smallest_imm_type (offsetT num)
1998 i386_operand_type t;
2000 operand_type_set (&t, 0);
2001 t.bitfield.imm64 = 1;
2003 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
2005 /* This code is disabled on the 486 because all the Imm1 forms
2006 in the opcode table are slower on the i486. They're the
2007 versions with the implicitly specified single-position
2008 displacement, which has another syntax if you really want to
2010 t.bitfield.imm1 = 1;
2011 t.bitfield.imm8 = 1;
2012 t.bitfield.imm8s = 1;
2013 t.bitfield.imm16 = 1;
2014 t.bitfield.imm32 = 1;
2015 t.bitfield.imm32s = 1;
2017 else if (fits_in_signed_byte (num))
2019 t.bitfield.imm8 = 1;
2020 t.bitfield.imm8s = 1;
2021 t.bitfield.imm16 = 1;
2022 t.bitfield.imm32 = 1;
2023 t.bitfield.imm32s = 1;
2025 else if (fits_in_unsigned_byte (num))
2027 t.bitfield.imm8 = 1;
2028 t.bitfield.imm16 = 1;
2029 t.bitfield.imm32 = 1;
2030 t.bitfield.imm32s = 1;
2032 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
2034 t.bitfield.imm16 = 1;
2035 t.bitfield.imm32 = 1;
2036 t.bitfield.imm32s = 1;
2038 else if (fits_in_signed_long (num))
2040 t.bitfield.imm32 = 1;
2041 t.bitfield.imm32s = 1;
2043 else if (fits_in_unsigned_long (num))
2044 t.bitfield.imm32 = 1;
2050 offset_in_range (offsetT val, int size)
2056 case 1: mask = ((addressT) 1 << 8) - 1; break;
2057 case 2: mask = ((addressT) 1 << 16) - 1; break;
2058 case 4: mask = ((addressT) 2 << 31) - 1; break;
2060 case 8: mask = ((addressT) 2 << 63) - 1; break;
2066 /* If BFD64, sign extend val for 32bit address mode. */
2067 if (flag_code != CODE_64BIT
2068 || i.prefix[ADDR_PREFIX])
2069 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
2070 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
2073 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
2075 char buf1[40], buf2[40];
2077 sprint_value (buf1, val);
2078 sprint_value (buf2, val & mask);
2079 as_warn (_("%s shortened to %s"), buf1, buf2);
2093 a. PREFIX_EXIST if attempting to add a prefix where one from the
2094 same class already exists.
2095 b. PREFIX_LOCK if lock prefix is added.
2096 c. PREFIX_REP if rep/repne prefix is added.
2097 d. PREFIX_OTHER if other prefix is added.
2100 static enum PREFIX_GROUP
2101 add_prefix (unsigned int prefix)
2103 enum PREFIX_GROUP ret = PREFIX_OTHER;
2106 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
2107 && flag_code == CODE_64BIT)
2109 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
2110 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
2111 && (prefix & (REX_R | REX_X | REX_B))))
2122 case CS_PREFIX_OPCODE:
2123 case DS_PREFIX_OPCODE:
2124 case ES_PREFIX_OPCODE:
2125 case FS_PREFIX_OPCODE:
2126 case GS_PREFIX_OPCODE:
2127 case SS_PREFIX_OPCODE:
2131 case REPNE_PREFIX_OPCODE:
2132 case REPE_PREFIX_OPCODE:
2137 case LOCK_PREFIX_OPCODE:
2146 case ADDR_PREFIX_OPCODE:
2150 case DATA_PREFIX_OPCODE:
2154 if (i.prefix[q] != 0)
2162 i.prefix[q] |= prefix;
2165 as_bad (_("same type of prefix used twice"));
2171 update_code_flag (int value, int check)
2173 PRINTF_LIKE ((*as_error));
2175 flag_code = (enum flag_code) value;
2176 if (flag_code == CODE_64BIT)
2178 cpu_arch_flags.bitfield.cpu64 = 1;
2179 cpu_arch_flags.bitfield.cpuno64 = 0;
2183 cpu_arch_flags.bitfield.cpu64 = 0;
2184 cpu_arch_flags.bitfield.cpuno64 = 1;
2186 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
2189 as_error = as_fatal;
2192 (*as_error) (_("64bit mode not supported on `%s'."),
2193 cpu_arch_name ? cpu_arch_name : default_arch);
2195 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
2198 as_error = as_fatal;
2201 (*as_error) (_("32bit mode not supported on `%s'."),
2202 cpu_arch_name ? cpu_arch_name : default_arch);
2204 stackop_size = '\0';
2208 set_code_flag (int value)
2210 update_code_flag (value, 0);
2214 set_16bit_gcc_code_flag (int new_code_flag)
2216 flag_code = (enum flag_code) new_code_flag;
2217 if (flag_code != CODE_16BIT)
2219 cpu_arch_flags.bitfield.cpu64 = 0;
2220 cpu_arch_flags.bitfield.cpuno64 = 1;
2221 stackop_size = LONG_MNEM_SUFFIX;
2225 set_intel_syntax (int syntax_flag)
2227 /* Find out if register prefixing is specified. */
2228 int ask_naked_reg = 0;
2231 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2233 char *string = input_line_pointer;
2234 int e = get_symbol_end ();
2236 if (strcmp (string, "prefix") == 0)
2238 else if (strcmp (string, "noprefix") == 0)
2241 as_bad (_("bad argument to syntax directive."));
2242 *input_line_pointer = e;
2244 demand_empty_rest_of_line ();
2246 intel_syntax = syntax_flag;
2248 if (ask_naked_reg == 0)
2249 allow_naked_reg = (intel_syntax
2250 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2252 allow_naked_reg = (ask_naked_reg < 0);
2254 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2256 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2257 identifier_chars['$'] = intel_syntax ? '$' : 0;
2258 register_prefix = allow_naked_reg ? "" : "%";
2262 set_intel_mnemonic (int mnemonic_flag)
2264 intel_mnemonic = mnemonic_flag;
2268 set_allow_index_reg (int flag)
2270 allow_index_reg = flag;
2274 set_check (int what)
2276 enum check_kind *kind;
2281 kind = &operand_check;
2292 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2294 char *string = input_line_pointer;
2295 int e = get_symbol_end ();
2297 if (strcmp (string, "none") == 0)
2299 else if (strcmp (string, "warning") == 0)
2300 *kind = check_warning;
2301 else if (strcmp (string, "error") == 0)
2302 *kind = check_error;
2304 as_bad (_("bad argument to %s_check directive."), str);
2305 *input_line_pointer = e;
2308 as_bad (_("missing argument for %s_check directive"), str);
2310 demand_empty_rest_of_line ();
2314 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2315 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2317 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2318 static const char *arch;
2320 /* Intel LIOM is only supported on ELF. */
2326 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2327 use default_arch. */
2328 arch = cpu_arch_name;
2330 arch = default_arch;
2333 /* If we are targeting Intel L1OM, we must enable it. */
2334 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2335 || new_flag.bitfield.cpul1om)
2338 /* If we are targeting Intel K1OM, we must enable it. */
2339 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_K1OM
2340 || new_flag.bitfield.cpuk1om)
2343 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2348 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2352 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2354 char *string = input_line_pointer;
2355 int e = get_symbol_end ();
2357 i386_cpu_flags flags;
2359 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2361 if (strcmp (string, cpu_arch[j].name) == 0)
2363 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2367 cpu_arch_name = cpu_arch[j].name;
2368 cpu_sub_arch_name = NULL;
2369 cpu_arch_flags = cpu_arch[j].flags;
2370 if (flag_code == CODE_64BIT)
2372 cpu_arch_flags.bitfield.cpu64 = 1;
2373 cpu_arch_flags.bitfield.cpuno64 = 0;
2377 cpu_arch_flags.bitfield.cpu64 = 0;
2378 cpu_arch_flags.bitfield.cpuno64 = 1;
2380 cpu_arch_isa = cpu_arch[j].type;
2381 cpu_arch_isa_flags = cpu_arch[j].flags;
2382 if (!cpu_arch_tune_set)
2384 cpu_arch_tune = cpu_arch_isa;
2385 cpu_arch_tune_flags = cpu_arch_isa_flags;
2390 if (!cpu_arch[j].negated)
2391 flags = cpu_flags_or (cpu_arch_flags,
2394 flags = cpu_flags_and_not (cpu_arch_flags,
2396 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2398 if (cpu_sub_arch_name)
2400 char *name = cpu_sub_arch_name;
2401 cpu_sub_arch_name = concat (name,
2403 (const char *) NULL);
2407 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2408 cpu_arch_flags = flags;
2409 cpu_arch_isa_flags = flags;
2411 *input_line_pointer = e;
2412 demand_empty_rest_of_line ();
2416 if (j >= ARRAY_SIZE (cpu_arch))
2417 as_bad (_("no such architecture: `%s'"), string);
2419 *input_line_pointer = e;
2422 as_bad (_("missing cpu architecture"));
2424 no_cond_jump_promotion = 0;
2425 if (*input_line_pointer == ','
2426 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2428 char *string = ++input_line_pointer;
2429 int e = get_symbol_end ();
2431 if (strcmp (string, "nojumps") == 0)
2432 no_cond_jump_promotion = 1;
2433 else if (strcmp (string, "jumps") == 0)
2436 as_bad (_("no such architecture modifier: `%s'"), string);
2438 *input_line_pointer = e;
2441 demand_empty_rest_of_line ();
2444 enum bfd_architecture
2447 if (cpu_arch_isa == PROCESSOR_L1OM)
2449 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2450 || flag_code != CODE_64BIT)
2451 as_fatal (_("Intel L1OM is 64bit ELF only"));
2452 return bfd_arch_l1om;
2454 else if (cpu_arch_isa == PROCESSOR_K1OM)
2456 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2457 || flag_code != CODE_64BIT)
2458 as_fatal (_("Intel K1OM is 64bit ELF only"));
2459 return bfd_arch_k1om;
2462 return bfd_arch_i386;
2468 if (!strncmp (default_arch, "x86_64", 6))
2470 if (cpu_arch_isa == PROCESSOR_L1OM)
2472 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2473 || default_arch[6] != '\0')
2474 as_fatal (_("Intel L1OM is 64bit ELF only"));
2475 return bfd_mach_l1om;
2477 else if (cpu_arch_isa == PROCESSOR_K1OM)
2479 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2480 || default_arch[6] != '\0')
2481 as_fatal (_("Intel K1OM is 64bit ELF only"));
2482 return bfd_mach_k1om;
2484 else if (default_arch[6] == '\0')
2485 return bfd_mach_x86_64;
2487 return bfd_mach_x64_32;
2489 else if (!strcmp (default_arch, "i386"))
2490 return bfd_mach_i386_i386;
2492 as_fatal (_("unknown architecture"));
2498 const char *hash_err;
2500 /* Initialize op_hash hash table. */
2501 op_hash = hash_new ();
2504 const insn_template *optab;
2505 templates *core_optab;
2507 /* Setup for loop. */
2509 core_optab = (templates *) xmalloc (sizeof (templates));
2510 core_optab->start = optab;
2515 if (optab->name == NULL
2516 || strcmp (optab->name, (optab - 1)->name) != 0)
2518 /* different name --> ship out current template list;
2519 add to hash table; & begin anew. */
2520 core_optab->end = optab;
2521 hash_err = hash_insert (op_hash,
2523 (void *) core_optab);
2526 as_fatal (_("can't hash %s: %s"),
2530 if (optab->name == NULL)
2532 core_optab = (templates *) xmalloc (sizeof (templates));
2533 core_optab->start = optab;
2538 /* Initialize reg_hash hash table. */
2539 reg_hash = hash_new ();
2541 const reg_entry *regtab;
2542 unsigned int regtab_size = i386_regtab_size;
2544 for (regtab = i386_regtab; regtab_size--; regtab++)
2546 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2548 as_fatal (_("can't hash %s: %s"),
2554 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2559 for (c = 0; c < 256; c++)
2564 mnemonic_chars[c] = c;
2565 register_chars[c] = c;
2566 operand_chars[c] = c;
2568 else if (ISLOWER (c))
2570 mnemonic_chars[c] = c;
2571 register_chars[c] = c;
2572 operand_chars[c] = c;
2574 else if (ISUPPER (c))
2576 mnemonic_chars[c] = TOLOWER (c);
2577 register_chars[c] = mnemonic_chars[c];
2578 operand_chars[c] = c;
2580 else if (c == '{' || c == '}')
2581 operand_chars[c] = c;
2583 if (ISALPHA (c) || ISDIGIT (c))
2584 identifier_chars[c] = c;
2587 identifier_chars[c] = c;
2588 operand_chars[c] = c;
2593 identifier_chars['@'] = '@';
2596 identifier_chars['?'] = '?';
2597 operand_chars['?'] = '?';
2599 digit_chars['-'] = '-';
2600 mnemonic_chars['_'] = '_';
2601 mnemonic_chars['-'] = '-';
2602 mnemonic_chars['.'] = '.';
2603 identifier_chars['_'] = '_';
2604 identifier_chars['.'] = '.';
2606 for (p = operand_special_chars; *p != '\0'; p++)
2607 operand_chars[(unsigned char) *p] = *p;
2610 if (flag_code == CODE_64BIT)
2612 #if defined (OBJ_COFF) && defined (TE_PE)
2613 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2616 x86_dwarf2_return_column = 16;
2618 x86_cie_data_alignment = -8;
2622 x86_dwarf2_return_column = 8;
2623 x86_cie_data_alignment = -4;
2628 i386_print_statistics (FILE *file)
2630 hash_print_statistics (file, "i386 opcode", op_hash);
2631 hash_print_statistics (file, "i386 register", reg_hash);
2636 /* Debugging routines for md_assemble. */
2637 static void pte (insn_template *);
2638 static void pt (i386_operand_type);
2639 static void pe (expressionS *);
2640 static void ps (symbolS *);
2643 pi (char *line, i386_insn *x)
2647 fprintf (stdout, "%s: template ", line);
2649 fprintf (stdout, " address: base %s index %s scale %x\n",
2650 x->base_reg ? x->base_reg->reg_name : "none",
2651 x->index_reg ? x->index_reg->reg_name : "none",
2652 x->log2_scale_factor);
2653 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2654 x->rm.mode, x->rm.reg, x->rm.regmem);
2655 fprintf (stdout, " sib: base %x index %x scale %x\n",
2656 x->sib.base, x->sib.index, x->sib.scale);
2657 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2658 (x->rex & REX_W) != 0,
2659 (x->rex & REX_R) != 0,
2660 (x->rex & REX_X) != 0,
2661 (x->rex & REX_B) != 0);
2662 for (j = 0; j < x->operands; j++)
2664 fprintf (stdout, " #%d: ", j + 1);
2666 fprintf (stdout, "\n");
2667 if (x->types[j].bitfield.reg8
2668 || x->types[j].bitfield.reg16
2669 || x->types[j].bitfield.reg32
2670 || x->types[j].bitfield.reg64
2671 || x->types[j].bitfield.regmmx
2672 || x->types[j].bitfield.regxmm
2673 || x->types[j].bitfield.regymm
2674 || x->types[j].bitfield.regzmm
2675 || x->types[j].bitfield.sreg2
2676 || x->types[j].bitfield.sreg3
2677 || x->types[j].bitfield.control
2678 || x->types[j].bitfield.debug
2679 || x->types[j].bitfield.test)
2680 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2681 if (operand_type_check (x->types[j], imm))
2683 if (operand_type_check (x->types[j], disp))
2684 pe (x->op[j].disps);
2689 pte (insn_template *t)
2692 fprintf (stdout, " %d operands ", t->operands);
2693 fprintf (stdout, "opcode %x ", t->base_opcode);
2694 if (t->extension_opcode != None)
2695 fprintf (stdout, "ext %x ", t->extension_opcode);
2696 if (t->opcode_modifier.d)
2697 fprintf (stdout, "D");
2698 if (t->opcode_modifier.w)
2699 fprintf (stdout, "W");
2700 fprintf (stdout, "\n");
2701 for (j = 0; j < t->operands; j++)
2703 fprintf (stdout, " #%d type ", j + 1);
2704 pt (t->operand_types[j]);
2705 fprintf (stdout, "\n");
2712 fprintf (stdout, " operation %d\n", e->X_op);
2713 fprintf (stdout, " add_number %ld (%lx)\n",
2714 (long) e->X_add_number, (long) e->X_add_number);
2715 if (e->X_add_symbol)
2717 fprintf (stdout, " add_symbol ");
2718 ps (e->X_add_symbol);
2719 fprintf (stdout, "\n");
2723 fprintf (stdout, " op_symbol ");
2724 ps (e->X_op_symbol);
2725 fprintf (stdout, "\n");
2732 fprintf (stdout, "%s type %s%s",
2734 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2735 segment_name (S_GET_SEGMENT (s)));
2738 static struct type_name
2740 i386_operand_type mask;
2743 const type_names[] =
2745 { OPERAND_TYPE_REG8, "r8" },
2746 { OPERAND_TYPE_REG16, "r16" },
2747 { OPERAND_TYPE_REG32, "r32" },
2748 { OPERAND_TYPE_REG64, "r64" },
2749 { OPERAND_TYPE_IMM8, "i8" },
2750 { OPERAND_TYPE_IMM8, "i8s" },
2751 { OPERAND_TYPE_IMM16, "i16" },
2752 { OPERAND_TYPE_IMM32, "i32" },
2753 { OPERAND_TYPE_IMM32S, "i32s" },
2754 { OPERAND_TYPE_IMM64, "i64" },
2755 { OPERAND_TYPE_IMM1, "i1" },
2756 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2757 { OPERAND_TYPE_DISP8, "d8" },
2758 { OPERAND_TYPE_DISP16, "d16" },
2759 { OPERAND_TYPE_DISP32, "d32" },
2760 { OPERAND_TYPE_DISP32S, "d32s" },
2761 { OPERAND_TYPE_DISP64, "d64" },
2762 { OPERAND_TYPE_VEC_DISP8, "Vector d8" },
2763 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2764 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2765 { OPERAND_TYPE_CONTROL, "control reg" },
2766 { OPERAND_TYPE_TEST, "test reg" },
2767 { OPERAND_TYPE_DEBUG, "debug reg" },
2768 { OPERAND_TYPE_FLOATREG, "FReg" },
2769 { OPERAND_TYPE_FLOATACC, "FAcc" },
2770 { OPERAND_TYPE_SREG2, "SReg2" },
2771 { OPERAND_TYPE_SREG3, "SReg3" },
2772 { OPERAND_TYPE_ACC, "Acc" },
2773 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2774 { OPERAND_TYPE_REGMMX, "rMMX" },
2775 { OPERAND_TYPE_REGXMM, "rXMM" },
2776 { OPERAND_TYPE_REGYMM, "rYMM" },
2777 { OPERAND_TYPE_REGZMM, "rZMM" },
2778 { OPERAND_TYPE_REGMASK, "Mask reg" },
2779 { OPERAND_TYPE_ESSEG, "es" },
2783 pt (i386_operand_type t)
2786 i386_operand_type a;
2788 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2790 a = operand_type_and (t, type_names[j].mask);
2791 if (!operand_type_all_zero (&a))
2792 fprintf (stdout, "%s, ", type_names[j].name);
2797 #endif /* DEBUG386 */
2799 static bfd_reloc_code_real_type
2800 reloc (unsigned int size,
2804 bfd_reloc_code_real_type other)
2806 if (other != NO_RELOC)
2808 reloc_howto_type *rel;
2813 case BFD_RELOC_X86_64_GOT32:
2814 return BFD_RELOC_X86_64_GOT64;
2816 case BFD_RELOC_X86_64_PLTOFF64:
2817 return BFD_RELOC_X86_64_PLTOFF64;
2819 case BFD_RELOC_X86_64_GOTPC32:
2820 other = BFD_RELOC_X86_64_GOTPC64;
2822 case BFD_RELOC_X86_64_GOTPCREL:
2823 other = BFD_RELOC_X86_64_GOTPCREL64;
2825 case BFD_RELOC_X86_64_TPOFF32:
2826 other = BFD_RELOC_X86_64_TPOFF64;
2828 case BFD_RELOC_X86_64_DTPOFF32:
2829 other = BFD_RELOC_X86_64_DTPOFF64;
2835 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2836 if (other == BFD_RELOC_SIZE32)
2839 return BFD_RELOC_SIZE64;
2841 as_bad (_("there are no pc-relative size relocations"));
2845 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2846 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
2849 rel = bfd_reloc_type_lookup (stdoutput, other);
2851 as_bad (_("unknown relocation (%u)"), other);
2852 else if (size != bfd_get_reloc_size (rel))
2853 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2854 bfd_get_reloc_size (rel),
2856 else if (pcrel && !rel->pc_relative)
2857 as_bad (_("non-pc-relative relocation for pc-relative field"));
2858 else if ((rel->complain_on_overflow == complain_overflow_signed
2860 || (rel->complain_on_overflow == complain_overflow_unsigned
2862 as_bad (_("relocated field and relocation type differ in signedness"));
2871 as_bad (_("there are no unsigned pc-relative relocations"));
2874 case 1: return BFD_RELOC_8_PCREL;
2875 case 2: return BFD_RELOC_16_PCREL;
2876 case 4: return (bnd_prefix && object_64bit
2877 ? BFD_RELOC_X86_64_PC32_BND
2878 : BFD_RELOC_32_PCREL);
2879 case 8: return BFD_RELOC_64_PCREL;
2881 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2888 case 4: return BFD_RELOC_X86_64_32S;
2893 case 1: return BFD_RELOC_8;
2894 case 2: return BFD_RELOC_16;
2895 case 4: return BFD_RELOC_32;
2896 case 8: return BFD_RELOC_64;
2898 as_bad (_("cannot do %s %u byte relocation"),
2899 sign > 0 ? "signed" : "unsigned", size);
2905 /* Here we decide which fixups can be adjusted to make them relative to
2906 the beginning of the section instead of the symbol. Basically we need
2907 to make sure that the dynamic relocations are done correctly, so in
2908 some cases we force the original symbol to be used. */
2911 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2913 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2917 /* Don't adjust pc-relative references to merge sections in 64-bit
2919 if (use_rela_relocations
2920 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2924 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2925 and changed later by validate_fix. */
2926 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2927 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2930 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
2931 for size relocations. */
2932 if (fixP->fx_r_type == BFD_RELOC_SIZE32
2933 || fixP->fx_r_type == BFD_RELOC_SIZE64
2934 || fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2935 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2936 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2937 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2938 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2939 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2940 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2941 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2942 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2943 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2944 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2945 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2946 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2947 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2948 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2949 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2950 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2951 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2952 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2953 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2954 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2955 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2956 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2957 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2958 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2959 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2960 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2961 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2968 intel_float_operand (const char *mnemonic)
2970 /* Note that the value returned is meaningful only for opcodes with (memory)
2971 operands, hence the code here is free to improperly handle opcodes that
2972 have no operands (for better performance and smaller code). */
2974 if (mnemonic[0] != 'f')
2975 return 0; /* non-math */
2977 switch (mnemonic[1])
2979 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2980 the fs segment override prefix not currently handled because no
2981 call path can make opcodes without operands get here */
2983 return 2 /* integer op */;
2985 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2986 return 3; /* fldcw/fldenv */
2989 if (mnemonic[2] != 'o' /* fnop */)
2990 return 3; /* non-waiting control op */
2993 if (mnemonic[2] == 's')
2994 return 3; /* frstor/frstpm */
2997 if (mnemonic[2] == 'a')
2998 return 3; /* fsave */
2999 if (mnemonic[2] == 't')
3001 switch (mnemonic[3])
3003 case 'c': /* fstcw */
3004 case 'd': /* fstdw */
3005 case 'e': /* fstenv */
3006 case 's': /* fsts[gw] */
3012 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
3013 return 0; /* fxsave/fxrstor are not really math ops */
3020 /* Build the VEX prefix. */
3023 build_vex_prefix (const insn_template *t)
3025 unsigned int register_specifier;
3026 unsigned int implied_prefix;
3027 unsigned int vector_length;
3029 /* Check register specifier. */
3030 if (i.vex.register_specifier)
3032 register_specifier =
3033 ~register_number (i.vex.register_specifier) & 0xf;
3034 gas_assert ((i.vex.register_specifier->reg_flags & RegVRex) == 0);
3037 register_specifier = 0xf;
3039 /* Use 2-byte VEX prefix by swappping destination and source
3042 && i.operands == i.reg_operands
3043 && i.tm.opcode_modifier.vexopcode == VEX0F
3044 && i.tm.opcode_modifier.s
3047 unsigned int xchg = i.operands - 1;
3048 union i386_op temp_op;
3049 i386_operand_type temp_type;
3051 temp_type = i.types[xchg];
3052 i.types[xchg] = i.types[0];
3053 i.types[0] = temp_type;
3054 temp_op = i.op[xchg];
3055 i.op[xchg] = i.op[0];
3058 gas_assert (i.rm.mode == 3);
3062 i.rm.regmem = i.rm.reg;
3065 /* Use the next insn. */
3069 if (i.tm.opcode_modifier.vex == VEXScalar)
3070 vector_length = avxscalar;
3072 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
3074 switch ((i.tm.base_opcode >> 8) & 0xff)
3079 case DATA_PREFIX_OPCODE:
3082 case REPE_PREFIX_OPCODE:
3085 case REPNE_PREFIX_OPCODE:
3092 /* Use 2-byte VEX prefix if possible. */
3093 if (i.tm.opcode_modifier.vexopcode == VEX0F
3094 && i.tm.opcode_modifier.vexw != VEXW1
3095 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
3097 /* 2-byte VEX prefix. */
3101 i.vex.bytes[0] = 0xc5;
3103 /* Check the REX.R bit. */
3104 r = (i.rex & REX_R) ? 0 : 1;
3105 i.vex.bytes[1] = (r << 7
3106 | register_specifier << 3
3107 | vector_length << 2
3112 /* 3-byte VEX prefix. */
3117 switch (i.tm.opcode_modifier.vexopcode)
3121 i.vex.bytes[0] = 0xc4;
3125 i.vex.bytes[0] = 0xc4;
3129 i.vex.bytes[0] = 0xc4;
3133 i.vex.bytes[0] = 0x8f;
3137 i.vex.bytes[0] = 0x8f;
3141 i.vex.bytes[0] = 0x8f;
3147 /* The high 3 bits of the second VEX byte are 1's compliment
3148 of RXB bits from REX. */
3149 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3151 /* Check the REX.W bit. */
3152 w = (i.rex & REX_W) ? 1 : 0;
3153 if (i.tm.opcode_modifier.vexw)
3158 if (i.tm.opcode_modifier.vexw == VEXW1)
3162 i.vex.bytes[2] = (w << 7
3163 | register_specifier << 3
3164 | vector_length << 2
3169 /* Build the EVEX prefix. */
3172 build_evex_prefix (void)
3174 unsigned int register_specifier;
3175 unsigned int implied_prefix;
3177 rex_byte vrex_used = 0;
3179 /* Check register specifier. */
3180 if (i.vex.register_specifier)
3182 gas_assert ((i.vrex & REX_X) == 0);
3184 register_specifier = i.vex.register_specifier->reg_num;
3185 if ((i.vex.register_specifier->reg_flags & RegRex))
3186 register_specifier += 8;
3187 /* The upper 16 registers are encoded in the fourth byte of the
3189 if (!(i.vex.register_specifier->reg_flags & RegVRex))
3190 i.vex.bytes[3] = 0x8;
3191 register_specifier = ~register_specifier & 0xf;
3195 register_specifier = 0xf;
3197 /* Encode upper 16 vector index register in the fourth byte of
3199 if (!(i.vrex & REX_X))
3200 i.vex.bytes[3] = 0x8;
3205 switch ((i.tm.base_opcode >> 8) & 0xff)
3210 case DATA_PREFIX_OPCODE:
3213 case REPE_PREFIX_OPCODE:
3216 case REPNE_PREFIX_OPCODE:
3223 /* 4 byte EVEX prefix. */
3225 i.vex.bytes[0] = 0x62;
3228 switch (i.tm.opcode_modifier.vexopcode)
3244 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
3246 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
3248 /* The fifth bit of the second EVEX byte is 1's compliment of the
3249 REX_R bit in VREX. */
3250 if (!(i.vrex & REX_R))
3251 i.vex.bytes[1] |= 0x10;
3255 if ((i.reg_operands + i.imm_operands) == i.operands)
3257 /* When all operands are registers, the REX_X bit in REX is not
3258 used. We reuse it to encode the upper 16 registers, which is
3259 indicated by the REX_B bit in VREX. The REX_X bit is encoded
3260 as 1's compliment. */
3261 if ((i.vrex & REX_B))
3264 i.vex.bytes[1] &= ~0x40;
3268 /* EVEX instructions shouldn't need the REX prefix. */
3269 i.vrex &= ~vrex_used;
3270 gas_assert (i.vrex == 0);
3272 /* Check the REX.W bit. */
3273 w = (i.rex & REX_W) ? 1 : 0;
3274 if (i.tm.opcode_modifier.vexw)
3276 if (i.tm.opcode_modifier.vexw == VEXW1)
3279 /* If w is not set it means we are dealing with WIG instruction. */
3282 if (evexwig == evexw1)
3286 /* Encode the U bit. */
3287 implied_prefix |= 0x4;
3289 /* The third byte of the EVEX prefix. */
3290 i.vex.bytes[2] = (w << 7 | register_specifier << 3 | implied_prefix);
3292 /* The fourth byte of the EVEX prefix. */
3293 /* The zeroing-masking bit. */
3294 if (i.mask && i.mask->zeroing)
3295 i.vex.bytes[3] |= 0x80;
3297 /* Don't always set the broadcast bit if there is no RC. */
3300 /* Encode the vector length. */
3301 unsigned int vec_length;
3303 switch (i.tm.opcode_modifier.evex)
3305 case EVEXLIG: /* LL' is ignored */
3306 vec_length = evexlig << 5;
3309 vec_length = 0 << 5;
3312 vec_length = 1 << 5;
3315 vec_length = 2 << 5;
3321 i.vex.bytes[3] |= vec_length;
3322 /* Encode the broadcast bit. */
3324 i.vex.bytes[3] |= 0x10;
3328 if (i.rounding->type != saeonly)
3329 i.vex.bytes[3] |= 0x10 | (i.rounding->type << 5);
3331 i.vex.bytes[3] |= 0x10;
3334 if (i.mask && i.mask->mask)
3335 i.vex.bytes[3] |= i.mask->mask->reg_num;
3339 process_immext (void)
3343 if ((i.tm.cpu_flags.bitfield.cpusse3 || i.tm.cpu_flags.bitfield.cpusvme)
3346 /* MONITOR/MWAIT as well as SVME instructions have fixed operands
3347 with an opcode suffix which is coded in the same place as an
3348 8-bit immediate field would be.
3349 Here we check those operands and remove them afterwards. */
3352 for (x = 0; x < i.operands; x++)
3353 if (register_number (i.op[x].regs) != x)
3354 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
3355 register_prefix, i.op[x].regs->reg_name, x + 1,
3361 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
3362 which is coded in the same place as an 8-bit immediate field
3363 would be. Here we fake an 8-bit immediate operand from the
3364 opcode suffix stored in tm.extension_opcode.
3366 AVX instructions also use this encoding, for some of
3367 3 argument instructions. */
3369 gas_assert (i.imm_operands <= 1
3371 || ((i.tm.opcode_modifier.vex
3372 || i.tm.opcode_modifier.evex)
3373 && i.operands <= 4)));
3375 exp = &im_expressions[i.imm_operands++];
3376 i.op[i.operands].imms = exp;
3377 i.types[i.operands] = imm8;
3379 exp->X_op = O_constant;
3380 exp->X_add_number = i.tm.extension_opcode;
3381 i.tm.extension_opcode = None;
3388 switch (i.tm.opcode_modifier.hleprefixok)
3393 as_bad (_("invalid instruction `%s' after `%s'"),
3394 i.tm.name, i.hle_prefix);
3397 if (i.prefix[LOCK_PREFIX])
3399 as_bad (_("missing `lock' with `%s'"), i.hle_prefix);
3403 case HLEPrefixRelease:
3404 if (i.prefix[HLE_PREFIX] != XRELEASE_PREFIX_OPCODE)
3406 as_bad (_("instruction `%s' after `xacquire' not allowed"),
3410 if (i.mem_operands == 0
3411 || !operand_type_check (i.types[i.operands - 1], anymem))
3413 as_bad (_("memory destination needed for instruction `%s'"
3414 " after `xrelease'"), i.tm.name);
3421 /* This is the guts of the machine-dependent assembler. LINE points to a
3422 machine dependent instruction. This function is supposed to emit
3423 the frags/bytes it assembles to. */
3426 md_assemble (char *line)
3429 char mnemonic[MAX_MNEM_SIZE];
3430 const insn_template *t;
3432 /* Initialize globals. */
3433 memset (&i, '\0', sizeof (i));
3434 for (j = 0; j < MAX_OPERANDS; j++)
3435 i.reloc[j] = NO_RELOC;
3436 memset (disp_expressions, '\0', sizeof (disp_expressions));
3437 memset (im_expressions, '\0', sizeof (im_expressions));
3438 save_stack_p = save_stack;
3440 /* First parse an instruction mnemonic & call i386_operand for the operands.
3441 We assume that the scrubber has arranged it so that line[0] is the valid
3442 start of a (possibly prefixed) mnemonic. */
3444 line = parse_insn (line, mnemonic);
3448 line = parse_operands (line, mnemonic);
3453 /* Now we've parsed the mnemonic into a set of templates, and have the
3454 operands at hand. */
3456 /* All intel opcodes have reversed operands except for "bound" and
3457 "enter". We also don't reverse intersegment "jmp" and "call"
3458 instructions with 2 immediate operands so that the immediate segment
3459 precedes the offset, as it does when in AT&T mode. */
3462 && (strcmp (mnemonic, "bound") != 0)
3463 && (strcmp (mnemonic, "invlpga") != 0)
3464 && !(operand_type_check (i.types[0], imm)
3465 && operand_type_check (i.types[1], imm)))
3468 /* The order of the immediates should be reversed
3469 for 2 immediates extrq and insertq instructions */
3470 if (i.imm_operands == 2
3471 && (strcmp (mnemonic, "extrq") == 0
3472 || strcmp (mnemonic, "insertq") == 0))
3473 swap_2_operands (0, 1);
3478 /* Don't optimize displacement for movabs since it only takes 64bit
3481 && i.disp_encoding != disp_encoding_32bit
3482 && (flag_code != CODE_64BIT
3483 || strcmp (mnemonic, "movabs") != 0))
3486 /* Next, we find a template that matches the given insn,
3487 making sure the overlap of the given operands types is consistent
3488 with the template operand types. */
3490 if (!(t = match_template ()))
3493 if (sse_check != check_none
3494 && !i.tm.opcode_modifier.noavx
3495 && (i.tm.cpu_flags.bitfield.cpusse
3496 || i.tm.cpu_flags.bitfield.cpusse2
3497 || i.tm.cpu_flags.bitfield.cpusse3
3498 || i.tm.cpu_flags.bitfield.cpussse3
3499 || i.tm.cpu_flags.bitfield.cpusse4_1
3500 || i.tm.cpu_flags.bitfield.cpusse4_2))
3502 (sse_check == check_warning
3504 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3507 /* Zap movzx and movsx suffix. The suffix has been set from
3508 "word ptr" or "byte ptr" on the source operand in Intel syntax
3509 or extracted from mnemonic in AT&T syntax. But we'll use
3510 the destination register to choose the suffix for encoding. */
3511 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3513 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3514 there is no suffix, the default will be byte extension. */
3515 if (i.reg_operands != 2
3518 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3523 if (i.tm.opcode_modifier.fwait)
3524 if (!add_prefix (FWAIT_OPCODE))
3527 /* Check if REP prefix is OK. */
3528 if (i.rep_prefix && !i.tm.opcode_modifier.repprefixok)
3530 as_bad (_("invalid instruction `%s' after `%s'"),
3531 i.tm.name, i.rep_prefix);
3535 /* Check for lock without a lockable instruction. Destination operand
3536 must be memory unless it is xchg (0x86). */
3537 if (i.prefix[LOCK_PREFIX]
3538 && (!i.tm.opcode_modifier.islockable
3539 || i.mem_operands == 0
3540 || (i.tm.base_opcode != 0x86
3541 && !operand_type_check (i.types[i.operands - 1], anymem))))
3543 as_bad (_("expecting lockable instruction after `lock'"));
3547 /* Check if HLE prefix is OK. */
3548 if (i.hle_prefix && !check_hle ())
3551 /* Check BND prefix. */
3552 if (i.bnd_prefix && !i.tm.opcode_modifier.bndprefixok)
3553 as_bad (_("expecting valid branch instruction after `bnd'"));
3555 if (i.tm.cpu_flags.bitfield.cpumpx
3556 && flag_code == CODE_64BIT
3557 && i.prefix[ADDR_PREFIX])
3558 as_bad (_("32-bit address isn't allowed in 64-bit MPX instructions."));
3560 /* Insert BND prefix. */
3562 && i.tm.opcode_modifier.bndprefixok
3563 && !i.prefix[BND_PREFIX])
3564 add_prefix (BND_PREFIX_OPCODE);
3566 /* Check string instruction segment overrides. */
3567 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3569 if (!check_string ())
3571 i.disp_operands = 0;
3574 if (!process_suffix ())
3577 /* Update operand types. */
3578 for (j = 0; j < i.operands; j++)
3579 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3581 /* Make still unresolved immediate matches conform to size of immediate
3582 given in i.suffix. */
3583 if (!finalize_imm ())
3586 if (i.types[0].bitfield.imm1)
3587 i.imm_operands = 0; /* kludge for shift insns. */
3589 /* We only need to check those implicit registers for instructions
3590 with 3 operands or less. */
3591 if (i.operands <= 3)
3592 for (j = 0; j < i.operands; j++)
3593 if (i.types[j].bitfield.inoutportreg
3594 || i.types[j].bitfield.shiftcount
3595 || i.types[j].bitfield.acc
3596 || i.types[j].bitfield.floatacc)
3599 /* ImmExt should be processed after SSE2AVX. */
3600 if (!i.tm.opcode_modifier.sse2avx
3601 && i.tm.opcode_modifier.immext)
3604 /* For insns with operands there are more diddles to do to the opcode. */
3607 if (!process_operands ())
3610 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3612 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3613 as_warn (_("translating to `%sp'"), i.tm.name);
3616 if (i.tm.opcode_modifier.vex)
3617 build_vex_prefix (t);
3619 if (i.tm.opcode_modifier.evex)
3620 build_evex_prefix ();
3622 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3623 instructions may define INT_OPCODE as well, so avoid this corner
3624 case for those instructions that use MODRM. */
3625 if (i.tm.base_opcode == INT_OPCODE
3626 && !i.tm.opcode_modifier.modrm
3627 && i.op[0].imms->X_add_number == 3)
3629 i.tm.base_opcode = INT3_OPCODE;
3633 if ((i.tm.opcode_modifier.jump
3634 || i.tm.opcode_modifier.jumpbyte
3635 || i.tm.opcode_modifier.jumpdword)
3636 && i.op[0].disps->X_op == O_constant)
3638 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3639 the absolute address given by the constant. Since ix86 jumps and
3640 calls are pc relative, we need to generate a reloc. */
3641 i.op[0].disps->X_add_symbol = &abs_symbol;
3642 i.op[0].disps->X_op = O_symbol;
3645 if (i.tm.opcode_modifier.rex64)
3648 /* For 8 bit registers we need an empty rex prefix. Also if the
3649 instruction already has a prefix, we need to convert old
3650 registers to new ones. */
3652 if ((i.types[0].bitfield.reg8
3653 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3654 || (i.types[1].bitfield.reg8
3655 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3656 || ((i.types[0].bitfield.reg8
3657 || i.types[1].bitfield.reg8)
3662 i.rex |= REX_OPCODE;
3663 for (x = 0; x < 2; x++)
3665 /* Look for 8 bit operand that uses old registers. */
3666 if (i.types[x].bitfield.reg8
3667 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3669 /* In case it is "hi" register, give up. */
3670 if (i.op[x].regs->reg_num > 3)
3671 as_bad (_("can't encode register '%s%s' in an "
3672 "instruction requiring REX prefix."),
3673 register_prefix, i.op[x].regs->reg_name);
3675 /* Otherwise it is equivalent to the extended register.
3676 Since the encoding doesn't change this is merely
3677 cosmetic cleanup for debug output. */
3679 i.op[x].regs = i.op[x].regs + 8;
3685 add_prefix (REX_OPCODE | i.rex);
3687 /* We are ready to output the insn. */
3692 parse_insn (char *line, char *mnemonic)
3695 char *token_start = l;
3698 const insn_template *t;
3704 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3709 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3711 as_bad (_("no such instruction: `%s'"), token_start);
3716 if (!is_space_char (*l)
3717 && *l != END_OF_INSN
3719 || (*l != PREFIX_SEPARATOR
3722 as_bad (_("invalid character %s in mnemonic"),
3723 output_invalid (*l));
3726 if (token_start == l)
3728 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3729 as_bad (_("expecting prefix; got nothing"));
3731 as_bad (_("expecting mnemonic; got nothing"));
3735 /* Look up instruction (or prefix) via hash table. */
3736 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3738 if (*l != END_OF_INSN
3739 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3740 && current_templates
3741 && current_templates->start->opcode_modifier.isprefix)
3743 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3745 as_bad ((flag_code != CODE_64BIT
3746 ? _("`%s' is only supported in 64-bit mode")
3747 : _("`%s' is not supported in 64-bit mode")),
3748 current_templates->start->name);
3751 /* If we are in 16-bit mode, do not allow addr16 or data16.
3752 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3753 if ((current_templates->start->opcode_modifier.size16
3754 || current_templates->start->opcode_modifier.size32)
3755 && flag_code != CODE_64BIT
3756 && (current_templates->start->opcode_modifier.size32
3757 ^ (flag_code == CODE_16BIT)))
3759 as_bad (_("redundant %s prefix"),
3760 current_templates->start->name);
3763 /* Add prefix, checking for repeated prefixes. */
3764 switch (add_prefix (current_templates->start->base_opcode))
3769 if (current_templates->start->cpu_flags.bitfield.cpuhle)
3770 i.hle_prefix = current_templates->start->name;
3771 else if (current_templates->start->cpu_flags.bitfield.cpumpx)
3772 i.bnd_prefix = current_templates->start->name;
3774 i.rep_prefix = current_templates->start->name;
3779 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3786 if (!current_templates)
3788 /* Check if we should swap operand or force 32bit displacement in
3790 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3792 else if (mnem_p - 3 == dot_p
3795 i.disp_encoding = disp_encoding_8bit;
3796 else if (mnem_p - 4 == dot_p
3800 i.disp_encoding = disp_encoding_32bit;
3805 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3808 if (!current_templates)
3811 /* See if we can get a match by trimming off a suffix. */
3814 case WORD_MNEM_SUFFIX:
3815 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3816 i.suffix = SHORT_MNEM_SUFFIX;
3818 case BYTE_MNEM_SUFFIX:
3819 case QWORD_MNEM_SUFFIX:
3820 i.suffix = mnem_p[-1];
3822 current_templates = (const templates *) hash_find (op_hash,
3825 case SHORT_MNEM_SUFFIX:
3826 case LONG_MNEM_SUFFIX:
3829 i.suffix = mnem_p[-1];
3831 current_templates = (const templates *) hash_find (op_hash,
3840 if (intel_float_operand (mnemonic) == 1)
3841 i.suffix = SHORT_MNEM_SUFFIX;
3843 i.suffix = LONG_MNEM_SUFFIX;
3845 current_templates = (const templates *) hash_find (op_hash,
3850 if (!current_templates)
3852 as_bad (_("no such instruction: `%s'"), token_start);
3857 if (current_templates->start->opcode_modifier.jump
3858 || current_templates->start->opcode_modifier.jumpbyte)
3860 /* Check for a branch hint. We allow ",pt" and ",pn" for
3861 predict taken and predict not taken respectively.
3862 I'm not sure that branch hints actually do anything on loop
3863 and jcxz insns (JumpByte) for current Pentium4 chips. They
3864 may work in the future and it doesn't hurt to accept them
3866 if (l[0] == ',' && l[1] == 'p')
3870 if (!add_prefix (DS_PREFIX_OPCODE))
3874 else if (l[2] == 'n')
3876 if (!add_prefix (CS_PREFIX_OPCODE))
3882 /* Any other comma loses. */
3885 as_bad (_("invalid character %s in mnemonic"),
3886 output_invalid (*l));
3890 /* Check if instruction is supported on specified architecture. */
3892 for (t = current_templates->start; t < current_templates->end; ++t)
3894 supported |= cpu_flags_match (t);
3895 if (supported == CPU_FLAGS_PERFECT_MATCH)
3899 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3901 as_bad (flag_code == CODE_64BIT
3902 ? _("`%s' is not supported in 64-bit mode")
3903 : _("`%s' is only supported in 64-bit mode"),
3904 current_templates->start->name);
3907 if (supported != CPU_FLAGS_PERFECT_MATCH)
3909 as_bad (_("`%s' is not supported on `%s%s'"),
3910 current_templates->start->name,
3911 cpu_arch_name ? cpu_arch_name : default_arch,
3912 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3917 if (!cpu_arch_flags.bitfield.cpui386
3918 && (flag_code != CODE_16BIT))
3920 as_warn (_("use .code16 to ensure correct addressing mode"));
3927 parse_operands (char *l, const char *mnemonic)
3931 /* 1 if operand is pending after ','. */
3932 unsigned int expecting_operand = 0;
3934 /* Non-zero if operand parens not balanced. */
3935 unsigned int paren_not_balanced;
3937 while (*l != END_OF_INSN)
3939 /* Skip optional white space before operand. */
3940 if (is_space_char (*l))
3942 if (!is_operand_char (*l) && *l != END_OF_INSN)
3944 as_bad (_("invalid character %s before operand %d"),
3945 output_invalid (*l),
3949 token_start = l; /* after white space */
3950 paren_not_balanced = 0;
3951 while (paren_not_balanced || *l != ',')
3953 if (*l == END_OF_INSN)
3955 if (paren_not_balanced)
3958 as_bad (_("unbalanced parenthesis in operand %d."),
3961 as_bad (_("unbalanced brackets in operand %d."),
3966 break; /* we are done */
3968 else if (!is_operand_char (*l) && !is_space_char (*l))
3970 as_bad (_("invalid character %s in operand %d"),
3971 output_invalid (*l),
3978 ++paren_not_balanced;
3980 --paren_not_balanced;
3985 ++paren_not_balanced;
3987 --paren_not_balanced;
3991 if (l != token_start)
3992 { /* Yes, we've read in another operand. */
3993 unsigned int operand_ok;
3994 this_operand = i.operands++;
3995 i.types[this_operand].bitfield.unspecified = 1;
3996 if (i.operands > MAX_OPERANDS)
3998 as_bad (_("spurious operands; (%d operands/instruction max)"),
4002 /* Now parse operand adding info to 'i' as we go along. */
4003 END_STRING_AND_SAVE (l);
4007 i386_intel_operand (token_start,
4008 intel_float_operand (mnemonic));
4010 operand_ok = i386_att_operand (token_start);
4012 RESTORE_END_STRING (l);
4018 if (expecting_operand)
4020 expecting_operand_after_comma:
4021 as_bad (_("expecting operand after ','; got nothing"));
4026 as_bad (_("expecting operand before ','; got nothing"));
4031 /* Now *l must be either ',' or END_OF_INSN. */
4034 if (*++l == END_OF_INSN)
4036 /* Just skip it, if it's \n complain. */
4037 goto expecting_operand_after_comma;
4039 expecting_operand = 1;
4046 swap_2_operands (int xchg1, int xchg2)
4048 union i386_op temp_op;
4049 i386_operand_type temp_type;
4050 enum bfd_reloc_code_real temp_reloc;
4052 temp_type = i.types[xchg2];
4053 i.types[xchg2] = i.types[xchg1];
4054 i.types[xchg1] = temp_type;
4055 temp_op = i.op[xchg2];
4056 i.op[xchg2] = i.op[xchg1];
4057 i.op[xchg1] = temp_op;
4058 temp_reloc = i.reloc[xchg2];
4059 i.reloc[xchg2] = i.reloc[xchg1];
4060 i.reloc[xchg1] = temp_reloc;
4064 if (i.mask->operand == xchg1)
4065 i.mask->operand = xchg2;
4066 else if (i.mask->operand == xchg2)
4067 i.mask->operand = xchg1;
4071 if (i.broadcast->operand == xchg1)
4072 i.broadcast->operand = xchg2;
4073 else if (i.broadcast->operand == xchg2)
4074 i.broadcast->operand = xchg1;
4078 if (i.rounding->operand == xchg1)
4079 i.rounding->operand = xchg2;
4080 else if (i.rounding->operand == xchg2)
4081 i.rounding->operand = xchg1;
4086 swap_operands (void)
4092 swap_2_operands (1, i.operands - 2);
4095 swap_2_operands (0, i.operands - 1);
4101 if (i.mem_operands == 2)
4103 const seg_entry *temp_seg;
4104 temp_seg = i.seg[0];
4105 i.seg[0] = i.seg[1];
4106 i.seg[1] = temp_seg;
4110 /* Try to ensure constant immediates are represented in the smallest
4115 char guess_suffix = 0;
4119 guess_suffix = i.suffix;
4120 else if (i.reg_operands)
4122 /* Figure out a suffix from the last register operand specified.
4123 We can't do this properly yet, ie. excluding InOutPortReg,
4124 but the following works for instructions with immediates.
4125 In any case, we can't set i.suffix yet. */
4126 for (op = i.operands; --op >= 0;)
4127 if (i.types[op].bitfield.reg8)
4129 guess_suffix = BYTE_MNEM_SUFFIX;
4132 else if (i.types[op].bitfield.reg16)
4134 guess_suffix = WORD_MNEM_SUFFIX;
4137 else if (i.types[op].bitfield.reg32)
4139 guess_suffix = LONG_MNEM_SUFFIX;
4142 else if (i.types[op].bitfield.reg64)
4144 guess_suffix = QWORD_MNEM_SUFFIX;
4148 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
4149 guess_suffix = WORD_MNEM_SUFFIX;
4151 for (op = i.operands; --op >= 0;)
4152 if (operand_type_check (i.types[op], imm))
4154 switch (i.op[op].imms->X_op)
4157 /* If a suffix is given, this operand may be shortened. */
4158 switch (guess_suffix)
4160 case LONG_MNEM_SUFFIX:
4161 i.types[op].bitfield.imm32 = 1;
4162 i.types[op].bitfield.imm64 = 1;
4164 case WORD_MNEM_SUFFIX:
4165 i.types[op].bitfield.imm16 = 1;
4166 i.types[op].bitfield.imm32 = 1;
4167 i.types[op].bitfield.imm32s = 1;
4168 i.types[op].bitfield.imm64 = 1;
4170 case BYTE_MNEM_SUFFIX:
4171 i.types[op].bitfield.imm8 = 1;
4172 i.types[op].bitfield.imm8s = 1;
4173 i.types[op].bitfield.imm16 = 1;
4174 i.types[op].bitfield.imm32 = 1;
4175 i.types[op].bitfield.imm32s = 1;
4176 i.types[op].bitfield.imm64 = 1;
4180 /* If this operand is at most 16 bits, convert it
4181 to a signed 16 bit number before trying to see
4182 whether it will fit in an even smaller size.
4183 This allows a 16-bit operand such as $0xffe0 to
4184 be recognised as within Imm8S range. */
4185 if ((i.types[op].bitfield.imm16)
4186 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
4188 i.op[op].imms->X_add_number =
4189 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
4191 if ((i.types[op].bitfield.imm32)
4192 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
4195 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
4196 ^ ((offsetT) 1 << 31))
4197 - ((offsetT) 1 << 31));
4200 = operand_type_or (i.types[op],
4201 smallest_imm_type (i.op[op].imms->X_add_number));
4203 /* We must avoid matching of Imm32 templates when 64bit
4204 only immediate is available. */
4205 if (guess_suffix == QWORD_MNEM_SUFFIX)
4206 i.types[op].bitfield.imm32 = 0;
4213 /* Symbols and expressions. */
4215 /* Convert symbolic operand to proper sizes for matching, but don't
4216 prevent matching a set of insns that only supports sizes other
4217 than those matching the insn suffix. */
4219 i386_operand_type mask, allowed;
4220 const insn_template *t;
4222 operand_type_set (&mask, 0);
4223 operand_type_set (&allowed, 0);
4225 for (t = current_templates->start;
4226 t < current_templates->end;
4228 allowed = operand_type_or (allowed,
4229 t->operand_types[op]);
4230 switch (guess_suffix)
4232 case QWORD_MNEM_SUFFIX:
4233 mask.bitfield.imm64 = 1;
4234 mask.bitfield.imm32s = 1;
4236 case LONG_MNEM_SUFFIX:
4237 mask.bitfield.imm32 = 1;
4239 case WORD_MNEM_SUFFIX:
4240 mask.bitfield.imm16 = 1;
4242 case BYTE_MNEM_SUFFIX:
4243 mask.bitfield.imm8 = 1;
4248 allowed = operand_type_and (mask, allowed);
4249 if (!operand_type_all_zero (&allowed))
4250 i.types[op] = operand_type_and (i.types[op], mask);
4257 /* Try to use the smallest displacement type too. */
4259 optimize_disp (void)
4263 for (op = i.operands; --op >= 0;)
4264 if (operand_type_check (i.types[op], disp))
4266 if (i.op[op].disps->X_op == O_constant)
4268 offsetT op_disp = i.op[op].disps->X_add_number;
4270 if (i.types[op].bitfield.disp16
4271 && (op_disp & ~(offsetT) 0xffff) == 0)
4273 /* If this operand is at most 16 bits, convert
4274 to a signed 16 bit number and don't use 64bit
4276 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
4277 i.types[op].bitfield.disp64 = 0;
4279 if (i.types[op].bitfield.disp32
4280 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
4282 /* If this operand is at most 32 bits, convert
4283 to a signed 32 bit number and don't use 64bit
4285 op_disp &= (((offsetT) 2 << 31) - 1);
4286 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
4287 i.types[op].bitfield.disp64 = 0;
4289 if (!op_disp && i.types[op].bitfield.baseindex)
4291 i.types[op].bitfield.disp8 = 0;
4292 i.types[op].bitfield.disp16 = 0;
4293 i.types[op].bitfield.disp32 = 0;
4294 i.types[op].bitfield.disp32s = 0;
4295 i.types[op].bitfield.disp64 = 0;
4299 else if (flag_code == CODE_64BIT)
4301 if (fits_in_signed_long (op_disp))
4303 i.types[op].bitfield.disp64 = 0;
4304 i.types[op].bitfield.disp32s = 1;
4306 if (i.prefix[ADDR_PREFIX]
4307 && fits_in_unsigned_long (op_disp))
4308 i.types[op].bitfield.disp32 = 1;
4310 if ((i.types[op].bitfield.disp32
4311 || i.types[op].bitfield.disp32s
4312 || i.types[op].bitfield.disp16)
4313 && fits_in_signed_byte (op_disp))
4314 i.types[op].bitfield.disp8 = 1;
4316 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
4317 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
4319 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
4320 i.op[op].disps, 0, i.reloc[op]);
4321 i.types[op].bitfield.disp8 = 0;
4322 i.types[op].bitfield.disp16 = 0;
4323 i.types[op].bitfield.disp32 = 0;
4324 i.types[op].bitfield.disp32s = 0;
4325 i.types[op].bitfield.disp64 = 0;
4328 /* We only support 64bit displacement on constants. */
4329 i.types[op].bitfield.disp64 = 0;
4333 /* Check if operands are valid for the instruction. */
4336 check_VecOperands (const insn_template *t)
4340 /* Without VSIB byte, we can't have a vector register for index. */
4341 if (!t->opcode_modifier.vecsib
4343 && (i.index_reg->reg_type.bitfield.regxmm
4344 || i.index_reg->reg_type.bitfield.regymm
4345 || i.index_reg->reg_type.bitfield.regzmm))
4347 i.error = unsupported_vector_index_register;
4351 /* Check if default mask is allowed. */
4352 if (t->opcode_modifier.nodefmask
4353 && (!i.mask || i.mask->mask->reg_num == 0))
4355 i.error = no_default_mask;
4359 /* For VSIB byte, we need a vector register for index, and all vector
4360 registers must be distinct. */
4361 if (t->opcode_modifier.vecsib)
4364 || !((t->opcode_modifier.vecsib == VecSIB128
4365 && i.index_reg->reg_type.bitfield.regxmm)
4366 || (t->opcode_modifier.vecsib == VecSIB256
4367 && i.index_reg->reg_type.bitfield.regymm)
4368 || (t->opcode_modifier.vecsib == VecSIB512
4369 && i.index_reg->reg_type.bitfield.regzmm)))
4371 i.error = invalid_vsib_address;
4375 gas_assert (i.reg_operands == 2 || i.mask);
4376 if (i.reg_operands == 2 && !i.mask)
4378 gas_assert (i.types[0].bitfield.regxmm
4379 || i.types[0].bitfield.regymm
4380 || i.types[0].bitfield.regzmm);
4381 gas_assert (i.types[2].bitfield.regxmm
4382 || i.types[2].bitfield.regymm
4383 || i.types[2].bitfield.regzmm);
4384 if (operand_check == check_none)
4386 if (register_number (i.op[0].regs)
4387 != register_number (i.index_reg)
4388 && register_number (i.op[2].regs)
4389 != register_number (i.index_reg)
4390 && register_number (i.op[0].regs)
4391 != register_number (i.op[2].regs))
4393 if (operand_check == check_error)
4395 i.error = invalid_vector_register_set;
4398 as_warn (_("mask, index, and destination registers should be distinct"));
4402 /* Check if broadcast is supported by the instruction and is applied
4403 to the memory operand. */
4406 int broadcasted_opnd_size;
4408 /* Check if specified broadcast is supported in this instruction,
4409 and it's applied to memory operand of DWORD or QWORD type,
4410 depending on VecESize. */
4411 if (i.broadcast->type != t->opcode_modifier.broadcast
4412 || !i.types[i.broadcast->operand].bitfield.mem
4413 || (t->opcode_modifier.vecesize == 0
4414 && !i.types[i.broadcast->operand].bitfield.dword
4415 && !i.types[i.broadcast->operand].bitfield.unspecified)
4416 || (t->opcode_modifier.vecesize == 1
4417 && !i.types[i.broadcast->operand].bitfield.qword
4418 && !i.types[i.broadcast->operand].bitfield.unspecified))
4421 broadcasted_opnd_size = t->opcode_modifier.vecesize ? 64 : 32;
4422 if (i.broadcast->type == BROADCAST_1TO16)
4423 broadcasted_opnd_size <<= 4; /* Broadcast 1to16. */
4424 else if (i.broadcast->type == BROADCAST_1TO8)
4425 broadcasted_opnd_size <<= 3; /* Broadcast 1to8. */
4429 if ((broadcasted_opnd_size == 256
4430 && !t->operand_types[i.broadcast->operand].bitfield.ymmword)
4431 || (broadcasted_opnd_size == 512
4432 && !t->operand_types[i.broadcast->operand].bitfield.zmmword))
4435 i.error = unsupported_broadcast;
4439 /* If broadcast is supported in this instruction, we need to check if
4440 operand of one-element size isn't specified without broadcast. */
4441 else if (t->opcode_modifier.broadcast && i.mem_operands)
4443 /* Find memory operand. */
4444 for (op = 0; op < i.operands; op++)
4445 if (operand_type_check (i.types[op], anymem))
4447 gas_assert (op < i.operands);
4448 /* Check size of the memory operand. */
4449 if ((t->opcode_modifier.vecesize == 0
4450 && i.types[op].bitfield.dword)
4451 || (t->opcode_modifier.vecesize == 1
4452 && i.types[op].bitfield.qword))
4454 i.error = broadcast_needed;
4459 /* Check if requested masking is supported. */
4461 && (!t->opcode_modifier.masking
4463 && t->opcode_modifier.masking == MERGING_MASKING)))
4465 i.error = unsupported_masking;
4469 /* Check if masking is applied to dest operand. */
4470 if (i.mask && (i.mask->operand != (int) (i.operands - 1)))
4472 i.error = mask_not_on_destination;
4479 if ((i.rounding->type != saeonly
4480 && !t->opcode_modifier.staticrounding)
4481 || (i.rounding->type == saeonly
4482 && (t->opcode_modifier.staticrounding
4483 || !t->opcode_modifier.sae)))
4485 i.error = unsupported_rc_sae;
4488 /* If the instruction has several immediate operands and one of
4489 them is rounding, the rounding operand should be the last
4490 immediate operand. */
4491 if (i.imm_operands > 1
4492 && i.rounding->operand != (int) (i.imm_operands - 1))
4494 i.error = rc_sae_operand_not_last_imm;
4499 /* Check vector Disp8 operand. */
4500 if (t->opcode_modifier.disp8memshift)
4503 i.memshift = t->opcode_modifier.vecesize ? 3 : 2;
4505 i.memshift = t->opcode_modifier.disp8memshift;
4507 for (op = 0; op < i.operands; op++)
4508 if (operand_type_check (i.types[op], disp)
4509 && i.op[op].disps->X_op == O_constant)
4511 offsetT value = i.op[op].disps->X_add_number;
4512 int vec_disp8_ok = fits_in_vec_disp8 (value);
4513 if (t->operand_types [op].bitfield.vec_disp8)
4516 i.types[op].bitfield.vec_disp8 = 1;
4519 /* Vector insn can only have Vec_Disp8/Disp32 in
4520 32/64bit modes, and Vec_Disp8/Disp16 in 16bit
4522 i.types[op].bitfield.disp8 = 0;
4523 if (flag_code != CODE_16BIT)
4524 i.types[op].bitfield.disp16 = 0;
4527 else if (flag_code != CODE_16BIT)
4529 /* One form of this instruction supports vector Disp8.
4530 Try vector Disp8 if we need to use Disp32. */
4531 if (vec_disp8_ok && !fits_in_signed_byte (value))
4533 i.error = try_vector_disp8;
4545 /* Check if operands are valid for the instruction. Update VEX
4549 VEX_check_operands (const insn_template *t)
4551 /* VREX is only valid with EVEX prefix. */
4552 if (i.need_vrex && !t->opcode_modifier.evex)
4554 i.error = invalid_register_operand;
4558 if (!t->opcode_modifier.vex)
4561 /* Only check VEX_Imm4, which must be the first operand. */
4562 if (t->operand_types[0].bitfield.vec_imm4)
4564 if (i.op[0].imms->X_op != O_constant
4565 || !fits_in_imm4 (i.op[0].imms->X_add_number))
4571 /* Turn off Imm8 so that update_imm won't complain. */
4572 i.types[0] = vec_imm4;
4578 static const insn_template *
4579 match_template (void)
4581 /* Points to template once we've found it. */
4582 const insn_template *t;
4583 i386_operand_type overlap0, overlap1, overlap2, overlap3;
4584 i386_operand_type overlap4;
4585 unsigned int found_reverse_match;
4586 i386_opcode_modifier suffix_check;
4587 i386_operand_type operand_types [MAX_OPERANDS];
4588 int addr_prefix_disp;
4590 unsigned int found_cpu_match;
4591 unsigned int check_register;
4592 enum i386_error specific_error = 0;
4594 #if MAX_OPERANDS != 5
4595 # error "MAX_OPERANDS must be 5."
4598 found_reverse_match = 0;
4599 addr_prefix_disp = -1;
4601 memset (&suffix_check, 0, sizeof (suffix_check));
4602 if (i.suffix == BYTE_MNEM_SUFFIX)
4603 suffix_check.no_bsuf = 1;
4604 else if (i.suffix == WORD_MNEM_SUFFIX)
4605 suffix_check.no_wsuf = 1;
4606 else if (i.suffix == SHORT_MNEM_SUFFIX)
4607 suffix_check.no_ssuf = 1;
4608 else if (i.suffix == LONG_MNEM_SUFFIX)
4609 suffix_check.no_lsuf = 1;
4610 else if (i.suffix == QWORD_MNEM_SUFFIX)
4611 suffix_check.no_qsuf = 1;
4612 else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
4613 suffix_check.no_ldsuf = 1;
4615 /* Must have right number of operands. */
4616 i.error = number_of_operands_mismatch;
4618 for (t = current_templates->start; t < current_templates->end; t++)
4620 addr_prefix_disp = -1;
4622 if (i.operands != t->operands)
4625 /* Check processor support. */
4626 i.error = unsupported;
4627 found_cpu_match = (cpu_flags_match (t)
4628 == CPU_FLAGS_PERFECT_MATCH);
4629 if (!found_cpu_match)
4632 /* Check old gcc support. */
4633 i.error = old_gcc_only;
4634 if (!old_gcc && t->opcode_modifier.oldgcc)
4637 /* Check AT&T mnemonic. */
4638 i.error = unsupported_with_intel_mnemonic;
4639 if (intel_mnemonic && t->opcode_modifier.attmnemonic)
4642 /* Check AT&T/Intel syntax. */
4643 i.error = unsupported_syntax;
4644 if ((intel_syntax && t->opcode_modifier.attsyntax)
4645 || (!intel_syntax && t->opcode_modifier.intelsyntax))
4648 /* Check the suffix, except for some instructions in intel mode. */
4649 i.error = invalid_instruction_suffix;
4650 if ((!intel_syntax || !t->opcode_modifier.ignoresize)
4651 && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
4652 || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
4653 || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
4654 || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
4655 || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
4656 || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
4659 if (!operand_size_match (t))
4662 for (j = 0; j < MAX_OPERANDS; j++)
4663 operand_types[j] = t->operand_types[j];
4665 /* In general, don't allow 64-bit operands in 32-bit mode. */
4666 if (i.suffix == QWORD_MNEM_SUFFIX
4667 && flag_code != CODE_64BIT
4669 ? (!t->opcode_modifier.ignoresize
4670 && !intel_float_operand (t->name))
4671 : intel_float_operand (t->name) != 2)
4672 && ((!operand_types[0].bitfield.regmmx
4673 && !operand_types[0].bitfield.regxmm
4674 && !operand_types[0].bitfield.regymm
4675 && !operand_types[0].bitfield.regzmm)
4676 || (!operand_types[t->operands > 1].bitfield.regmmx
4677 && !!operand_types[t->operands > 1].bitfield.regxmm
4678 && !!operand_types[t->operands > 1].bitfield.regymm
4679 && !!operand_types[t->operands > 1].bitfield.regzmm))
4680 && (t->base_opcode != 0x0fc7
4681 || t->extension_opcode != 1 /* cmpxchg8b */))
4684 /* In general, don't allow 32-bit operands on pre-386. */
4685 else if (i.suffix == LONG_MNEM_SUFFIX
4686 && !cpu_arch_flags.bitfield.cpui386
4688 ? (!t->opcode_modifier.ignoresize
4689 && !intel_float_operand (t->name))
4690 : intel_float_operand (t->name) != 2)
4691 && ((!operand_types[0].bitfield.regmmx
4692 && !operand_types[0].bitfield.regxmm)
4693 || (!operand_types[t->operands > 1].bitfield.regmmx
4694 && !!operand_types[t->operands > 1].bitfield.regxmm)))
4697 /* Do not verify operands when there are none. */
4701 /* We've found a match; break out of loop. */
4705 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
4706 into Disp32/Disp16/Disp32 operand. */
4707 if (i.prefix[ADDR_PREFIX] != 0)
4709 /* There should be only one Disp operand. */
4713 for (j = 0; j < MAX_OPERANDS; j++)
4715 if (operand_types[j].bitfield.disp16)
4717 addr_prefix_disp = j;
4718 operand_types[j].bitfield.disp32 = 1;
4719 operand_types[j].bitfield.disp16 = 0;
4725 for (j = 0; j < MAX_OPERANDS; j++)
4727 if (operand_types[j].bitfield.disp32)
4729 addr_prefix_disp = j;
4730 operand_types[j].bitfield.disp32 = 0;
4731 operand_types[j].bitfield.disp16 = 1;
4737 for (j = 0; j < MAX_OPERANDS; j++)
4739 if (operand_types[j].bitfield.disp64)
4741 addr_prefix_disp = j;
4742 operand_types[j].bitfield.disp64 = 0;
4743 operand_types[j].bitfield.disp32 = 1;
4751 /* We check register size if needed. */
4752 check_register = t->opcode_modifier.checkregsize;
4753 overlap0 = operand_type_and (i.types[0], operand_types[0]);
4754 switch (t->operands)
4757 if (!operand_type_match (overlap0, i.types[0]))
4761 /* xchg %eax, %eax is a special case. It is an aliase for nop
4762 only in 32bit mode and we can use opcode 0x90. In 64bit
4763 mode, we can't use 0x90 for xchg %eax, %eax since it should
4764 zero-extend %eax to %rax. */
4765 if (flag_code == CODE_64BIT
4766 && t->base_opcode == 0x90
4767 && operand_type_equal (&i.types [0], &acc32)
4768 && operand_type_equal (&i.types [1], &acc32))
4772 /* If we swap operand in encoding, we either match
4773 the next one or reverse direction of operands. */
4774 if (t->opcode_modifier.s)
4776 else if (t->opcode_modifier.d)
4781 /* If we swap operand in encoding, we match the next one. */
4782 if (i.swap_operand && t->opcode_modifier.s)
4786 overlap1 = operand_type_and (i.types[1], operand_types[1]);
4787 if (!operand_type_match (overlap0, i.types[0])
4788 || !operand_type_match (overlap1, i.types[1])
4790 && !operand_type_register_match (overlap0, i.types[0],
4792 overlap1, i.types[1],
4795 /* Check if other direction is valid ... */
4796 if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
4800 /* Try reversing direction of operands. */
4801 overlap0 = operand_type_and (i.types[0], operand_types[1]);
4802 overlap1 = operand_type_and (i.types[1], operand_types[0]);
4803 if (!operand_type_match (overlap0, i.types[0])
4804 || !operand_type_match (overlap1, i.types[1])
4806 && !operand_type_register_match (overlap0,
4813 /* Does not match either direction. */
4816 /* found_reverse_match holds which of D or FloatDR
4818 if (t->opcode_modifier.d)
4819 found_reverse_match = Opcode_D;
4820 else if (t->opcode_modifier.floatd)
4821 found_reverse_match = Opcode_FloatD;
4823 found_reverse_match = 0;
4824 if (t->opcode_modifier.floatr)
4825 found_reverse_match |= Opcode_FloatR;
4829 /* Found a forward 2 operand match here. */
4830 switch (t->operands)
4833 overlap4 = operand_type_and (i.types[4],
4836 overlap3 = operand_type_and (i.types[3],
4839 overlap2 = operand_type_and (i.types[2],
4844 switch (t->operands)
4847 if (!operand_type_match (overlap4, i.types[4])
4848 || !operand_type_register_match (overlap3,
4856 if (!operand_type_match (overlap3, i.types[3])
4858 && !operand_type_register_match (overlap2,
4866 /* Here we make use of the fact that there are no
4867 reverse match 3 operand instructions, and all 3
4868 operand instructions only need to be checked for
4869 register consistency between operands 2 and 3. */
4870 if (!operand_type_match (overlap2, i.types[2])
4872 && !operand_type_register_match (overlap1,
4882 /* Found either forward/reverse 2, 3 or 4 operand match here:
4883 slip through to break. */
4885 if (!found_cpu_match)
4887 found_reverse_match = 0;
4891 /* Check if vector and VEX operands are valid. */
4892 if (check_VecOperands (t) || VEX_check_operands (t))
4894 specific_error = i.error;
4898 /* We've found a match; break out of loop. */
4902 if (t == current_templates->end)
4904 /* We found no match. */
4905 const char *err_msg;
4906 switch (specific_error ? specific_error : i.error)
4910 case operand_size_mismatch:
4911 err_msg = _("operand size mismatch");
4913 case operand_type_mismatch:
4914 err_msg = _("operand type mismatch");
4916 case register_type_mismatch:
4917 err_msg = _("register type mismatch");
4919 case number_of_operands_mismatch:
4920 err_msg = _("number of operands mismatch");
4922 case invalid_instruction_suffix:
4923 err_msg = _("invalid instruction suffix");
4926 err_msg = _("constant doesn't fit in 4 bits");
4929 err_msg = _("only supported with old gcc");
4931 case unsupported_with_intel_mnemonic:
4932 err_msg = _("unsupported with Intel mnemonic");
4934 case unsupported_syntax:
4935 err_msg = _("unsupported syntax");
4938 as_bad (_("unsupported instruction `%s'"),
4939 current_templates->start->name);
4941 case invalid_vsib_address:
4942 err_msg = _("invalid VSIB address");
4944 case invalid_vector_register_set:
4945 err_msg = _("mask, index, and destination registers must be distinct");
4947 case unsupported_vector_index_register:
4948 err_msg = _("unsupported vector index register");
4950 case unsupported_broadcast:
4951 err_msg = _("unsupported broadcast");
4953 case broadcast_not_on_src_operand:
4954 err_msg = _("broadcast not on source memory operand");
4956 case broadcast_needed:
4957 err_msg = _("broadcast is needed for operand of such type");
4959 case unsupported_masking:
4960 err_msg = _("unsupported masking");
4962 case mask_not_on_destination:
4963 err_msg = _("mask not on destination operand");
4965 case no_default_mask:
4966 err_msg = _("default mask isn't allowed");
4968 case unsupported_rc_sae:
4969 err_msg = _("unsupported static rounding/sae");
4971 case rc_sae_operand_not_last_imm:
4973 err_msg = _("RC/SAE operand must precede immediate operands");
4975 err_msg = _("RC/SAE operand must follow immediate operands");
4977 case invalid_register_operand:
4978 err_msg = _("invalid register operand");
4981 as_bad (_("%s for `%s'"), err_msg,
4982 current_templates->start->name);
4986 if (!quiet_warnings)
4989 && (i.types[0].bitfield.jumpabsolute
4990 != operand_types[0].bitfield.jumpabsolute))
4992 as_warn (_("indirect %s without `*'"), t->name);
4995 if (t->opcode_modifier.isprefix
4996 && t->opcode_modifier.ignoresize)
4998 /* Warn them that a data or address size prefix doesn't
4999 affect assembly of the next line of code. */
5000 as_warn (_("stand-alone `%s' prefix"), t->name);
5004 /* Copy the template we found. */
5007 if (addr_prefix_disp != -1)
5008 i.tm.operand_types[addr_prefix_disp]
5009 = operand_types[addr_prefix_disp];
5011 if (found_reverse_match)
5013 /* If we found a reverse match we must alter the opcode
5014 direction bit. found_reverse_match holds bits to change
5015 (different for int & float insns). */
5017 i.tm.base_opcode ^= found_reverse_match;
5019 i.tm.operand_types[0] = operand_types[1];
5020 i.tm.operand_types[1] = operand_types[0];
5029 int mem_op = operand_type_check (i.types[0], anymem) ? 0 : 1;
5030 if (i.tm.operand_types[mem_op].bitfield.esseg)
5032 if (i.seg[0] != NULL && i.seg[0] != &es)
5034 as_bad (_("`%s' operand %d must use `%ses' segment"),
5040 /* There's only ever one segment override allowed per instruction.
5041 This instruction possibly has a legal segment override on the
5042 second operand, so copy the segment to where non-string
5043 instructions store it, allowing common code. */
5044 i.seg[0] = i.seg[1];
5046 else if (i.tm.operand_types[mem_op + 1].bitfield.esseg)
5048 if (i.seg[1] != NULL && i.seg[1] != &es)
5050 as_bad (_("`%s' operand %d must use `%ses' segment"),
5061 process_suffix (void)
5063 /* If matched instruction specifies an explicit instruction mnemonic
5065 if (i.tm.opcode_modifier.size16)
5066 i.suffix = WORD_MNEM_SUFFIX;
5067 else if (i.tm.opcode_modifier.size32)
5068 i.suffix = LONG_MNEM_SUFFIX;
5069 else if (i.tm.opcode_modifier.size64)
5070 i.suffix = QWORD_MNEM_SUFFIX;
5071 else if (i.reg_operands)
5073 /* If there's no instruction mnemonic suffix we try to invent one
5074 based on register operands. */
5077 /* We take i.suffix from the last register operand specified,
5078 Destination register type is more significant than source
5079 register type. crc32 in SSE4.2 prefers source register
5081 if (i.tm.base_opcode == 0xf20f38f1)
5083 if (i.types[0].bitfield.reg16)
5084 i.suffix = WORD_MNEM_SUFFIX;
5085 else if (i.types[0].bitfield.reg32)
5086 i.suffix = LONG_MNEM_SUFFIX;
5087 else if (i.types[0].bitfield.reg64)
5088 i.suffix = QWORD_MNEM_SUFFIX;
5090 else if (i.tm.base_opcode == 0xf20f38f0)
5092 if (i.types[0].bitfield.reg8)
5093 i.suffix = BYTE_MNEM_SUFFIX;
5100 if (i.tm.base_opcode == 0xf20f38f1
5101 || i.tm.base_opcode == 0xf20f38f0)
5103 /* We have to know the operand size for crc32. */
5104 as_bad (_("ambiguous memory operand size for `%s`"),
5109 for (op = i.operands; --op >= 0;)
5110 if (!i.tm.operand_types[op].bitfield.inoutportreg)
5112 if (i.types[op].bitfield.reg8)
5114 i.suffix = BYTE_MNEM_SUFFIX;
5117 else if (i.types[op].bitfield.reg16)
5119 i.suffix = WORD_MNEM_SUFFIX;
5122 else if (i.types[op].bitfield.reg32)
5124 i.suffix = LONG_MNEM_SUFFIX;
5127 else if (i.types[op].bitfield.reg64)
5129 i.suffix = QWORD_MNEM_SUFFIX;
5135 else if (i.suffix == BYTE_MNEM_SUFFIX)
5138 && i.tm.opcode_modifier.ignoresize
5139 && i.tm.opcode_modifier.no_bsuf)
5141 else if (!check_byte_reg ())
5144 else if (i.suffix == LONG_MNEM_SUFFIX)
5147 && i.tm.opcode_modifier.ignoresize
5148 && i.tm.opcode_modifier.no_lsuf)
5150 else if (!check_long_reg ())
5153 else if (i.suffix == QWORD_MNEM_SUFFIX)
5156 && i.tm.opcode_modifier.ignoresize
5157 && i.tm.opcode_modifier.no_qsuf)
5159 else if (!check_qword_reg ())
5162 else if (i.suffix == WORD_MNEM_SUFFIX)
5165 && i.tm.opcode_modifier.ignoresize
5166 && i.tm.opcode_modifier.no_wsuf)
5168 else if (!check_word_reg ())
5171 else if (i.suffix == XMMWORD_MNEM_SUFFIX
5172 || i.suffix == YMMWORD_MNEM_SUFFIX
5173 || i.suffix == ZMMWORD_MNEM_SUFFIX)
5175 /* Skip if the instruction has x/y/z suffix. match_template
5176 should check if it is a valid suffix. */
5178 else if (intel_syntax && i.tm.opcode_modifier.ignoresize)
5179 /* Do nothing if the instruction is going to ignore the prefix. */
5184 else if (i.tm.opcode_modifier.defaultsize
5186 /* exclude fldenv/frstor/fsave/fstenv */
5187 && i.tm.opcode_modifier.no_ssuf)
5189 i.suffix = stackop_size;
5191 else if (intel_syntax
5193 && (i.tm.operand_types[0].bitfield.jumpabsolute
5194 || i.tm.opcode_modifier.jumpbyte
5195 || i.tm.opcode_modifier.jumpintersegment
5196 || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */
5197 && i.tm.extension_opcode <= 3)))
5202 if (!i.tm.opcode_modifier.no_qsuf)
5204 i.suffix = QWORD_MNEM_SUFFIX;
5208 if (!i.tm.opcode_modifier.no_lsuf)
5209 i.suffix = LONG_MNEM_SUFFIX;
5212 if (!i.tm.opcode_modifier.no_wsuf)
5213 i.suffix = WORD_MNEM_SUFFIX;
5222 if (i.tm.opcode_modifier.w)
5224 as_bad (_("no instruction mnemonic suffix given and "
5225 "no register operands; can't size instruction"));
5231 unsigned int suffixes;
5233 suffixes = !i.tm.opcode_modifier.no_bsuf;
5234 if (!i.tm.opcode_modifier.no_wsuf)
5236 if (!i.tm.opcode_modifier.no_lsuf)
5238 if (!i.tm.opcode_modifier.no_ldsuf)
5240 if (!i.tm.opcode_modifier.no_ssuf)
5242 if (!i.tm.opcode_modifier.no_qsuf)
5245 /* There are more than suffix matches. */
5246 if (i.tm.opcode_modifier.w
5247 || ((suffixes & (suffixes - 1))
5248 && !i.tm.opcode_modifier.defaultsize
5249 && !i.tm.opcode_modifier.ignoresize))
5251 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
5257 /* Change the opcode based on the operand size given by i.suffix;
5258 We don't need to change things for byte insns. */
5261 && i.suffix != BYTE_MNEM_SUFFIX
5262 && i.suffix != XMMWORD_MNEM_SUFFIX
5263 && i.suffix != YMMWORD_MNEM_SUFFIX
5264 && i.suffix != ZMMWORD_MNEM_SUFFIX)
5266 /* It's not a byte, select word/dword operation. */
5267 if (i.tm.opcode_modifier.w)
5269 if (i.tm.opcode_modifier.shortform)
5270 i.tm.base_opcode |= 8;
5272 i.tm.base_opcode |= 1;
5275 /* Now select between word & dword operations via the operand
5276 size prefix, except for instructions that will ignore this
5278 if (i.tm.opcode_modifier.addrprefixop0)
5280 /* The address size override prefix changes the size of the
5282 if ((flag_code == CODE_32BIT
5283 && i.op->regs[0].reg_type.bitfield.reg16)
5284 || (flag_code != CODE_32BIT
5285 && i.op->regs[0].reg_type.bitfield.reg32))
5286 if (!add_prefix (ADDR_PREFIX_OPCODE))
5289 else if (i.suffix != QWORD_MNEM_SUFFIX
5290 && i.suffix != LONG_DOUBLE_MNEM_SUFFIX
5291 && !i.tm.opcode_modifier.ignoresize
5292 && !i.tm.opcode_modifier.floatmf
5293 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
5294 || (flag_code == CODE_64BIT
5295 && i.tm.opcode_modifier.jumpbyte)))
5297 unsigned int prefix = DATA_PREFIX_OPCODE;
5299 if (i.tm.opcode_modifier.jumpbyte) /* jcxz, loop */
5300 prefix = ADDR_PREFIX_OPCODE;
5302 if (!add_prefix (prefix))
5306 /* Set mode64 for an operand. */
5307 if (i.suffix == QWORD_MNEM_SUFFIX
5308 && flag_code == CODE_64BIT
5309 && !i.tm.opcode_modifier.norex64)
5311 /* Special case for xchg %rax,%rax. It is NOP and doesn't
5312 need rex64. cmpxchg8b is also a special case. */
5313 if (! (i.operands == 2
5314 && i.tm.base_opcode == 0x90
5315 && i.tm.extension_opcode == None
5316 && operand_type_equal (&i.types [0], &acc64)
5317 && operand_type_equal (&i.types [1], &acc64))
5318 && ! (i.operands == 1
5319 && i.tm.base_opcode == 0xfc7
5320 && i.tm.extension_opcode == 1
5321 && !operand_type_check (i.types [0], reg)
5322 && operand_type_check (i.types [0], anymem)))
5326 /* Size floating point instruction. */
5327 if (i.suffix == LONG_MNEM_SUFFIX)
5328 if (i.tm.opcode_modifier.floatmf)
5329 i.tm.base_opcode ^= 4;
5336 check_byte_reg (void)
5340 for (op = i.operands; --op >= 0;)
5342 /* If this is an eight bit register, it's OK. If it's the 16 or
5343 32 bit version of an eight bit register, we will just use the
5344 low portion, and that's OK too. */
5345 if (i.types[op].bitfield.reg8)
5348 /* I/O port address operands are OK too. */
5349 if (i.tm.operand_types[op].bitfield.inoutportreg)
5352 /* crc32 doesn't generate this warning. */
5353 if (i.tm.base_opcode == 0xf20f38f0)
5356 if ((i.types[op].bitfield.reg16
5357 || i.types[op].bitfield.reg32
5358 || i.types[op].bitfield.reg64)
5359 && i.op[op].regs->reg_num < 4
5360 /* Prohibit these changes in 64bit mode, since the lowering
5361 would be more complicated. */
5362 && flag_code != CODE_64BIT)
5364 #if REGISTER_WARNINGS
5365 if (!quiet_warnings)
5366 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5368 (i.op[op].regs + (i.types[op].bitfield.reg16
5369 ? REGNAM_AL - REGNAM_AX
5370 : REGNAM_AL - REGNAM_EAX))->reg_name,
5372 i.op[op].regs->reg_name,
5377 /* Any other register is bad. */
5378 if (i.types[op].bitfield.reg16
5379 || i.types[op].bitfield.reg32
5380 || i.types[op].bitfield.reg64
5381 || i.types[op].bitfield.regmmx
5382 || i.types[op].bitfield.regxmm
5383 || i.types[op].bitfield.regymm
5384 || i.types[op].bitfield.regzmm
5385 || i.types[op].bitfield.sreg2
5386 || i.types[op].bitfield.sreg3
5387 || i.types[op].bitfield.control
5388 || i.types[op].bitfield.debug
5389 || i.types[op].bitfield.test
5390 || i.types[op].bitfield.floatreg
5391 || i.types[op].bitfield.floatacc)
5393 as_bad (_("`%s%s' not allowed with `%s%c'"),
5395 i.op[op].regs->reg_name,
5405 check_long_reg (void)
5409 for (op = i.operands; --op >= 0;)
5410 /* Reject eight bit registers, except where the template requires
5411 them. (eg. movzb) */
5412 if (i.types[op].bitfield.reg8
5413 && (i.tm.operand_types[op].bitfield.reg16
5414 || i.tm.operand_types[op].bitfield.reg32
5415 || i.tm.operand_types[op].bitfield.acc))
5417 as_bad (_("`%s%s' not allowed with `%s%c'"),
5419 i.op[op].regs->reg_name,
5424 /* Warn if the e prefix on a general reg is missing. */
5425 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5426 && i.types[op].bitfield.reg16
5427 && (i.tm.operand_types[op].bitfield.reg32
5428 || i.tm.operand_types[op].bitfield.acc))
5430 /* Prohibit these changes in the 64bit mode, since the
5431 lowering is more complicated. */
5432 if (flag_code == CODE_64BIT)
5434 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5435 register_prefix, i.op[op].regs->reg_name,
5439 #if REGISTER_WARNINGS
5440 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5442 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
5443 register_prefix, i.op[op].regs->reg_name, i.suffix);
5446 /* Warn if the r prefix on a general reg is present. */
5447 else if (i.types[op].bitfield.reg64
5448 && (i.tm.operand_types[op].bitfield.reg32
5449 || i.tm.operand_types[op].bitfield.acc))
5452 && i.tm.opcode_modifier.toqword
5453 && !i.types[0].bitfield.regxmm)
5455 /* Convert to QWORD. We want REX byte. */
5456 i.suffix = QWORD_MNEM_SUFFIX;
5460 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5461 register_prefix, i.op[op].regs->reg_name,
5470 check_qword_reg (void)
5474 for (op = i.operands; --op >= 0; )
5475 /* Reject eight bit registers, except where the template requires
5476 them. (eg. movzb) */
5477 if (i.types[op].bitfield.reg8
5478 && (i.tm.operand_types[op].bitfield.reg16
5479 || i.tm.operand_types[op].bitfield.reg32
5480 || i.tm.operand_types[op].bitfield.acc))
5482 as_bad (_("`%s%s' not allowed with `%s%c'"),
5484 i.op[op].regs->reg_name,
5489 /* Warn if the r prefix on a general reg is missing. */
5490 else if ((i.types[op].bitfield.reg16
5491 || i.types[op].bitfield.reg32)
5492 && (i.tm.operand_types[op].bitfield.reg32
5493 || i.tm.operand_types[op].bitfield.acc))
5495 /* Prohibit these changes in the 64bit mode, since the
5496 lowering is more complicated. */
5498 && i.tm.opcode_modifier.todword
5499 && !i.types[0].bitfield.regxmm)
5501 /* Convert to DWORD. We don't want REX byte. */
5502 i.suffix = LONG_MNEM_SUFFIX;
5506 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5507 register_prefix, i.op[op].regs->reg_name,
5516 check_word_reg (void)
5519 for (op = i.operands; --op >= 0;)
5520 /* Reject eight bit registers, except where the template requires
5521 them. (eg. movzb) */
5522 if (i.types[op].bitfield.reg8
5523 && (i.tm.operand_types[op].bitfield.reg16
5524 || i.tm.operand_types[op].bitfield.reg32
5525 || i.tm.operand_types[op].bitfield.acc))
5527 as_bad (_("`%s%s' not allowed with `%s%c'"),
5529 i.op[op].regs->reg_name,
5534 /* Warn if the e or r prefix on a general reg is present. */
5535 else if ((!quiet_warnings || flag_code == CODE_64BIT)
5536 && (i.types[op].bitfield.reg32
5537 || i.types[op].bitfield.reg64)
5538 && (i.tm.operand_types[op].bitfield.reg16
5539 || i.tm.operand_types[op].bitfield.acc))
5541 /* Prohibit these changes in the 64bit mode, since the
5542 lowering is more complicated. */
5543 if (flag_code == CODE_64BIT)
5545 as_bad (_("incorrect register `%s%s' used with `%c' suffix"),
5546 register_prefix, i.op[op].regs->reg_name,
5550 #if REGISTER_WARNINGS
5551 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
5553 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
5554 register_prefix, i.op[op].regs->reg_name, i.suffix);
5561 update_imm (unsigned int j)
5563 i386_operand_type overlap = i.types[j];
5564 if ((overlap.bitfield.imm8
5565 || overlap.bitfield.imm8s
5566 || overlap.bitfield.imm16
5567 || overlap.bitfield.imm32
5568 || overlap.bitfield.imm32s
5569 || overlap.bitfield.imm64)
5570 && !operand_type_equal (&overlap, &imm8)
5571 && !operand_type_equal (&overlap, &imm8s)
5572 && !operand_type_equal (&overlap, &imm16)
5573 && !operand_type_equal (&overlap, &imm32)
5574 && !operand_type_equal (&overlap, &imm32s)
5575 && !operand_type_equal (&overlap, &imm64))
5579 i386_operand_type temp;
5581 operand_type_set (&temp, 0);
5582 if (i.suffix == BYTE_MNEM_SUFFIX)
5584 temp.bitfield.imm8 = overlap.bitfield.imm8;
5585 temp.bitfield.imm8s = overlap.bitfield.imm8s;
5587 else if (i.suffix == WORD_MNEM_SUFFIX)
5588 temp.bitfield.imm16 = overlap.bitfield.imm16;
5589 else if (i.suffix == QWORD_MNEM_SUFFIX)
5591 temp.bitfield.imm64 = overlap.bitfield.imm64;
5592 temp.bitfield.imm32s = overlap.bitfield.imm32s;
5595 temp.bitfield.imm32 = overlap.bitfield.imm32;
5598 else if (operand_type_equal (&overlap, &imm16_32_32s)
5599 || operand_type_equal (&overlap, &imm16_32)
5600 || operand_type_equal (&overlap, &imm16_32s))
5602 if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
5607 if (!operand_type_equal (&overlap, &imm8)
5608 && !operand_type_equal (&overlap, &imm8s)
5609 && !operand_type_equal (&overlap, &imm16)
5610 && !operand_type_equal (&overlap, &imm32)
5611 && !operand_type_equal (&overlap, &imm32s)
5612 && !operand_type_equal (&overlap, &imm64))
5614 as_bad (_("no instruction mnemonic suffix given; "
5615 "can't determine immediate size"));
5619 i.types[j] = overlap;
5629 /* Update the first 2 immediate operands. */
5630 n = i.operands > 2 ? 2 : i.operands;
5633 for (j = 0; j < n; j++)
5634 if (update_imm (j) == 0)
5637 /* The 3rd operand can't be immediate operand. */
5638 gas_assert (operand_type_check (i.types[2], imm) == 0);
5645 bad_implicit_operand (int xmm)
5647 const char *ireg = xmm ? "xmm0" : "ymm0";
5650 as_bad (_("the last operand of `%s' must be `%s%s'"),
5651 i.tm.name, register_prefix, ireg);
5653 as_bad (_("the first operand of `%s' must be `%s%s'"),
5654 i.tm.name, register_prefix, ireg);
5659 process_operands (void)
5661 /* Default segment register this instruction will use for memory
5662 accesses. 0 means unknown. This is only for optimizing out
5663 unnecessary segment overrides. */
5664 const seg_entry *default_seg = 0;
5666 if (i.tm.opcode_modifier.sse2avx && i.tm.opcode_modifier.vexvvvv)
5668 unsigned int dupl = i.operands;
5669 unsigned int dest = dupl - 1;
5672 /* The destination must be an xmm register. */
5673 gas_assert (i.reg_operands
5674 && MAX_OPERANDS > dupl
5675 && operand_type_equal (&i.types[dest], ®xmm));
5677 if (i.tm.opcode_modifier.firstxmm0)
5679 /* The first operand is implicit and must be xmm0. */
5680 gas_assert (operand_type_equal (&i.types[0], ®xmm));
5681 if (register_number (i.op[0].regs) != 0)
5682 return bad_implicit_operand (1);
5684 if (i.tm.opcode_modifier.vexsources == VEX3SOURCES)
5686 /* Keep xmm0 for instructions with VEX prefix and 3
5692 /* We remove the first xmm0 and keep the number of
5693 operands unchanged, which in fact duplicates the
5695 for (j = 1; j < i.operands; j++)
5697 i.op[j - 1] = i.op[j];
5698 i.types[j - 1] = i.types[j];
5699 i.tm.operand_types[j - 1] = i.tm.operand_types[j];
5703 else if (i.tm.opcode_modifier.implicit1stxmm0)
5705 gas_assert ((MAX_OPERANDS - 1) > dupl
5706 && (i.tm.opcode_modifier.vexsources
5709 /* Add the implicit xmm0 for instructions with VEX prefix
5711 for (j = i.operands; j > 0; j--)
5713 i.op[j] = i.op[j - 1];
5714 i.types[j] = i.types[j - 1];
5715 i.tm.operand_types[j] = i.tm.operand_types[j - 1];
5718 = (const reg_entry *) hash_find (reg_hash, "xmm0");
5719 i.types[0] = regxmm;
5720 i.tm.operand_types[0] = regxmm;
5723 i.reg_operands += 2;
5728 i.op[dupl] = i.op[dest];
5729 i.types[dupl] = i.types[dest];
5730 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5739 i.op[dupl] = i.op[dest];
5740 i.types[dupl] = i.types[dest];
5741 i.tm.operand_types[dupl] = i.tm.operand_types[dest];
5744 if (i.tm.opcode_modifier.immext)
5747 else if (i.tm.opcode_modifier.firstxmm0)
5751 /* The first operand is implicit and must be xmm0/ymm0/zmm0. */
5752 gas_assert (i.reg_operands
5753 && (operand_type_equal (&i.types[0], ®xmm)
5754 || operand_type_equal (&i.types[0], ®ymm)
5755 || operand_type_equal (&i.types[0], ®zmm)));
5756 if (register_number (i.op[0].regs) != 0)
5757 return bad_implicit_operand (i.types[0].bitfield.regxmm);
5759 for (j = 1; j < i.operands; j++)
5761 i.op[j - 1] = i.op[j];
5762 i.types[j - 1] = i.types[j];
5764 /* We need to adjust fields in i.tm since they are used by
5765 build_modrm_byte. */
5766 i.tm.operand_types [j - 1] = i.tm.operand_types [j];
5773 else if (i.tm.opcode_modifier.regkludge)
5775 /* The imul $imm, %reg instruction is converted into
5776 imul $imm, %reg, %reg, and the clr %reg instruction
5777 is converted into xor %reg, %reg. */
5779 unsigned int first_reg_op;
5781 if (operand_type_check (i.types[0], reg))
5785 /* Pretend we saw the extra register operand. */
5786 gas_assert (i.reg_operands == 1
5787 && i.op[first_reg_op + 1].regs == 0);
5788 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
5789 i.types[first_reg_op + 1] = i.types[first_reg_op];
5794 if (i.tm.opcode_modifier.shortform)
5796 if (i.types[0].bitfield.sreg2
5797 || i.types[0].bitfield.sreg3)
5799 if (i.tm.base_opcode == POP_SEG_SHORT
5800 && i.op[0].regs->reg_num == 1)
5802 as_bad (_("you can't `pop %scs'"), register_prefix);
5805 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
5806 if ((i.op[0].regs->reg_flags & RegRex) != 0)
5811 /* The register or float register operand is in operand
5815 if (i.types[0].bitfield.floatreg
5816 || operand_type_check (i.types[0], reg))
5820 /* Register goes in low 3 bits of opcode. */
5821 i.tm.base_opcode |= i.op[op].regs->reg_num;
5822 if ((i.op[op].regs->reg_flags & RegRex) != 0)
5824 if (!quiet_warnings && i.tm.opcode_modifier.ugh)
5826 /* Warn about some common errors, but press on regardless.
5827 The first case can be generated by gcc (<= 2.8.1). */
5828 if (i.operands == 2)
5830 /* Reversed arguments on faddp, fsubp, etc. */
5831 as_warn (_("translating to `%s %s%s,%s%s'"), i.tm.name,
5832 register_prefix, i.op[!intel_syntax].regs->reg_name,
5833 register_prefix, i.op[intel_syntax].regs->reg_name);
5837 /* Extraneous `l' suffix on fp insn. */
5838 as_warn (_("translating to `%s %s%s'"), i.tm.name,
5839 register_prefix, i.op[0].regs->reg_name);
5844 else if (i.tm.opcode_modifier.modrm)
5846 /* The opcode is completed (modulo i.tm.extension_opcode which
5847 must be put into the modrm byte). Now, we make the modrm and
5848 index base bytes based on all the info we've collected. */
5850 default_seg = build_modrm_byte ();
5852 else if ((i.tm.base_opcode & ~0x3) == MOV_AX_DISP32)
5856 else if (i.tm.opcode_modifier.isstring)
5858 /* For the string instructions that allow a segment override
5859 on one of their operands, the default segment is ds. */
5863 if (i.tm.base_opcode == 0x8d /* lea */
5866 as_warn (_("segment override on `%s' is ineffectual"), i.tm.name);
5868 /* If a segment was explicitly specified, and the specified segment
5869 is not the default, use an opcode prefix to select it. If we
5870 never figured out what the default segment is, then default_seg
5871 will be zero at this point, and the specified segment prefix will
5873 if ((i.seg[0]) && (i.seg[0] != default_seg))
5875 if (!add_prefix (i.seg[0]->seg_prefix))
5881 static const seg_entry *
5882 build_modrm_byte (void)
5884 const seg_entry *default_seg = 0;
5885 unsigned int source, dest;
5888 /* The first operand of instructions with VEX prefix and 3 sources
5889 must be VEX_Imm4. */
5890 vex_3_sources = i.tm.opcode_modifier.vexsources == VEX3SOURCES;
5893 unsigned int nds, reg_slot;
5896 if (i.tm.opcode_modifier.veximmext
5897 && i.tm.opcode_modifier.immext)
5899 dest = i.operands - 2;
5900 gas_assert (dest == 3);
5903 dest = i.operands - 1;
5906 /* There are 2 kinds of instructions:
5907 1. 5 operands: 4 register operands or 3 register operands
5908 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5909 VexW0 or VexW1. The destination must be either XMM, YMM or
5911 2. 4 operands: 4 register operands or 3 register operands
5912 plus 1 memory operand, VexXDS, and VexImmExt */
5913 gas_assert ((i.reg_operands == 4
5914 || (i.reg_operands == 3 && i.mem_operands == 1))
5915 && i.tm.opcode_modifier.vexvvvv == VEXXDS
5916 && (i.tm.opcode_modifier.veximmext
5917 || (i.imm_operands == 1
5918 && i.types[0].bitfield.vec_imm4
5919 && (i.tm.opcode_modifier.vexw == VEXW0
5920 || i.tm.opcode_modifier.vexw == VEXW1)
5921 && (operand_type_equal (&i.tm.operand_types[dest], ®xmm)
5922 || operand_type_equal (&i.tm.operand_types[dest], ®ymm)
5923 || operand_type_equal (&i.tm.operand_types[dest], ®zmm)))));
5925 if (i.imm_operands == 0)
5927 /* When there is no immediate operand, generate an 8bit
5928 immediate operand to encode the first operand. */
5929 exp = &im_expressions[i.imm_operands++];
5930 i.op[i.operands].imms = exp;
5931 i.types[i.operands] = imm8;
5933 /* If VexW1 is set, the first operand is the source and
5934 the second operand is encoded in the immediate operand. */
5935 if (i.tm.opcode_modifier.vexw == VEXW1)
5946 /* FMA swaps REG and NDS. */
5947 if (i.tm.cpu_flags.bitfield.cpufma)
5955 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
5957 || operand_type_equal (&i.tm.operand_types[reg_slot],
5959 || operand_type_equal (&i.tm.operand_types[reg_slot],
5961 exp->X_op = O_constant;
5962 exp->X_add_number = register_number (i.op[reg_slot].regs) << 4;
5963 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
5967 unsigned int imm_slot;
5969 if (i.tm.opcode_modifier.vexw == VEXW0)
5971 /* If VexW0 is set, the third operand is the source and
5972 the second operand is encoded in the immediate
5979 /* VexW1 is set, the second operand is the source and
5980 the third operand is encoded in the immediate
5986 if (i.tm.opcode_modifier.immext)
5988 /* When ImmExt is set, the immdiate byte is the last
5990 imm_slot = i.operands - 1;
5998 /* Turn on Imm8 so that output_imm will generate it. */
5999 i.types[imm_slot].bitfield.imm8 = 1;
6002 gas_assert (operand_type_equal (&i.tm.operand_types[reg_slot],
6004 || operand_type_equal (&i.tm.operand_types[reg_slot],
6006 || operand_type_equal (&i.tm.operand_types[reg_slot],
6008 i.op[imm_slot].imms->X_add_number
6009 |= register_number (i.op[reg_slot].regs) << 4;
6010 gas_assert ((i.op[reg_slot].regs->reg_flags & RegVRex) == 0);
6013 gas_assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm)
6014 || operand_type_equal (&i.tm.operand_types[nds],
6016 || operand_type_equal (&i.tm.operand_types[nds],
6018 i.vex.register_specifier = i.op[nds].regs;
6023 /* i.reg_operands MUST be the number of real register operands;
6024 implicit registers do not count. If there are 3 register
6025 operands, it must be a instruction with VexNDS. For a
6026 instruction with VexNDD, the destination register is encoded
6027 in VEX prefix. If there are 4 register operands, it must be
6028 a instruction with VEX prefix and 3 sources. */
6029 if (i.mem_operands == 0
6030 && ((i.reg_operands == 2
6031 && i.tm.opcode_modifier.vexvvvv <= VEXXDS)
6032 || (i.reg_operands == 3
6033 && i.tm.opcode_modifier.vexvvvv == VEXXDS)
6034 || (i.reg_operands == 4 && vex_3_sources)))
6042 /* When there are 3 operands, one of them may be immediate,
6043 which may be the first or the last operand. Otherwise,
6044 the first operand must be shift count register (cl) or it
6045 is an instruction with VexNDS. */
6046 gas_assert (i.imm_operands == 1
6047 || (i.imm_operands == 0
6048 && (i.tm.opcode_modifier.vexvvvv == VEXXDS
6049 || i.types[0].bitfield.shiftcount)));
6050 if (operand_type_check (i.types[0], imm)
6051 || i.types[0].bitfield.shiftcount)
6057 /* When there are 4 operands, the first two must be 8bit
6058 immediate operands. The source operand will be the 3rd
6061 For instructions with VexNDS, if the first operand
6062 an imm8, the source operand is the 2nd one. If the last
6063 operand is imm8, the source operand is the first one. */
6064 gas_assert ((i.imm_operands == 2
6065 && i.types[0].bitfield.imm8
6066 && i.types[1].bitfield.imm8)
6067 || (i.tm.opcode_modifier.vexvvvv == VEXXDS
6068 && i.imm_operands == 1
6069 && (i.types[0].bitfield.imm8
6070 || i.types[i.operands - 1].bitfield.imm8
6072 if (i.imm_operands == 2)
6076 if (i.types[0].bitfield.imm8)
6083 if (i.tm.opcode_modifier.evex)
6085 /* For EVEX instructions, when there are 5 operands, the
6086 first one must be immediate operand. If the second one
6087 is immediate operand, the source operand is the 3th
6088 one. If the last one is immediate operand, the source
6089 operand is the 2nd one. */
6090 gas_assert (i.imm_operands == 2
6091 && i.tm.opcode_modifier.sae
6092 && operand_type_check (i.types[0], imm));
6093 if (operand_type_check (i.types[1], imm))
6095 else if (operand_type_check (i.types[4], imm))
6109 /* RC/SAE operand could be between DEST and SRC. That happens
6110 when one operand is GPR and the other one is XMM/YMM/ZMM
6112 if (i.rounding && i.rounding->operand == (int) dest)
6115 if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6117 /* For instructions with VexNDS, the register-only source
6118 operand must be 32/64bit integer, XMM, YMM or ZMM
6119 register. It is encoded in VEX prefix. We need to
6120 clear RegMem bit before calling operand_type_equal. */
6122 i386_operand_type op;
6125 /* Check register-only source operand when two source
6126 operands are swapped. */
6127 if (!i.tm.operand_types[source].bitfield.baseindex
6128 && i.tm.operand_types[dest].bitfield.baseindex)
6136 op = i.tm.operand_types[vvvv];
6137 op.bitfield.regmem = 0;
6138 if ((dest + 1) >= i.operands
6139 || (op.bitfield.reg32 != 1
6140 && !op.bitfield.reg64 != 1
6141 && !operand_type_equal (&op, ®xmm)
6142 && !operand_type_equal (&op, ®ymm)
6143 && !operand_type_equal (&op, ®zmm)
6144 && !operand_type_equal (&op, ®mask)))
6146 i.vex.register_specifier = i.op[vvvv].regs;
6152 /* One of the register operands will be encoded in the i.tm.reg
6153 field, the other in the combined i.tm.mode and i.tm.regmem
6154 fields. If no form of this instruction supports a memory
6155 destination operand, then we assume the source operand may
6156 sometimes be a memory operand and so we need to store the
6157 destination in the i.rm.reg field. */
6158 if (!i.tm.operand_types[dest].bitfield.regmem
6159 && operand_type_check (i.tm.operand_types[dest], anymem) == 0)
6161 i.rm.reg = i.op[dest].regs->reg_num;
6162 i.rm.regmem = i.op[source].regs->reg_num;
6163 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6165 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6167 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6169 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6174 i.rm.reg = i.op[source].regs->reg_num;
6175 i.rm.regmem = i.op[dest].regs->reg_num;
6176 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
6178 if ((i.op[dest].regs->reg_flags & RegVRex) != 0)
6180 if ((i.op[source].regs->reg_flags & RegRex) != 0)
6182 if ((i.op[source].regs->reg_flags & RegVRex) != 0)
6185 if (flag_code != CODE_64BIT && (i.rex & (REX_R | REX_B)))
6187 if (!i.types[0].bitfield.control
6188 && !i.types[1].bitfield.control)
6190 i.rex &= ~(REX_R | REX_B);
6191 add_prefix (LOCK_PREFIX_OPCODE);
6195 { /* If it's not 2 reg operands... */
6200 unsigned int fake_zero_displacement = 0;
6203 for (op = 0; op < i.operands; op++)
6204 if (operand_type_check (i.types[op], anymem))
6206 gas_assert (op < i.operands);
6208 if (i.tm.opcode_modifier.vecsib)
6210 if (i.index_reg->reg_num == RegEiz
6211 || i.index_reg->reg_num == RegRiz)
6214 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6217 i.sib.base = NO_BASE_REGISTER;
6218 i.sib.scale = i.log2_scale_factor;
6219 /* No Vec_Disp8 if there is no base. */
6220 i.types[op].bitfield.vec_disp8 = 0;
6221 i.types[op].bitfield.disp8 = 0;
6222 i.types[op].bitfield.disp16 = 0;
6223 i.types[op].bitfield.disp64 = 0;
6224 if (flag_code != CODE_64BIT)
6226 /* Must be 32 bit */
6227 i.types[op].bitfield.disp32 = 1;
6228 i.types[op].bitfield.disp32s = 0;
6232 i.types[op].bitfield.disp32 = 0;
6233 i.types[op].bitfield.disp32s = 1;
6236 i.sib.index = i.index_reg->reg_num;
6237 if ((i.index_reg->reg_flags & RegRex) != 0)
6239 if ((i.index_reg->reg_flags & RegVRex) != 0)
6245 if (i.base_reg == 0)
6248 if (!i.disp_operands)
6250 fake_zero_displacement = 1;
6251 /* Instructions with VSIB byte need 32bit displacement
6252 if there is no base register. */
6253 if (i.tm.opcode_modifier.vecsib)
6254 i.types[op].bitfield.disp32 = 1;
6256 if (i.index_reg == 0)
6258 gas_assert (!i.tm.opcode_modifier.vecsib);
6259 /* Operand is just <disp> */
6260 if (flag_code == CODE_64BIT)
6262 /* 64bit mode overwrites the 32bit absolute
6263 addressing by RIP relative addressing and
6264 absolute addressing is encoded by one of the
6265 redundant SIB forms. */
6266 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6267 i.sib.base = NO_BASE_REGISTER;
6268 i.sib.index = NO_INDEX_REGISTER;
6269 i.types[op] = ((i.prefix[ADDR_PREFIX] == 0)
6270 ? disp32s : disp32);
6272 else if ((flag_code == CODE_16BIT)
6273 ^ (i.prefix[ADDR_PREFIX] != 0))
6275 i.rm.regmem = NO_BASE_REGISTER_16;
6276 i.types[op] = disp16;
6280 i.rm.regmem = NO_BASE_REGISTER;
6281 i.types[op] = disp32;
6284 else if (!i.tm.opcode_modifier.vecsib)
6286 /* !i.base_reg && i.index_reg */
6287 if (i.index_reg->reg_num == RegEiz
6288 || i.index_reg->reg_num == RegRiz)
6289 i.sib.index = NO_INDEX_REGISTER;
6291 i.sib.index = i.index_reg->reg_num;
6292 i.sib.base = NO_BASE_REGISTER;
6293 i.sib.scale = i.log2_scale_factor;
6294 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6295 /* No Vec_Disp8 if there is no base. */
6296 i.types[op].bitfield.vec_disp8 = 0;
6297 i.types[op].bitfield.disp8 = 0;
6298 i.types[op].bitfield.disp16 = 0;
6299 i.types[op].bitfield.disp64 = 0;
6300 if (flag_code != CODE_64BIT)
6302 /* Must be 32 bit */
6303 i.types[op].bitfield.disp32 = 1;
6304 i.types[op].bitfield.disp32s = 0;
6308 i.types[op].bitfield.disp32 = 0;
6309 i.types[op].bitfield.disp32s = 1;
6311 if ((i.index_reg->reg_flags & RegRex) != 0)
6315 /* RIP addressing for 64bit mode. */
6316 else if (i.base_reg->reg_num == RegRip ||
6317 i.base_reg->reg_num == RegEip)
6319 gas_assert (!i.tm.opcode_modifier.vecsib);
6320 i.rm.regmem = NO_BASE_REGISTER;
6321 i.types[op].bitfield.disp8 = 0;
6322 i.types[op].bitfield.disp16 = 0;
6323 i.types[op].bitfield.disp32 = 0;
6324 i.types[op].bitfield.disp32s = 1;
6325 i.types[op].bitfield.disp64 = 0;
6326 i.types[op].bitfield.vec_disp8 = 0;
6327 i.flags[op] |= Operand_PCrel;
6328 if (! i.disp_operands)
6329 fake_zero_displacement = 1;
6331 else if (i.base_reg->reg_type.bitfield.reg16)
6333 gas_assert (!i.tm.opcode_modifier.vecsib);
6334 switch (i.base_reg->reg_num)
6337 if (i.index_reg == 0)
6339 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
6340 i.rm.regmem = i.index_reg->reg_num - 6;
6344 if (i.index_reg == 0)
6347 if (operand_type_check (i.types[op], disp) == 0)
6349 /* fake (%bp) into 0(%bp) */
6350 if (i.tm.operand_types[op].bitfield.vec_disp8)
6351 i.types[op].bitfield.vec_disp8 = 1;
6353 i.types[op].bitfield.disp8 = 1;
6354 fake_zero_displacement = 1;
6357 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
6358 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
6360 default: /* (%si) -> 4 or (%di) -> 5 */
6361 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
6363 i.rm.mode = mode_from_disp_size (i.types[op]);
6365 else /* i.base_reg and 32/64 bit mode */
6367 if (flag_code == CODE_64BIT
6368 && operand_type_check (i.types[op], disp))
6370 i386_operand_type temp;
6371 operand_type_set (&temp, 0);
6372 temp.bitfield.disp8 = i.types[op].bitfield.disp8;
6373 temp.bitfield.vec_disp8
6374 = i.types[op].bitfield.vec_disp8;
6376 if (i.prefix[ADDR_PREFIX] == 0)
6377 i.types[op].bitfield.disp32s = 1;
6379 i.types[op].bitfield.disp32 = 1;
6382 if (!i.tm.opcode_modifier.vecsib)
6383 i.rm.regmem = i.base_reg->reg_num;
6384 if ((i.base_reg->reg_flags & RegRex) != 0)
6386 i.sib.base = i.base_reg->reg_num;
6387 /* x86-64 ignores REX prefix bit here to avoid decoder
6389 if (!(i.base_reg->reg_flags & RegRex)
6390 && (i.base_reg->reg_num == EBP_REG_NUM
6391 || i.base_reg->reg_num == ESP_REG_NUM))
6393 if (i.base_reg->reg_num == 5 && i.disp_operands == 0)
6395 fake_zero_displacement = 1;
6396 if (i.tm.operand_types [op].bitfield.vec_disp8)
6397 i.types[op].bitfield.vec_disp8 = 1;
6399 i.types[op].bitfield.disp8 = 1;
6401 i.sib.scale = i.log2_scale_factor;
6402 if (i.index_reg == 0)
6404 gas_assert (!i.tm.opcode_modifier.vecsib);
6405 /* <disp>(%esp) becomes two byte modrm with no index
6406 register. We've already stored the code for esp
6407 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
6408 Any base register besides %esp will not use the
6409 extra modrm byte. */
6410 i.sib.index = NO_INDEX_REGISTER;
6412 else if (!i.tm.opcode_modifier.vecsib)
6414 if (i.index_reg->reg_num == RegEiz
6415 || i.index_reg->reg_num == RegRiz)
6416 i.sib.index = NO_INDEX_REGISTER;
6418 i.sib.index = i.index_reg->reg_num;
6419 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
6420 if ((i.index_reg->reg_flags & RegRex) != 0)
6425 && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
6426 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL))
6430 if (!fake_zero_displacement
6434 fake_zero_displacement = 1;
6435 if (i.disp_encoding == disp_encoding_8bit)
6436 i.types[op].bitfield.disp8 = 1;
6438 i.types[op].bitfield.disp32 = 1;
6440 i.rm.mode = mode_from_disp_size (i.types[op]);
6444 if (fake_zero_displacement)
6446 /* Fakes a zero displacement assuming that i.types[op]
6447 holds the correct displacement size. */
6450 gas_assert (i.op[op].disps == 0);
6451 exp = &disp_expressions[i.disp_operands++];
6452 i.op[op].disps = exp;
6453 exp->X_op = O_constant;
6454 exp->X_add_number = 0;
6455 exp->X_add_symbol = (symbolS *) 0;
6456 exp->X_op_symbol = (symbolS *) 0;
6464 if (i.tm.opcode_modifier.vexsources == XOP2SOURCES)
6466 if (operand_type_check (i.types[0], imm))
6467 i.vex.register_specifier = NULL;
6470 /* VEX.vvvv encodes one of the sources when the first
6471 operand is not an immediate. */
6472 if (i.tm.opcode_modifier.vexw == VEXW0)
6473 i.vex.register_specifier = i.op[0].regs;
6475 i.vex.register_specifier = i.op[1].regs;
6478 /* Destination is a XMM register encoded in the ModRM.reg
6480 i.rm.reg = i.op[2].regs->reg_num;
6481 if ((i.op[2].regs->reg_flags & RegRex) != 0)
6484 /* ModRM.rm and VEX.B encodes the other source. */
6485 if (!i.mem_operands)
6489 if (i.tm.opcode_modifier.vexw == VEXW0)
6490 i.rm.regmem = i.op[1].regs->reg_num;
6492 i.rm.regmem = i.op[0].regs->reg_num;
6494 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6498 else if (i.tm.opcode_modifier.vexvvvv == VEXLWP)
6500 i.vex.register_specifier = i.op[2].regs;
6501 if (!i.mem_operands)
6504 i.rm.regmem = i.op[1].regs->reg_num;
6505 if ((i.op[1].regs->reg_flags & RegRex) != 0)
6509 /* Fill in i.rm.reg or i.rm.regmem field with register operand
6510 (if any) based on i.tm.extension_opcode. Again, we must be
6511 careful to make sure that segment/control/debug/test/MMX
6512 registers are coded into the i.rm.reg field. */
6513 else if (i.reg_operands)
6516 unsigned int vex_reg = ~0;
6518 for (op = 0; op < i.operands; op++)
6519 if (i.types[op].bitfield.reg8
6520 || i.types[op].bitfield.reg16
6521 || i.types[op].bitfield.reg32
6522 || i.types[op].bitfield.reg64
6523 || i.types[op].bitfield.regmmx
6524 || i.types[op].bitfield.regxmm
6525 || i.types[op].bitfield.regymm
6526 || i.types[op].bitfield.regbnd
6527 || i.types[op].bitfield.regzmm
6528 || i.types[op].bitfield.regmask
6529 || i.types[op].bitfield.sreg2
6530 || i.types[op].bitfield.sreg3
6531 || i.types[op].bitfield.control
6532 || i.types[op].bitfield.debug
6533 || i.types[op].bitfield.test)
6538 else if (i.tm.opcode_modifier.vexvvvv == VEXXDS)
6540 /* For instructions with VexNDS, the register-only
6541 source operand is encoded in VEX prefix. */
6542 gas_assert (mem != (unsigned int) ~0);
6547 gas_assert (op < i.operands);
6551 /* Check register-only source operand when two source
6552 operands are swapped. */
6553 if (!i.tm.operand_types[op].bitfield.baseindex
6554 && i.tm.operand_types[op + 1].bitfield.baseindex)
6558 gas_assert (mem == (vex_reg + 1)
6559 && op < i.operands);
6564 gas_assert (vex_reg < i.operands);
6568 else if (i.tm.opcode_modifier.vexvvvv == VEXNDD)
6570 /* For instructions with VexNDD, the register destination
6571 is encoded in VEX prefix. */
6572 if (i.mem_operands == 0)
6574 /* There is no memory operand. */
6575 gas_assert ((op + 2) == i.operands);
6580 /* There are only 2 operands. */
6581 gas_assert (op < 2 && i.operands == 2);
6586 gas_assert (op < i.operands);
6588 if (vex_reg != (unsigned int) ~0)
6590 i386_operand_type *type = &i.tm.operand_types[vex_reg];
6592 if (type->bitfield.reg32 != 1
6593 && type->bitfield.reg64 != 1
6594 && !operand_type_equal (type, ®xmm)
6595 && !operand_type_equal (type, ®ymm)
6596 && !operand_type_equal (type, ®zmm)
6597 && !operand_type_equal (type, ®mask))
6600 i.vex.register_specifier = i.op[vex_reg].regs;
6603 /* Don't set OP operand twice. */
6606 /* If there is an extension opcode to put here, the
6607 register number must be put into the regmem field. */
6608 if (i.tm.extension_opcode != None)
6610 i.rm.regmem = i.op[op].regs->reg_num;
6611 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6613 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6618 i.rm.reg = i.op[op].regs->reg_num;
6619 if ((i.op[op].regs->reg_flags & RegRex) != 0)
6621 if ((i.op[op].regs->reg_flags & RegVRex) != 0)
6626 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
6627 must set it to 3 to indicate this is a register operand
6628 in the regmem field. */
6629 if (!i.mem_operands)
6633 /* Fill in i.rm.reg field with extension opcode (if any). */
6634 if (i.tm.extension_opcode != None)
6635 i.rm.reg = i.tm.extension_opcode;
6641 output_branch (void)
6647 relax_substateT subtype;
6651 code16 = flag_code == CODE_16BIT ? CODE16 : 0;
6652 size = i.disp_encoding == disp_encoding_32bit ? BIG : SMALL;
6655 if (i.prefix[DATA_PREFIX] != 0)
6661 /* Pentium4 branch hints. */
6662 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6663 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6668 if (i.prefix[REX_PREFIX] != 0)
6674 /* BND prefixed jump. */
6675 if (i.prefix[BND_PREFIX] != 0)
6677 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6681 if (i.prefixes != 0 && !intel_syntax)
6682 as_warn (_("skipping prefixes on this instruction"));
6684 /* It's always a symbol; End frag & setup for relax.
6685 Make sure there is enough room in this frag for the largest
6686 instruction we may generate in md_convert_frag. This is 2
6687 bytes for the opcode and room for the prefix and largest
6689 frag_grow (prefix + 2 + 4);
6690 /* Prefix and 1 opcode byte go in fr_fix. */
6691 p = frag_more (prefix + 1);
6692 if (i.prefix[DATA_PREFIX] != 0)
6693 *p++ = DATA_PREFIX_OPCODE;
6694 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
6695 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
6696 *p++ = i.prefix[SEG_PREFIX];
6697 if (i.prefix[REX_PREFIX] != 0)
6698 *p++ = i.prefix[REX_PREFIX];
6699 *p = i.tm.base_opcode;
6701 if ((unsigned char) *p == JUMP_PC_RELATIVE)
6702 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, size);
6703 else if (cpu_arch_flags.bitfield.cpui386)
6704 subtype = ENCODE_RELAX_STATE (COND_JUMP, size);
6706 subtype = ENCODE_RELAX_STATE (COND_JUMP86, size);
6709 sym = i.op[0].disps->X_add_symbol;
6710 off = i.op[0].disps->X_add_number;
6712 if (i.op[0].disps->X_op != O_constant
6713 && i.op[0].disps->X_op != O_symbol)
6715 /* Handle complex expressions. */
6716 sym = make_expr_symbol (i.op[0].disps);
6720 /* 1 possible extra opcode + 4 byte displacement go in var part.
6721 Pass reloc in fr_var. */
6722 frag_var (rs_machine_dependent, 5,
6724 || i.reloc[0] != NO_RELOC
6725 || (i.bnd_prefix == NULL && !add_bnd_prefix))
6727 : BFD_RELOC_X86_64_PC32_BND),
6728 subtype, sym, off, p);
6738 if (i.tm.opcode_modifier.jumpbyte)
6740 /* This is a loop or jecxz type instruction. */
6742 if (i.prefix[ADDR_PREFIX] != 0)
6744 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
6747 /* Pentium4 branch hints. */
6748 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
6749 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
6751 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
6760 if (flag_code == CODE_16BIT)
6763 if (i.prefix[DATA_PREFIX] != 0)
6765 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
6775 if (i.prefix[REX_PREFIX] != 0)
6777 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
6781 /* BND prefixed jump. */
6782 if (i.prefix[BND_PREFIX] != 0)
6784 FRAG_APPEND_1_CHAR (i.prefix[BND_PREFIX]);
6788 if (i.prefixes != 0 && !intel_syntax)
6789 as_warn (_("skipping prefixes on this instruction"));
6791 p = frag_more (i.tm.opcode_length + size);
6792 switch (i.tm.opcode_length)
6795 *p++ = i.tm.base_opcode >> 8;
6797 *p++ = i.tm.base_opcode;
6803 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6804 i.op[0].disps, 1, reloc (size, 1, 1,
6805 (i.bnd_prefix != NULL
6809 /* All jumps handled here are signed, but don't use a signed limit
6810 check for 32 and 16 bit jumps as we want to allow wrap around at
6811 4G and 64k respectively. */
6813 fixP->fx_signed = 1;
6817 output_interseg_jump (void)
6825 if (flag_code == CODE_16BIT)
6829 if (i.prefix[DATA_PREFIX] != 0)
6835 if (i.prefix[REX_PREFIX] != 0)
6845 if (i.prefixes != 0 && !intel_syntax)
6846 as_warn (_("skipping prefixes on this instruction"));
6848 /* 1 opcode; 2 segment; offset */
6849 p = frag_more (prefix + 1 + 2 + size);
6851 if (i.prefix[DATA_PREFIX] != 0)
6852 *p++ = DATA_PREFIX_OPCODE;
6854 if (i.prefix[REX_PREFIX] != 0)
6855 *p++ = i.prefix[REX_PREFIX];
6857 *p++ = i.tm.base_opcode;
6858 if (i.op[1].imms->X_op == O_constant)
6860 offsetT n = i.op[1].imms->X_add_number;
6863 && !fits_in_unsigned_word (n)
6864 && !fits_in_signed_word (n))
6866 as_bad (_("16-bit jump out of range"));
6869 md_number_to_chars (p, n, size);
6872 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
6873 i.op[1].imms, 0, reloc (size, 0, 0, 0, i.reloc[1]));
6874 if (i.op[0].imms->X_op != O_constant)
6875 as_bad (_("can't handle non absolute segment in `%s'"),
6877 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
6883 fragS *insn_start_frag;
6884 offsetT insn_start_off;
6886 /* Tie dwarf2 debug info to the address at the start of the insn.
6887 We can't do this after the insn has been output as the current
6888 frag may have been closed off. eg. by frag_var. */
6889 dwarf2_emit_insn (0);
6891 insn_start_frag = frag_now;
6892 insn_start_off = frag_now_fix ();
6895 if (i.tm.opcode_modifier.jump)
6897 else if (i.tm.opcode_modifier.jumpbyte
6898 || i.tm.opcode_modifier.jumpdword)
6900 else if (i.tm.opcode_modifier.jumpintersegment)
6901 output_interseg_jump ();
6904 /* Output normal instructions here. */
6908 unsigned int prefix;
6910 /* Since the VEX/EVEX prefix contains the implicit prefix, we
6911 don't need the explicit prefix. */
6912 if (!i.tm.opcode_modifier.vex && !i.tm.opcode_modifier.evex)
6914 switch (i.tm.opcode_length)
6917 if (i.tm.base_opcode & 0xff000000)
6919 prefix = (i.tm.base_opcode >> 24) & 0xff;
6924 if ((i.tm.base_opcode & 0xff0000) != 0)
6926 prefix = (i.tm.base_opcode >> 16) & 0xff;
6927 if (i.tm.cpu_flags.bitfield.cpupadlock)
6930 if (prefix != REPE_PREFIX_OPCODE
6931 || (i.prefix[REP_PREFIX]
6932 != REPE_PREFIX_OPCODE))
6933 add_prefix (prefix);
6936 add_prefix (prefix);
6945 /* The prefix bytes. */
6946 for (j = ARRAY_SIZE (i.prefix), q = i.prefix; j > 0; j--, q++)
6948 FRAG_APPEND_1_CHAR (*q);
6952 for (j = 0, q = i.prefix; j < ARRAY_SIZE (i.prefix); j++, q++)
6957 /* REX byte is encoded in VEX prefix. */
6961 FRAG_APPEND_1_CHAR (*q);
6964 /* There should be no other prefixes for instructions
6969 /* For EVEX instructions i.vrex should become 0 after
6970 build_evex_prefix. For VEX instructions upper 16 registers
6971 aren't available, so VREX should be 0. */
6974 /* Now the VEX prefix. */
6975 p = frag_more (i.vex.length);
6976 for (j = 0; j < i.vex.length; j++)
6977 p[j] = i.vex.bytes[j];
6980 /* Now the opcode; be careful about word order here! */
6981 if (i.tm.opcode_length == 1)
6983 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
6987 switch (i.tm.opcode_length)
6991 *p++ = (i.tm.base_opcode >> 24) & 0xff;
6992 *p++ = (i.tm.base_opcode >> 16) & 0xff;
6996 *p++ = (i.tm.base_opcode >> 16) & 0xff;
7006 /* Put out high byte first: can't use md_number_to_chars! */
7007 *p++ = (i.tm.base_opcode >> 8) & 0xff;
7008 *p = i.tm.base_opcode & 0xff;
7011 /* Now the modrm byte and sib byte (if present). */
7012 if (i.tm.opcode_modifier.modrm)
7014 FRAG_APPEND_1_CHAR ((i.rm.regmem << 0
7017 /* If i.rm.regmem == ESP (4)
7018 && i.rm.mode != (Register mode)
7020 ==> need second modrm byte. */
7021 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
7023 && !(i.base_reg && i.base_reg->reg_type.bitfield.reg16))
7024 FRAG_APPEND_1_CHAR ((i.sib.base << 0
7026 | i.sib.scale << 6));
7029 if (i.disp_operands)
7030 output_disp (insn_start_frag, insn_start_off);
7033 output_imm (insn_start_frag, insn_start_off);
7039 pi ("" /*line*/, &i);
7041 #endif /* DEBUG386 */
7044 /* Return the size of the displacement operand N. */
7047 disp_size (unsigned int n)
7051 /* Vec_Disp8 has to be 8bit. */
7052 if (i.types[n].bitfield.vec_disp8)
7054 else if (i.types[n].bitfield.disp64)
7056 else if (i.types[n].bitfield.disp8)
7058 else if (i.types[n].bitfield.disp16)
7063 /* Return the size of the immediate operand N. */
7066 imm_size (unsigned int n)
7069 if (i.types[n].bitfield.imm64)
7071 else if (i.types[n].bitfield.imm8 || i.types[n].bitfield.imm8s)
7073 else if (i.types[n].bitfield.imm16)
7079 output_disp (fragS *insn_start_frag, offsetT insn_start_off)
7084 for (n = 0; n < i.operands; n++)
7086 if (i.types[n].bitfield.vec_disp8
7087 || operand_type_check (i.types[n], disp))
7089 if (i.op[n].disps->X_op == O_constant)
7091 int size = disp_size (n);
7092 offsetT val = i.op[n].disps->X_add_number;
7094 if (i.types[n].bitfield.vec_disp8)
7096 val = offset_in_range (val, size);
7097 p = frag_more (size);
7098 md_number_to_chars (p, val, size);
7102 enum bfd_reloc_code_real reloc_type;
7103 int size = disp_size (n);
7104 int sign = i.types[n].bitfield.disp32s;
7105 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
7107 /* We can't have 8 bit displacement here. */
7108 gas_assert (!i.types[n].bitfield.disp8);
7110 /* The PC relative address is computed relative
7111 to the instruction boundary, so in case immediate
7112 fields follows, we need to adjust the value. */
7113 if (pcrel && i.imm_operands)
7118 for (n1 = 0; n1 < i.operands; n1++)
7119 if (operand_type_check (i.types[n1], imm))
7121 /* Only one immediate is allowed for PC
7122 relative address. */
7123 gas_assert (sz == 0);
7125 i.op[n].disps->X_add_number -= sz;
7127 /* We should find the immediate. */
7128 gas_assert (sz != 0);
7131 p = frag_more (size);
7132 reloc_type = reloc (size, pcrel, sign,
7133 (i.bnd_prefix != NULL
7137 && GOT_symbol == i.op[n].disps->X_add_symbol
7138 && (((reloc_type == BFD_RELOC_32
7139 || reloc_type == BFD_RELOC_X86_64_32S
7140 || (reloc_type == BFD_RELOC_64
7142 && (i.op[n].disps->X_op == O_symbol
7143 || (i.op[n].disps->X_op == O_add
7144 && ((symbol_get_value_expression
7145 (i.op[n].disps->X_op_symbol)->X_op)
7147 || reloc_type == BFD_RELOC_32_PCREL))
7151 if (insn_start_frag == frag_now)
7152 add = (p - frag_now->fr_literal) - insn_start_off;
7157 add = insn_start_frag->fr_fix - insn_start_off;
7158 for (fr = insn_start_frag->fr_next;
7159 fr && fr != frag_now; fr = fr->fr_next)
7161 add += p - frag_now->fr_literal;
7166 reloc_type = BFD_RELOC_386_GOTPC;
7167 i.op[n].imms->X_add_number += add;
7169 else if (reloc_type == BFD_RELOC_64)
7170 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7172 /* Don't do the adjustment for x86-64, as there
7173 the pcrel addressing is relative to the _next_
7174 insn, and that is taken care of in other code. */
7175 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7177 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7178 i.op[n].disps, pcrel, reloc_type);
7185 output_imm (fragS *insn_start_frag, offsetT insn_start_off)
7190 for (n = 0; n < i.operands; n++)
7192 /* Skip SAE/RC Imm operand in EVEX. They are already handled. */
7193 if (i.rounding && (int) n == i.rounding->operand)
7196 if (operand_type_check (i.types[n], imm))
7198 if (i.op[n].imms->X_op == O_constant)
7200 int size = imm_size (n);
7203 val = offset_in_range (i.op[n].imms->X_add_number,
7205 p = frag_more (size);
7206 md_number_to_chars (p, val, size);
7210 /* Not absolute_section.
7211 Need a 32-bit fixup (don't support 8bit
7212 non-absolute imms). Try to support other
7214 enum bfd_reloc_code_real reloc_type;
7215 int size = imm_size (n);
7218 if (i.types[n].bitfield.imm32s
7219 && (i.suffix == QWORD_MNEM_SUFFIX
7220 || (!i.suffix && i.tm.opcode_modifier.no_lsuf)))
7225 p = frag_more (size);
7226 reloc_type = reloc (size, 0, sign, 0, i.reloc[n]);
7228 /* This is tough to explain. We end up with this one if we
7229 * have operands that look like
7230 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
7231 * obtain the absolute address of the GOT, and it is strongly
7232 * preferable from a performance point of view to avoid using
7233 * a runtime relocation for this. The actual sequence of
7234 * instructions often look something like:
7239 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
7241 * The call and pop essentially return the absolute address
7242 * of the label .L66 and store it in %ebx. The linker itself
7243 * will ultimately change the first operand of the addl so
7244 * that %ebx points to the GOT, but to keep things simple, the
7245 * .o file must have this operand set so that it generates not
7246 * the absolute address of .L66, but the absolute address of
7247 * itself. This allows the linker itself simply treat a GOTPC
7248 * relocation as asking for a pcrel offset to the GOT to be
7249 * added in, and the addend of the relocation is stored in the
7250 * operand field for the instruction itself.
7252 * Our job here is to fix the operand so that it would add
7253 * the correct offset so that %ebx would point to itself. The
7254 * thing that is tricky is that .-.L66 will point to the
7255 * beginning of the instruction, so we need to further modify
7256 * the operand so that it will point to itself. There are
7257 * other cases where you have something like:
7259 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
7261 * and here no correction would be required. Internally in
7262 * the assembler we treat operands of this form as not being
7263 * pcrel since the '.' is explicitly mentioned, and I wonder
7264 * whether it would simplify matters to do it this way. Who
7265 * knows. In earlier versions of the PIC patches, the
7266 * pcrel_adjust field was used to store the correction, but
7267 * since the expression is not pcrel, I felt it would be
7268 * confusing to do it this way. */
7270 if ((reloc_type == BFD_RELOC_32
7271 || reloc_type == BFD_RELOC_X86_64_32S
7272 || reloc_type == BFD_RELOC_64)
7274 && GOT_symbol == i.op[n].imms->X_add_symbol
7275 && (i.op[n].imms->X_op == O_symbol
7276 || (i.op[n].imms->X_op == O_add
7277 && ((symbol_get_value_expression
7278 (i.op[n].imms->X_op_symbol)->X_op)
7283 if (insn_start_frag == frag_now)
7284 add = (p - frag_now->fr_literal) - insn_start_off;
7289 add = insn_start_frag->fr_fix - insn_start_off;
7290 for (fr = insn_start_frag->fr_next;
7291 fr && fr != frag_now; fr = fr->fr_next)
7293 add += p - frag_now->fr_literal;
7297 reloc_type = BFD_RELOC_386_GOTPC;
7299 reloc_type = BFD_RELOC_X86_64_GOTPC32;
7301 reloc_type = BFD_RELOC_X86_64_GOTPC64;
7302 i.op[n].imms->X_add_number += add;
7304 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
7305 i.op[n].imms, 0, reloc_type);
7311 /* x86_cons_fix_new is called via the expression parsing code when a
7312 reloc is needed. We use this hook to get the correct .got reloc. */
7313 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
7314 static int cons_sign = -1;
7317 x86_cons_fix_new (fragS *frag, unsigned int off, unsigned int len,
7320 enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, 0, got_reloc);
7322 got_reloc = NO_RELOC;
7325 if (exp->X_op == O_secrel)
7327 exp->X_op = O_symbol;
7328 r = BFD_RELOC_32_SECREL;
7332 fix_new_exp (frag, off, len, exp, 0, r);
7335 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
7336 purpose of the `.dc.a' internal pseudo-op. */
7339 x86_address_bytes (void)
7341 if ((stdoutput->arch_info->mach & bfd_mach_x64_32))
7343 return stdoutput->arch_info->bits_per_address / 8;
7346 #if !(defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (OBJ_MACH_O)) \
7348 # define lex_got(reloc, adjust, types) NULL
7350 /* Parse operands of the form
7351 <symbol>@GOTOFF+<nnn>
7352 and similar .plt or .got references.
7354 If we find one, set up the correct relocation in RELOC and copy the
7355 input string, minus the `@GOTOFF' into a malloc'd buffer for
7356 parsing by the calling routine. Return this buffer, and if ADJUST
7357 is non-null set it to the length of the string we removed from the
7358 input line. Otherwise return NULL. */
7360 lex_got (enum bfd_reloc_code_real *rel,
7362 i386_operand_type *types,
7365 /* Some of the relocations depend on the size of what field is to
7366 be relocated. But in our callers i386_immediate and i386_displacement
7367 we don't yet know the operand size (this will be set by insn
7368 matching). Hence we record the word32 relocation here,
7369 and adjust the reloc according to the real size in reloc(). */
7370 static const struct {
7373 const enum bfd_reloc_code_real rel[2];
7374 const i386_operand_type types64;
7376 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7377 { STRING_COMMA_LEN ("SIZE"), { BFD_RELOC_SIZE32,
7379 OPERAND_TYPE_IMM32_64 },
7381 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real,
7382 BFD_RELOC_X86_64_PLTOFF64 },
7383 OPERAND_TYPE_IMM64 },
7384 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32,
7385 BFD_RELOC_X86_64_PLT32 },
7386 OPERAND_TYPE_IMM32_32S_DISP32 },
7387 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real,
7388 BFD_RELOC_X86_64_GOTPLT64 },
7389 OPERAND_TYPE_IMM64_DISP64 },
7390 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF,
7391 BFD_RELOC_X86_64_GOTOFF64 },
7392 OPERAND_TYPE_IMM64_DISP64 },
7393 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real,
7394 BFD_RELOC_X86_64_GOTPCREL },
7395 OPERAND_TYPE_IMM32_32S_DISP32 },
7396 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD,
7397 BFD_RELOC_X86_64_TLSGD },
7398 OPERAND_TYPE_IMM32_32S_DISP32 },
7399 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM,
7400 _dummy_first_bfd_reloc_code_real },
7401 OPERAND_TYPE_NONE },
7402 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real,
7403 BFD_RELOC_X86_64_TLSLD },
7404 OPERAND_TYPE_IMM32_32S_DISP32 },
7405 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32,
7406 BFD_RELOC_X86_64_GOTTPOFF },
7407 OPERAND_TYPE_IMM32_32S_DISP32 },
7408 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32,
7409 BFD_RELOC_X86_64_TPOFF32 },
7410 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7411 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE,
7412 _dummy_first_bfd_reloc_code_real },
7413 OPERAND_TYPE_NONE },
7414 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32,
7415 BFD_RELOC_X86_64_DTPOFF32 },
7416 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7417 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE,
7418 _dummy_first_bfd_reloc_code_real },
7419 OPERAND_TYPE_NONE },
7420 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE,
7421 _dummy_first_bfd_reloc_code_real },
7422 OPERAND_TYPE_NONE },
7423 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32,
7424 BFD_RELOC_X86_64_GOT32 },
7425 OPERAND_TYPE_IMM32_32S_64_DISP32 },
7426 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC,
7427 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
7428 OPERAND_TYPE_IMM32_32S_DISP32 },
7429 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL,
7430 BFD_RELOC_X86_64_TLSDESC_CALL },
7431 OPERAND_TYPE_IMM32_32S_DISP32 },
7436 #if defined (OBJ_MAYBE_ELF)
7441 for (cp = input_line_pointer; *cp != '@'; cp++)
7442 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7445 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7447 int len = gotrel[j].len;
7448 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7450 if (gotrel[j].rel[object_64bit] != 0)
7453 char *tmpbuf, *past_reloc;
7455 *rel = gotrel[j].rel[object_64bit];
7459 if (flag_code != CODE_64BIT)
7461 types->bitfield.imm32 = 1;
7462 types->bitfield.disp32 = 1;
7465 *types = gotrel[j].types64;
7468 if (j != 0 && GOT_symbol == NULL)
7469 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
7471 /* The length of the first part of our input line. */
7472 first = cp - input_line_pointer;
7474 /* The second part goes from after the reloc token until
7475 (and including) an end_of_line char or comma. */
7476 past_reloc = cp + 1 + len;
7478 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7480 second = cp + 1 - past_reloc;
7482 /* Allocate and copy string. The trailing NUL shouldn't
7483 be necessary, but be safe. */
7484 tmpbuf = (char *) xmalloc (first + second + 2);
7485 memcpy (tmpbuf, input_line_pointer, first);
7486 if (second != 0 && *past_reloc != ' ')
7487 /* Replace the relocation token with ' ', so that
7488 errors like foo@GOTOFF1 will be detected. */
7489 tmpbuf[first++] = ' ';
7491 /* Increment length by 1 if the relocation token is
7496 memcpy (tmpbuf + first, past_reloc, second);
7497 tmpbuf[first + second] = '\0';
7498 if (bnd_prefix && *rel == BFD_RELOC_X86_64_PLT32)
7499 *rel = BFD_RELOC_X86_64_PLT32_BND;
7503 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7504 gotrel[j].str, 1 << (5 + object_64bit));
7509 /* Might be a symbol version string. Don't as_bad here. */
7518 /* Parse operands of the form
7519 <symbol>@SECREL32+<nnn>
7521 If we find one, set up the correct relocation in RELOC and copy the
7522 input string, minus the `@SECREL32' into a malloc'd buffer for
7523 parsing by the calling routine. Return this buffer, and if ADJUST
7524 is non-null set it to the length of the string we removed from the
7525 input line. Otherwise return NULL.
7527 This function is copied from the ELF version above adjusted for PE targets. */
7530 lex_got (enum bfd_reloc_code_real *rel ATTRIBUTE_UNUSED,
7531 int *adjust ATTRIBUTE_UNUSED,
7532 i386_operand_type *types ATTRIBUTE_UNUSED)
7538 const enum bfd_reloc_code_real rel[2];
7539 const i386_operand_type types64;
7543 { STRING_COMMA_LEN ("SECREL32"), { BFD_RELOC_32_SECREL,
7544 BFD_RELOC_32_SECREL },
7545 OPERAND_TYPE_IMM32_32S_64_DISP32_64 },
7551 for (cp = input_line_pointer; *cp != '@'; cp++)
7552 if (is_end_of_line[(unsigned char) *cp] || *cp == ',')
7555 for (j = 0; j < ARRAY_SIZE (gotrel); j++)
7557 int len = gotrel[j].len;
7559 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
7561 if (gotrel[j].rel[object_64bit] != 0)
7564 char *tmpbuf, *past_reloc;
7566 *rel = gotrel[j].rel[object_64bit];
7572 if (flag_code != CODE_64BIT)
7574 types->bitfield.imm32 = 1;
7575 types->bitfield.disp32 = 1;
7578 *types = gotrel[j].types64;
7581 /* The length of the first part of our input line. */
7582 first = cp - input_line_pointer;
7584 /* The second part goes from after the reloc token until
7585 (and including) an end_of_line char or comma. */
7586 past_reloc = cp + 1 + len;
7588 while (!is_end_of_line[(unsigned char) *cp] && *cp != ',')
7590 second = cp + 1 - past_reloc;
7592 /* Allocate and copy string. The trailing NUL shouldn't
7593 be necessary, but be safe. */
7594 tmpbuf = (char *) xmalloc (first + second + 2);
7595 memcpy (tmpbuf, input_line_pointer, first);
7596 if (second != 0 && *past_reloc != ' ')
7597 /* Replace the relocation token with ' ', so that
7598 errors like foo@SECLREL321 will be detected. */
7599 tmpbuf[first++] = ' ';
7600 memcpy (tmpbuf + first, past_reloc, second);
7601 tmpbuf[first + second] = '\0';
7605 as_bad (_("@%s reloc is not supported with %d-bit output format"),
7606 gotrel[j].str, 1 << (5 + object_64bit));
7611 /* Might be a symbol version string. Don't as_bad here. */
7618 x86_cons (expressionS *exp, int size)
7620 intel_syntax = -intel_syntax;
7623 if (size == 4 || (object_64bit && size == 8))
7625 /* Handle @GOTOFF and the like in an expression. */
7627 char *gotfree_input_line;
7630 save = input_line_pointer;
7631 gotfree_input_line = lex_got (&got_reloc, &adjust, NULL, 0);
7632 if (gotfree_input_line)
7633 input_line_pointer = gotfree_input_line;
7637 if (gotfree_input_line)
7639 /* expression () has merrily parsed up to the end of line,
7640 or a comma - in the wrong buffer. Transfer how far
7641 input_line_pointer has moved to the right buffer. */
7642 input_line_pointer = (save
7643 + (input_line_pointer - gotfree_input_line)
7645 free (gotfree_input_line);
7646 if (exp->X_op == O_constant
7647 || exp->X_op == O_absent
7648 || exp->X_op == O_illegal
7649 || exp->X_op == O_register
7650 || exp->X_op == O_big)
7652 char c = *input_line_pointer;
7653 *input_line_pointer = 0;
7654 as_bad (_("missing or invalid expression `%s'"), save);
7655 *input_line_pointer = c;
7662 intel_syntax = -intel_syntax;
7665 i386_intel_simplify (exp);
7669 signed_cons (int size)
7671 if (flag_code == CODE_64BIT)
7679 pe_directive_secrel (int dummy ATTRIBUTE_UNUSED)
7686 if (exp.X_op == O_symbol)
7687 exp.X_op = O_secrel;
7689 emit_expr (&exp, 4);
7691 while (*input_line_pointer++ == ',');
7693 input_line_pointer--;
7694 demand_empty_rest_of_line ();
7698 /* Handle Vector operations. */
7701 check_VecOperations (char *op_string, char *op_end)
7703 const reg_entry *mask;
7708 && (op_end == NULL || op_string < op_end))
7711 if (*op_string == '{')
7715 /* Check broadcasts. */
7716 if (strncmp (op_string, "1to", 3) == 0)
7721 goto duplicated_vec_op;
7724 if (*op_string == '8')
7725 bcst_type = BROADCAST_1TO8;
7726 else if (*op_string == '1'
7727 && *(op_string+1) == '6')
7729 bcst_type = BROADCAST_1TO16;
7734 as_bad (_("Unsupported broadcast: `%s'"), saved);
7739 broadcast_op.type = bcst_type;
7740 broadcast_op.operand = this_operand;
7741 i.broadcast = &broadcast_op;
7743 /* Check masking operation. */
7744 else if ((mask = parse_register (op_string, &end_op)) != NULL)
7746 /* k0 can't be used for write mask. */
7747 if (mask->reg_num == 0)
7749 as_bad (_("`%s' can't be used for write mask"),
7756 mask_op.mask = mask;
7757 mask_op.zeroing = 0;
7758 mask_op.operand = this_operand;
7764 goto duplicated_vec_op;
7766 i.mask->mask = mask;
7768 /* Only "{z}" is allowed here. No need to check
7769 zeroing mask explicitly. */
7770 if (i.mask->operand != this_operand)
7772 as_bad (_("invalid write mask `%s'"), saved);
7779 /* Check zeroing-flag for masking operation. */
7780 else if (*op_string == 'z')
7784 mask_op.mask = NULL;
7785 mask_op.zeroing = 1;
7786 mask_op.operand = this_operand;
7791 if (i.mask->zeroing)
7794 as_bad (_("duplicated `%s'"), saved);
7798 i.mask->zeroing = 1;
7800 /* Only "{%k}" is allowed here. No need to check mask
7801 register explicitly. */
7802 if (i.mask->operand != this_operand)
7804 as_bad (_("invalid zeroing-masking `%s'"),
7813 goto unknown_vec_op;
7815 if (*op_string != '}')
7817 as_bad (_("missing `}' in `%s'"), saved);
7824 /* We don't know this one. */
7825 as_bad (_("unknown vector operation: `%s'"), saved);
7833 i386_immediate (char *imm_start)
7835 char *save_input_line_pointer;
7836 char *gotfree_input_line;
7839 i386_operand_type types;
7841 operand_type_set (&types, ~0);
7843 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
7845 as_bad (_("at most %d immediate operands are allowed"),
7846 MAX_IMMEDIATE_OPERANDS);
7850 exp = &im_expressions[i.imm_operands++];
7851 i.op[this_operand].imms = exp;
7853 if (is_space_char (*imm_start))
7856 save_input_line_pointer = input_line_pointer;
7857 input_line_pointer = imm_start;
7859 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
7860 (i.bnd_prefix != NULL
7861 || add_bnd_prefix));
7862 if (gotfree_input_line)
7863 input_line_pointer = gotfree_input_line;
7865 exp_seg = expression (exp);
7869 /* Handle vector operations. */
7870 if (*input_line_pointer == '{')
7872 input_line_pointer = check_VecOperations (input_line_pointer,
7874 if (input_line_pointer == NULL)
7878 if (*input_line_pointer)
7879 as_bad (_("junk `%s' after expression"), input_line_pointer);
7881 input_line_pointer = save_input_line_pointer;
7882 if (gotfree_input_line)
7884 free (gotfree_input_line);
7886 if (exp->X_op == O_constant || exp->X_op == O_register)
7887 exp->X_op = O_illegal;
7890 return i386_finalize_immediate (exp_seg, exp, types, imm_start);
7894 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
7895 i386_operand_type types, const char *imm_start)
7897 if (exp->X_op == O_absent || exp->X_op == O_illegal || exp->X_op == O_big)
7900 as_bad (_("missing or invalid immediate expression `%s'"),
7904 else if (exp->X_op == O_constant)
7906 /* Size it properly later. */
7907 i.types[this_operand].bitfield.imm64 = 1;
7908 /* If not 64bit, sign extend val. */
7909 if (flag_code != CODE_64BIT
7910 && (exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
7912 = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
7914 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7915 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
7916 && exp_seg != absolute_section
7917 && exp_seg != text_section
7918 && exp_seg != data_section
7919 && exp_seg != bss_section
7920 && exp_seg != undefined_section
7921 && !bfd_is_com_section (exp_seg))
7923 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
7927 else if (!intel_syntax && exp->X_op == O_register)
7930 as_bad (_("illegal immediate register operand %s"), imm_start);
7935 /* This is an address. The size of the address will be
7936 determined later, depending on destination register,
7937 suffix, or the default for the section. */
7938 i.types[this_operand].bitfield.imm8 = 1;
7939 i.types[this_operand].bitfield.imm16 = 1;
7940 i.types[this_operand].bitfield.imm32 = 1;
7941 i.types[this_operand].bitfield.imm32s = 1;
7942 i.types[this_operand].bitfield.imm64 = 1;
7943 i.types[this_operand] = operand_type_and (i.types[this_operand],
7951 i386_scale (char *scale)
7954 char *save = input_line_pointer;
7956 input_line_pointer = scale;
7957 val = get_absolute_expression ();
7962 i.log2_scale_factor = 0;
7965 i.log2_scale_factor = 1;
7968 i.log2_scale_factor = 2;
7971 i.log2_scale_factor = 3;
7975 char sep = *input_line_pointer;
7977 *input_line_pointer = '\0';
7978 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
7980 *input_line_pointer = sep;
7981 input_line_pointer = save;
7985 if (i.log2_scale_factor != 0 && i.index_reg == 0)
7987 as_warn (_("scale factor of %d without an index register"),
7988 1 << i.log2_scale_factor);
7989 i.log2_scale_factor = 0;
7991 scale = input_line_pointer;
7992 input_line_pointer = save;
7997 i386_displacement (char *disp_start, char *disp_end)
8001 char *save_input_line_pointer;
8002 char *gotfree_input_line;
8004 i386_operand_type bigdisp, types = anydisp;
8007 if (i.disp_operands == MAX_MEMORY_OPERANDS)
8009 as_bad (_("at most %d displacement operands are allowed"),
8010 MAX_MEMORY_OPERANDS);
8014 operand_type_set (&bigdisp, 0);
8015 if ((i.types[this_operand].bitfield.jumpabsolute)
8016 || (!current_templates->start->opcode_modifier.jump
8017 && !current_templates->start->opcode_modifier.jumpdword))
8019 bigdisp.bitfield.disp32 = 1;
8020 override = (i.prefix[ADDR_PREFIX] != 0);
8021 if (flag_code == CODE_64BIT)
8025 bigdisp.bitfield.disp32s = 1;
8026 bigdisp.bitfield.disp64 = 1;
8029 else if ((flag_code == CODE_16BIT) ^ override)
8031 bigdisp.bitfield.disp32 = 0;
8032 bigdisp.bitfield.disp16 = 1;
8037 /* For PC-relative branches, the width of the displacement
8038 is dependent upon data size, not address size. */
8039 override = (i.prefix[DATA_PREFIX] != 0);
8040 if (flag_code == CODE_64BIT)
8042 if (override || i.suffix == WORD_MNEM_SUFFIX)
8043 bigdisp.bitfield.disp16 = 1;
8046 bigdisp.bitfield.disp32 = 1;
8047 bigdisp.bitfield.disp32s = 1;
8053 override = (i.suffix == (flag_code != CODE_16BIT
8055 : LONG_MNEM_SUFFIX));
8056 bigdisp.bitfield.disp32 = 1;
8057 if ((flag_code == CODE_16BIT) ^ override)
8059 bigdisp.bitfield.disp32 = 0;
8060 bigdisp.bitfield.disp16 = 1;
8064 i.types[this_operand] = operand_type_or (i.types[this_operand],
8067 exp = &disp_expressions[i.disp_operands];
8068 i.op[this_operand].disps = exp;
8070 save_input_line_pointer = input_line_pointer;
8071 input_line_pointer = disp_start;
8072 END_STRING_AND_SAVE (disp_end);
8074 #ifndef GCC_ASM_O_HACK
8075 #define GCC_ASM_O_HACK 0
8078 END_STRING_AND_SAVE (disp_end + 1);
8079 if (i.types[this_operand].bitfield.baseIndex
8080 && displacement_string_end[-1] == '+')
8082 /* This hack is to avoid a warning when using the "o"
8083 constraint within gcc asm statements.
8086 #define _set_tssldt_desc(n,addr,limit,type) \
8087 __asm__ __volatile__ ( \
8089 "movw %w1,2+%0\n\t" \
8091 "movb %b1,4+%0\n\t" \
8092 "movb %4,5+%0\n\t" \
8093 "movb $0,6+%0\n\t" \
8094 "movb %h1,7+%0\n\t" \
8096 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
8098 This works great except that the output assembler ends
8099 up looking a bit weird if it turns out that there is
8100 no offset. You end up producing code that looks like:
8113 So here we provide the missing zero. */
8115 *displacement_string_end = '0';
8118 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL, &types,
8119 (i.bnd_prefix != NULL
8120 || add_bnd_prefix));
8121 if (gotfree_input_line)
8122 input_line_pointer = gotfree_input_line;
8124 exp_seg = expression (exp);
8127 if (*input_line_pointer)
8128 as_bad (_("junk `%s' after expression"), input_line_pointer);
8130 RESTORE_END_STRING (disp_end + 1);
8132 input_line_pointer = save_input_line_pointer;
8133 if (gotfree_input_line)
8135 free (gotfree_input_line);
8137 if (exp->X_op == O_constant || exp->X_op == O_register)
8138 exp->X_op = O_illegal;
8141 ret = i386_finalize_displacement (exp_seg, exp, types, disp_start);
8143 RESTORE_END_STRING (disp_end);
8149 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED, expressionS *exp,
8150 i386_operand_type types, const char *disp_start)
8152 i386_operand_type bigdisp;
8155 /* We do this to make sure that the section symbol is in
8156 the symbol table. We will ultimately change the relocation
8157 to be relative to the beginning of the section. */
8158 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
8159 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
8160 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8162 if (exp->X_op != O_symbol)
8165 if (S_IS_LOCAL (exp->X_add_symbol)
8166 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section
8167 && S_GET_SEGMENT (exp->X_add_symbol) != expr_section)
8168 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
8169 exp->X_op = O_subtract;
8170 exp->X_op_symbol = GOT_symbol;
8171 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
8172 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
8173 else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64)
8174 i.reloc[this_operand] = BFD_RELOC_64;
8176 i.reloc[this_operand] = BFD_RELOC_32;
8179 else if (exp->X_op == O_absent
8180 || exp->X_op == O_illegal
8181 || exp->X_op == O_big)
8184 as_bad (_("missing or invalid displacement expression `%s'"),
8189 else if (flag_code == CODE_64BIT
8190 && !i.prefix[ADDR_PREFIX]
8191 && exp->X_op == O_constant)
8193 /* Since displacement is signed extended to 64bit, don't allow
8194 disp32 and turn off disp32s if they are out of range. */
8195 i.types[this_operand].bitfield.disp32 = 0;
8196 if (!fits_in_signed_long (exp->X_add_number))
8198 i.types[this_operand].bitfield.disp32s = 0;
8199 if (i.types[this_operand].bitfield.baseindex)
8201 as_bad (_("0x%lx out range of signed 32bit displacement"),
8202 (long) exp->X_add_number);
8208 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8209 else if (exp->X_op != O_constant
8210 && OUTPUT_FLAVOR == bfd_target_aout_flavour
8211 && exp_seg != absolute_section
8212 && exp_seg != text_section
8213 && exp_seg != data_section
8214 && exp_seg != bss_section
8215 && exp_seg != undefined_section
8216 && !bfd_is_com_section (exp_seg))
8218 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
8223 /* Check if this is a displacement only operand. */
8224 bigdisp = i.types[this_operand];
8225 bigdisp.bitfield.disp8 = 0;
8226 bigdisp.bitfield.disp16 = 0;
8227 bigdisp.bitfield.disp32 = 0;
8228 bigdisp.bitfield.disp32s = 0;
8229 bigdisp.bitfield.disp64 = 0;
8230 if (operand_type_all_zero (&bigdisp))
8231 i.types[this_operand] = operand_type_and (i.types[this_operand],
8237 /* Make sure the memory operand we've been dealt is valid.
8238 Return 1 on success, 0 on a failure. */
8241 i386_index_check (const char *operand_string)
8243 const char *kind = "base/index";
8244 enum flag_code addr_mode;
8246 if (i.prefix[ADDR_PREFIX])
8247 addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
8250 addr_mode = flag_code;
8252 #if INFER_ADDR_PREFIX
8253 if (i.mem_operands == 0)
8255 /* Infer address prefix from the first memory operand. */
8256 const reg_entry *addr_reg = i.base_reg;
8258 if (addr_reg == NULL)
8259 addr_reg = i.index_reg;
8263 if (addr_reg->reg_num == RegEip
8264 || addr_reg->reg_num == RegEiz
8265 || addr_reg->reg_type.bitfield.reg32)
8266 addr_mode = CODE_32BIT;
8267 else if (flag_code != CODE_64BIT
8268 && addr_reg->reg_type.bitfield.reg16)
8269 addr_mode = CODE_16BIT;
8271 if (addr_mode != flag_code)
8273 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
8275 /* Change the size of any displacement too. At most one
8276 of Disp16 or Disp32 is set.
8277 FIXME. There doesn't seem to be any real need for
8278 separate Disp16 and Disp32 flags. The same goes for
8279 Imm16 and Imm32. Removing them would probably clean
8280 up the code quite a lot. */
8281 if (flag_code != CODE_64BIT
8282 && (i.types[this_operand].bitfield.disp16
8283 || i.types[this_operand].bitfield.disp32))
8284 i.types[this_operand]
8285 = operand_type_xor (i.types[this_operand], disp16_32);
8292 if (current_templates->start->opcode_modifier.isstring
8293 && !current_templates->start->opcode_modifier.immext
8294 && (current_templates->end[-1].opcode_modifier.isstring
8297 /* Memory operands of string insns are special in that they only allow
8298 a single register (rDI, rSI, or rBX) as their memory address. */
8299 const reg_entry *expected_reg;
8300 static const char *di_si[][2] =
8306 static const char *bx[] = { "ebx", "bx", "rbx" };
8308 kind = "string address";
8310 if (current_templates->start->opcode_modifier.w)
8312 i386_operand_type type = current_templates->end[-1].operand_types[0];
8314 if (!type.bitfield.baseindex
8315 || ((!i.mem_operands != !intel_syntax)
8316 && current_templates->end[-1].operand_types[1]
8317 .bitfield.baseindex))
8318 type = current_templates->end[-1].operand_types[1];
8319 expected_reg = hash_find (reg_hash,
8320 di_si[addr_mode][type.bitfield.esseg]);
8324 expected_reg = hash_find (reg_hash, bx[addr_mode]);
8326 if (i.base_reg != expected_reg
8328 || operand_type_check (i.types[this_operand], disp))
8330 /* The second memory operand must have the same size as
8334 && !((addr_mode == CODE_64BIT
8335 && i.base_reg->reg_type.bitfield.reg64)
8336 || (addr_mode == CODE_32BIT
8337 ? i.base_reg->reg_type.bitfield.reg32
8338 : i.base_reg->reg_type.bitfield.reg16)))
8341 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
8343 intel_syntax ? '[' : '(',
8345 expected_reg->reg_name,
8346 intel_syntax ? ']' : ')');
8353 as_bad (_("`%s' is not a valid %s expression"),
8354 operand_string, kind);
8359 if (addr_mode != CODE_16BIT)
8361 /* 32-bit/64-bit checks. */
8363 && (addr_mode == CODE_64BIT
8364 ? !i.base_reg->reg_type.bitfield.reg64
8365 : !i.base_reg->reg_type.bitfield.reg32)
8367 || (i.base_reg->reg_num
8368 != (addr_mode == CODE_64BIT ? RegRip : RegEip))))
8370 && !i.index_reg->reg_type.bitfield.regxmm
8371 && !i.index_reg->reg_type.bitfield.regymm
8372 && !i.index_reg->reg_type.bitfield.regzmm
8373 && ((addr_mode == CODE_64BIT
8374 ? !(i.index_reg->reg_type.bitfield.reg64
8375 || i.index_reg->reg_num == RegRiz)
8376 : !(i.index_reg->reg_type.bitfield.reg32
8377 || i.index_reg->reg_num == RegEiz))
8378 || !i.index_reg->reg_type.bitfield.baseindex)))
8383 /* 16-bit checks. */
8385 && (!i.base_reg->reg_type.bitfield.reg16
8386 || !i.base_reg->reg_type.bitfield.baseindex))
8388 && (!i.index_reg->reg_type.bitfield.reg16
8389 || !i.index_reg->reg_type.bitfield.baseindex
8391 && i.base_reg->reg_num < 6
8392 && i.index_reg->reg_num >= 6
8393 && i.log2_scale_factor == 0))))
8400 /* Handle vector immediates. */
8403 RC_SAE_immediate (const char *imm_start)
8405 unsigned int match_found, j;
8406 const char *pstr = imm_start;
8414 for (j = 0; j < ARRAY_SIZE (RC_NamesTable); j++)
8416 if (!strncmp (pstr, RC_NamesTable[j].name, RC_NamesTable[j].len))
8420 rc_op.type = RC_NamesTable[j].type;
8421 rc_op.operand = this_operand;
8422 i.rounding = &rc_op;
8426 as_bad (_("duplicated `%s'"), imm_start);
8429 pstr += RC_NamesTable[j].len;
8439 as_bad (_("Missing '}': '%s'"), imm_start);
8442 /* RC/SAE immediate string should contain nothing more. */;
8445 as_bad (_("Junk after '}': '%s'"), imm_start);
8449 exp = &im_expressions[i.imm_operands++];
8450 i.op[this_operand].imms = exp;
8452 exp->X_op = O_constant;
8453 exp->X_add_number = 0;
8454 exp->X_add_symbol = (symbolS *) 0;
8455 exp->X_op_symbol = (symbolS *) 0;
8457 i.types[this_operand].bitfield.imm8 = 1;
8461 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
8465 i386_att_operand (char *operand_string)
8469 char *op_string = operand_string;
8471 if (is_space_char (*op_string))
8474 /* We check for an absolute prefix (differentiating,
8475 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
8476 if (*op_string == ABSOLUTE_PREFIX)
8479 if (is_space_char (*op_string))
8481 i.types[this_operand].bitfield.jumpabsolute = 1;
8484 /* Check if operand is a register. */
8485 if ((r = parse_register (op_string, &end_op)) != NULL)
8487 i386_operand_type temp;
8489 /* Check for a segment override by searching for ':' after a
8490 segment register. */
8492 if (is_space_char (*op_string))
8494 if (*op_string == ':'
8495 && (r->reg_type.bitfield.sreg2
8496 || r->reg_type.bitfield.sreg3))
8501 i.seg[i.mem_operands] = &es;
8504 i.seg[i.mem_operands] = &cs;
8507 i.seg[i.mem_operands] = &ss;
8510 i.seg[i.mem_operands] = &ds;
8513 i.seg[i.mem_operands] = &fs;
8516 i.seg[i.mem_operands] = &gs;
8520 /* Skip the ':' and whitespace. */
8522 if (is_space_char (*op_string))
8525 if (!is_digit_char (*op_string)
8526 && !is_identifier_char (*op_string)
8527 && *op_string != '('
8528 && *op_string != ABSOLUTE_PREFIX)
8530 as_bad (_("bad memory operand `%s'"), op_string);
8533 /* Handle case of %es:*foo. */
8534 if (*op_string == ABSOLUTE_PREFIX)
8537 if (is_space_char (*op_string))
8539 i.types[this_operand].bitfield.jumpabsolute = 1;
8541 goto do_memory_reference;
8544 /* Handle vector operations. */
8545 if (*op_string == '{')
8547 op_string = check_VecOperations (op_string, NULL);
8548 if (op_string == NULL)
8554 as_bad (_("junk `%s' after register"), op_string);
8558 temp.bitfield.baseindex = 0;
8559 i.types[this_operand] = operand_type_or (i.types[this_operand],
8561 i.types[this_operand].bitfield.unspecified = 0;
8562 i.op[this_operand].regs = r;
8565 else if (*op_string == REGISTER_PREFIX)
8567 as_bad (_("bad register name `%s'"), op_string);
8570 else if (*op_string == IMMEDIATE_PREFIX)
8573 if (i.types[this_operand].bitfield.jumpabsolute)
8575 as_bad (_("immediate operand illegal with absolute jump"));
8578 if (!i386_immediate (op_string))
8581 else if (RC_SAE_immediate (operand_string))
8583 /* If it is a RC or SAE immediate, do nothing. */
8586 else if (is_digit_char (*op_string)
8587 || is_identifier_char (*op_string)
8588 || *op_string == '(')
8590 /* This is a memory reference of some sort. */
8593 /* Start and end of displacement string expression (if found). */
8594 char *displacement_string_start;
8595 char *displacement_string_end;
8598 do_memory_reference:
8599 if ((i.mem_operands == 1
8600 && !current_templates->start->opcode_modifier.isstring)
8601 || i.mem_operands == 2)
8603 as_bad (_("too many memory references for `%s'"),
8604 current_templates->start->name);
8608 /* Check for base index form. We detect the base index form by
8609 looking for an ')' at the end of the operand, searching
8610 for the '(' matching it, and finding a REGISTER_PREFIX or ','
8612 base_string = op_string + strlen (op_string);
8614 /* Handle vector operations. */
8615 vop_start = strchr (op_string, '{');
8616 if (vop_start && vop_start < base_string)
8618 if (check_VecOperations (vop_start, base_string) == NULL)
8620 base_string = vop_start;
8624 if (is_space_char (*base_string))
8627 /* If we only have a displacement, set-up for it to be parsed later. */
8628 displacement_string_start = op_string;
8629 displacement_string_end = base_string + 1;
8631 if (*base_string == ')')
8634 unsigned int parens_balanced = 1;
8635 /* We've already checked that the number of left & right ()'s are
8636 equal, so this loop will not be infinite. */
8640 if (*base_string == ')')
8642 if (*base_string == '(')
8645 while (parens_balanced);
8647 temp_string = base_string;
8649 /* Skip past '(' and whitespace. */
8651 if (is_space_char (*base_string))
8654 if (*base_string == ','
8655 || ((i.base_reg = parse_register (base_string, &end_op))
8658 displacement_string_end = temp_string;
8660 i.types[this_operand].bitfield.baseindex = 1;
8664 base_string = end_op;
8665 if (is_space_char (*base_string))
8669 /* There may be an index reg or scale factor here. */
8670 if (*base_string == ',')
8673 if (is_space_char (*base_string))
8676 if ((i.index_reg = parse_register (base_string, &end_op))
8679 base_string = end_op;
8680 if (is_space_char (*base_string))
8682 if (*base_string == ',')
8685 if (is_space_char (*base_string))
8688 else if (*base_string != ')')
8690 as_bad (_("expecting `,' or `)' "
8691 "after index register in `%s'"),
8696 else if (*base_string == REGISTER_PREFIX)
8698 end_op = strchr (base_string, ',');
8701 as_bad (_("bad register name `%s'"), base_string);
8705 /* Check for scale factor. */
8706 if (*base_string != ')')
8708 char *end_scale = i386_scale (base_string);
8713 base_string = end_scale;
8714 if (is_space_char (*base_string))
8716 if (*base_string != ')')
8718 as_bad (_("expecting `)' "
8719 "after scale factor in `%s'"),
8724 else if (!i.index_reg)
8726 as_bad (_("expecting index register or scale factor "
8727 "after `,'; got '%c'"),
8732 else if (*base_string != ')')
8734 as_bad (_("expecting `,' or `)' "
8735 "after base register in `%s'"),
8740 else if (*base_string == REGISTER_PREFIX)
8742 end_op = strchr (base_string, ',');
8745 as_bad (_("bad register name `%s'"), base_string);
8750 /* If there's an expression beginning the operand, parse it,
8751 assuming displacement_string_start and
8752 displacement_string_end are meaningful. */
8753 if (displacement_string_start != displacement_string_end)
8755 if (!i386_displacement (displacement_string_start,
8756 displacement_string_end))
8760 /* Special case for (%dx) while doing input/output op. */
8762 && operand_type_equal (&i.base_reg->reg_type,
8763 ®16_inoutportreg)
8765 && i.log2_scale_factor == 0
8766 && i.seg[i.mem_operands] == 0
8767 && !operand_type_check (i.types[this_operand], disp))
8769 i.types[this_operand] = inoutportreg;
8773 if (i386_index_check (operand_string) == 0)
8775 i.types[this_operand].bitfield.mem = 1;
8780 /* It's not a memory operand; argh! */
8781 as_bad (_("invalid char %s beginning operand %d `%s'"),
8782 output_invalid (*op_string),
8787 return 1; /* Normal return. */
8790 /* Calculate the maximum variable size (i.e., excluding fr_fix)
8791 that an rs_machine_dependent frag may reach. */
8794 i386_frag_max_var (fragS *frag)
8796 /* The only relaxable frags are for jumps.
8797 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
8798 gas_assert (frag->fr_type == rs_machine_dependent);
8799 return TYPE_FROM_RELAX_STATE (frag->fr_subtype) == UNCOND_JUMP ? 4 : 5;
8802 /* md_estimate_size_before_relax()
8804 Called just before relax() for rs_machine_dependent frags. The x86
8805 assembler uses these frags to handle variable size jump
8808 Any symbol that is now undefined will not become defined.
8809 Return the correct fr_subtype in the frag.
8810 Return the initial "guess for variable size of frag" to caller.
8811 The guess is actually the growth beyond the fixed part. Whatever
8812 we do to grow the fixed or variable part contributes to our
8816 md_estimate_size_before_relax (fragS *fragP, segT segment)
8818 /* We've already got fragP->fr_subtype right; all we have to do is
8819 check for un-relaxable symbols. On an ELF system, we can't relax
8820 an externally visible symbol, because it may be overridden by a
8822 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
8823 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8825 && (S_IS_EXTERNAL (fragP->fr_symbol)
8826 || S_IS_WEAK (fragP->fr_symbol)
8827 || ((symbol_get_bfdsym (fragP->fr_symbol)->flags
8828 & BSF_GNU_INDIRECT_FUNCTION))))
8830 #if defined (OBJ_COFF) && defined (TE_PE)
8831 || (OUTPUT_FLAVOR == bfd_target_coff_flavour
8832 && S_IS_WEAK (fragP->fr_symbol))
8836 /* Symbol is undefined in this segment, or we need to keep a
8837 reloc so that weak symbols can be overridden. */
8838 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
8839 enum bfd_reloc_code_real reloc_type;
8840 unsigned char *opcode;
8843 if (fragP->fr_var != NO_RELOC)
8844 reloc_type = (enum bfd_reloc_code_real) fragP->fr_var;
8846 reloc_type = BFD_RELOC_16_PCREL;
8848 reloc_type = BFD_RELOC_32_PCREL;
8850 old_fr_fix = fragP->fr_fix;
8851 opcode = (unsigned char *) fragP->fr_opcode;
8853 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
8856 /* Make jmp (0xeb) a (d)word displacement jump. */
8858 fragP->fr_fix += size;
8859 fix_new (fragP, old_fr_fix, size,
8861 fragP->fr_offset, 1,
8867 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
8869 /* Negate the condition, and branch past an
8870 unconditional jump. */
8873 /* Insert an unconditional jump. */
8875 /* We added two extra opcode bytes, and have a two byte
8877 fragP->fr_fix += 2 + 2;
8878 fix_new (fragP, old_fr_fix + 2, 2,
8880 fragP->fr_offset, 1,
8887 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
8892 fixP = fix_new (fragP, old_fr_fix, 1,
8894 fragP->fr_offset, 1,
8896 fixP->fx_signed = 1;
8900 /* This changes the byte-displacement jump 0x7N
8901 to the (d)word-displacement jump 0x0f,0x8N. */
8902 opcode[1] = opcode[0] + 0x10;
8903 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8904 /* We've added an opcode byte. */
8905 fragP->fr_fix += 1 + size;
8906 fix_new (fragP, old_fr_fix + 1, size,
8908 fragP->fr_offset, 1,
8913 BAD_CASE (fragP->fr_subtype);
8917 return fragP->fr_fix - old_fr_fix;
8920 /* Guess size depending on current relax state. Initially the relax
8921 state will correspond to a short jump and we return 1, because
8922 the variable part of the frag (the branch offset) is one byte
8923 long. However, we can relax a section more than once and in that
8924 case we must either set fr_subtype back to the unrelaxed state,
8925 or return the value for the appropriate branch. */
8926 return md_relax_table[fragP->fr_subtype].rlx_length;
8929 /* Called after relax() is finished.
8931 In: Address of frag.
8932 fr_type == rs_machine_dependent.
8933 fr_subtype is what the address relaxed to.
8935 Out: Any fixSs and constants are set up.
8936 Caller will turn frag into a ".space 0". */
8939 md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec ATTRIBUTE_UNUSED,
8942 unsigned char *opcode;
8943 unsigned char *where_to_put_displacement = NULL;
8944 offsetT target_address;
8945 offsetT opcode_address;
8946 unsigned int extension = 0;
8947 offsetT displacement_from_opcode_start;
8949 opcode = (unsigned char *) fragP->fr_opcode;
8951 /* Address we want to reach in file space. */
8952 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
8954 /* Address opcode resides at in file space. */
8955 opcode_address = fragP->fr_address + fragP->fr_fix;
8957 /* Displacement from opcode start to fill into instruction. */
8958 displacement_from_opcode_start = target_address - opcode_address;
8960 if ((fragP->fr_subtype & BIG) == 0)
8962 /* Don't have to change opcode. */
8963 extension = 1; /* 1 opcode + 1 displacement */
8964 where_to_put_displacement = &opcode[1];
8968 if (no_cond_jump_promotion
8969 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
8970 as_warn_where (fragP->fr_file, fragP->fr_line,
8971 _("long jump required"));
8973 switch (fragP->fr_subtype)
8975 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
8976 extension = 4; /* 1 opcode + 4 displacement */
8978 where_to_put_displacement = &opcode[1];
8981 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
8982 extension = 2; /* 1 opcode + 2 displacement */
8984 where_to_put_displacement = &opcode[1];
8987 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
8988 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
8989 extension = 5; /* 2 opcode + 4 displacement */
8990 opcode[1] = opcode[0] + 0x10;
8991 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8992 where_to_put_displacement = &opcode[2];
8995 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
8996 extension = 3; /* 2 opcode + 2 displacement */
8997 opcode[1] = opcode[0] + 0x10;
8998 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
8999 where_to_put_displacement = &opcode[2];
9002 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
9007 where_to_put_displacement = &opcode[3];
9011 BAD_CASE (fragP->fr_subtype);
9016 /* If size if less then four we are sure that the operand fits,
9017 but if it's 4, then it could be that the displacement is larger
9019 if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype) == 4
9021 && ((addressT) (displacement_from_opcode_start - extension
9022 + ((addressT) 1 << 31))
9023 > (((addressT) 2 << 31) - 1)))
9025 as_bad_where (fragP->fr_file, fragP->fr_line,
9026 _("jump target out of range"));
9027 /* Make us emit 0. */
9028 displacement_from_opcode_start = extension;
9030 /* Now put displacement after opcode. */
9031 md_number_to_chars ((char *) where_to_put_displacement,
9032 (valueT) (displacement_from_opcode_start - extension),
9033 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
9034 fragP->fr_fix += extension;
9037 /* Apply a fixup (fixP) to segment data, once it has been determined
9038 by our caller that we have all the info we need to fix it up.
9040 Parameter valP is the pointer to the value of the bits.
9042 On the 386, immediates, displacements, and data pointers are all in
9043 the same (little-endian) format, so we don't need to care about which
9047 md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
9049 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
9050 valueT value = *valP;
9052 #if !defined (TE_Mach)
9055 switch (fixP->fx_r_type)
9061 fixP->fx_r_type = BFD_RELOC_64_PCREL;
9064 case BFD_RELOC_X86_64_32S:
9065 fixP->fx_r_type = BFD_RELOC_32_PCREL;
9068 fixP->fx_r_type = BFD_RELOC_16_PCREL;
9071 fixP->fx_r_type = BFD_RELOC_8_PCREL;
9076 if (fixP->fx_addsy != NULL
9077 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
9078 || fixP->fx_r_type == BFD_RELOC_64_PCREL
9079 || fixP->fx_r_type == BFD_RELOC_16_PCREL
9080 || fixP->fx_r_type == BFD_RELOC_8_PCREL
9081 || fixP->fx_r_type == BFD_RELOC_X86_64_PC32_BND)
9082 && !use_rela_relocations)
9084 /* This is a hack. There should be a better way to handle this.
9085 This covers for the fact that bfd_install_relocation will
9086 subtract the current location (for partial_inplace, PC relative
9087 relocations); see more below. */
9091 || OUTPUT_FLAVOR == bfd_target_coff_flavour
9094 value += fixP->fx_where + fixP->fx_frag->fr_address;
9096 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9099 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
9102 || (symbol_section_p (fixP->fx_addsy)
9103 && sym_seg != absolute_section))
9104 && !generic_force_reloc (fixP))
9106 /* Yes, we add the values in twice. This is because
9107 bfd_install_relocation subtracts them out again. I think
9108 bfd_install_relocation is broken, but I don't dare change
9110 value += fixP->fx_where + fixP->fx_frag->fr_address;
9114 #if defined (OBJ_COFF) && defined (TE_PE)
9115 /* For some reason, the PE format does not store a
9116 section address offset for a PC relative symbol. */
9117 if (S_GET_SEGMENT (fixP->fx_addsy) != seg
9118 || S_IS_WEAK (fixP->fx_addsy))
9119 value += md_pcrel_from (fixP);
9122 #if defined (OBJ_COFF) && defined (TE_PE)
9123 if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9125 value -= S_GET_VALUE (fixP->fx_addsy);
9129 /* Fix a few things - the dynamic linker expects certain values here,
9130 and we must not disappoint it. */
9131 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9132 if (IS_ELF && fixP->fx_addsy)
9133 switch (fixP->fx_r_type)
9135 case BFD_RELOC_386_PLT32:
9136 case BFD_RELOC_X86_64_PLT32:
9137 case BFD_RELOC_X86_64_PLT32_BND:
9138 /* Make the jump instruction point to the address of the operand. At
9139 runtime we merely add the offset to the actual PLT entry. */
9143 case BFD_RELOC_386_TLS_GD:
9144 case BFD_RELOC_386_TLS_LDM:
9145 case BFD_RELOC_386_TLS_IE_32:
9146 case BFD_RELOC_386_TLS_IE:
9147 case BFD_RELOC_386_TLS_GOTIE:
9148 case BFD_RELOC_386_TLS_GOTDESC:
9149 case BFD_RELOC_X86_64_TLSGD:
9150 case BFD_RELOC_X86_64_TLSLD:
9151 case BFD_RELOC_X86_64_GOTTPOFF:
9152 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
9153 value = 0; /* Fully resolved at runtime. No addend. */
9155 case BFD_RELOC_386_TLS_LE:
9156 case BFD_RELOC_386_TLS_LDO_32:
9157 case BFD_RELOC_386_TLS_LE_32:
9158 case BFD_RELOC_X86_64_DTPOFF32:
9159 case BFD_RELOC_X86_64_DTPOFF64:
9160 case BFD_RELOC_X86_64_TPOFF32:
9161 case BFD_RELOC_X86_64_TPOFF64:
9162 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9165 case BFD_RELOC_386_TLS_DESC_CALL:
9166 case BFD_RELOC_X86_64_TLSDESC_CALL:
9167 value = 0; /* Fully resolved at runtime. No addend. */
9168 S_SET_THREAD_LOCAL (fixP->fx_addsy);
9172 case BFD_RELOC_386_GOT32:
9173 case BFD_RELOC_X86_64_GOT32:
9174 value = 0; /* Fully resolved at runtime. No addend. */
9177 case BFD_RELOC_VTABLE_INHERIT:
9178 case BFD_RELOC_VTABLE_ENTRY:
9185 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
9187 #endif /* !defined (TE_Mach) */
9189 /* Are we finished with this relocation now? */
9190 if (fixP->fx_addsy == NULL)
9192 #if defined (OBJ_COFF) && defined (TE_PE)
9193 else if (fixP->fx_addsy != NULL && S_IS_WEAK (fixP->fx_addsy))
9196 /* Remember value for tc_gen_reloc. */
9197 fixP->fx_addnumber = value;
9198 /* Clear out the frag for now. */
9202 else if (use_rela_relocations)
9204 fixP->fx_no_overflow = 1;
9205 /* Remember value for tc_gen_reloc. */
9206 fixP->fx_addnumber = value;
9210 md_number_to_chars (p, value, fixP->fx_size);
9214 md_atof (int type, char *litP, int *sizeP)
9216 /* This outputs the LITTLENUMs in REVERSE order;
9217 in accord with the bigendian 386. */
9218 return ieee_md_atof (type, litP, sizeP, FALSE);
9221 static char output_invalid_buf[sizeof (unsigned char) * 2 + 6];
9224 output_invalid (int c)
9227 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9230 snprintf (output_invalid_buf, sizeof (output_invalid_buf),
9231 "(0x%x)", (unsigned char) c);
9232 return output_invalid_buf;
9235 /* REG_STRING starts *before* REGISTER_PREFIX. */
9237 static const reg_entry *
9238 parse_real_register (char *reg_string, char **end_op)
9240 char *s = reg_string;
9242 char reg_name_given[MAX_REG_NAME_SIZE + 1];
9245 /* Skip possible REGISTER_PREFIX and possible whitespace. */
9246 if (*s == REGISTER_PREFIX)
9249 if (is_space_char (*s))
9253 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
9255 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
9256 return (const reg_entry *) NULL;
9260 /* For naked regs, make sure that we are not dealing with an identifier.
9261 This prevents confusing an identifier like `eax_var' with register
9263 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
9264 return (const reg_entry *) NULL;
9268 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
9270 /* Handle floating point regs, allowing spaces in the (i) part. */
9271 if (r == i386_regtab /* %st is first entry of table */)
9273 if (is_space_char (*s))
9278 if (is_space_char (*s))
9280 if (*s >= '0' && *s <= '7')
9284 if (is_space_char (*s))
9289 r = (const reg_entry *) hash_find (reg_hash, "st(0)");
9294 /* We have "%st(" then garbage. */
9295 return (const reg_entry *) NULL;
9299 if (r == NULL || allow_pseudo_reg)
9302 if (operand_type_all_zero (&r->reg_type))
9303 return (const reg_entry *) NULL;
9305 if ((r->reg_type.bitfield.reg32
9306 || r->reg_type.bitfield.sreg3
9307 || r->reg_type.bitfield.control
9308 || r->reg_type.bitfield.debug
9309 || r->reg_type.bitfield.test)
9310 && !cpu_arch_flags.bitfield.cpui386)
9311 return (const reg_entry *) NULL;
9313 if (r->reg_type.bitfield.floatreg
9314 && !cpu_arch_flags.bitfield.cpu8087
9315 && !cpu_arch_flags.bitfield.cpu287
9316 && !cpu_arch_flags.bitfield.cpu387)
9317 return (const reg_entry *) NULL;
9319 if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
9320 return (const reg_entry *) NULL;
9322 if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
9323 return (const reg_entry *) NULL;
9325 if (r->reg_type.bitfield.regymm && !cpu_arch_flags.bitfield.cpuavx)
9326 return (const reg_entry *) NULL;
9328 if ((r->reg_type.bitfield.regzmm || r->reg_type.bitfield.regmask)
9329 && !cpu_arch_flags.bitfield.cpuavx512f)
9330 return (const reg_entry *) NULL;
9332 /* Don't allow fake index register unless allow_index_reg isn't 0. */
9333 if (!allow_index_reg
9334 && (r->reg_num == RegEiz || r->reg_num == RegRiz))
9335 return (const reg_entry *) NULL;
9337 /* Upper 16 vector register is only available with VREX in 64bit
9339 if ((r->reg_flags & RegVRex))
9341 if (!cpu_arch_flags.bitfield.cpuvrex
9342 || flag_code != CODE_64BIT)
9343 return (const reg_entry *) NULL;
9348 if (((r->reg_flags & (RegRex64 | RegRex))
9349 || r->reg_type.bitfield.reg64)
9350 && (!cpu_arch_flags.bitfield.cpulm
9351 || !operand_type_equal (&r->reg_type, &control))
9352 && flag_code != CODE_64BIT)
9353 return (const reg_entry *) NULL;
9355 if (r->reg_type.bitfield.sreg3 && r->reg_num == RegFlat && !intel_syntax)
9356 return (const reg_entry *) NULL;
9361 /* REG_STRING starts *before* REGISTER_PREFIX. */
9363 static const reg_entry *
9364 parse_register (char *reg_string, char **end_op)
9368 if (*reg_string == REGISTER_PREFIX || allow_naked_reg)
9369 r = parse_real_register (reg_string, end_op);
9374 char *save = input_line_pointer;
9378 input_line_pointer = reg_string;
9379 c = get_symbol_end ();
9380 symbolP = symbol_find (reg_string);
9381 if (symbolP && S_GET_SEGMENT (symbolP) == reg_section)
9383 const expressionS *e = symbol_get_value_expression (symbolP);
9385 know (e->X_op == O_register);
9386 know (e->X_add_number >= 0
9387 && (valueT) e->X_add_number < i386_regtab_size);
9388 r = i386_regtab + e->X_add_number;
9389 *end_op = input_line_pointer;
9391 *input_line_pointer = c;
9392 input_line_pointer = save;
9398 i386_parse_name (char *name, expressionS *e, char *nextcharP)
9401 char *end = input_line_pointer;
9404 r = parse_register (name, &input_line_pointer);
9405 if (r && end <= input_line_pointer)
9407 *nextcharP = *input_line_pointer;
9408 *input_line_pointer = 0;
9409 e->X_op = O_register;
9410 e->X_add_number = r - i386_regtab;
9413 input_line_pointer = end;
9415 return intel_syntax ? i386_intel_parse_name (name, e) : 0;
9419 md_operand (expressionS *e)
9424 switch (*input_line_pointer)
9426 case REGISTER_PREFIX:
9427 r = parse_real_register (input_line_pointer, &end);
9430 e->X_op = O_register;
9431 e->X_add_number = r - i386_regtab;
9432 input_line_pointer = end;
9437 gas_assert (intel_syntax);
9438 end = input_line_pointer++;
9440 if (*input_line_pointer == ']')
9442 ++input_line_pointer;
9443 e->X_op_symbol = make_expr_symbol (e);
9444 e->X_add_symbol = NULL;
9445 e->X_add_number = 0;
9451 input_line_pointer = end;
9458 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9459 const char *md_shortopts = "kVQ:sqn";
9461 const char *md_shortopts = "qn";
9464 #define OPTION_32 (OPTION_MD_BASE + 0)
9465 #define OPTION_64 (OPTION_MD_BASE + 1)
9466 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
9467 #define OPTION_MARCH (OPTION_MD_BASE + 3)
9468 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
9469 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
9470 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
9471 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
9472 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
9473 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
9474 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
9475 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
9476 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
9477 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
9478 #define OPTION_X32 (OPTION_MD_BASE + 14)
9479 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
9480 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
9481 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
9483 struct option md_longopts[] =
9485 {"32", no_argument, NULL, OPTION_32},
9486 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9487 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9488 {"64", no_argument, NULL, OPTION_64},
9490 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9491 {"x32", no_argument, NULL, OPTION_X32},
9493 {"divide", no_argument, NULL, OPTION_DIVIDE},
9494 {"march", required_argument, NULL, OPTION_MARCH},
9495 {"mtune", required_argument, NULL, OPTION_MTUNE},
9496 {"mmnemonic", required_argument, NULL, OPTION_MMNEMONIC},
9497 {"msyntax", required_argument, NULL, OPTION_MSYNTAX},
9498 {"mindex-reg", no_argument, NULL, OPTION_MINDEX_REG},
9499 {"mnaked-reg", no_argument, NULL, OPTION_MNAKED_REG},
9500 {"mold-gcc", no_argument, NULL, OPTION_MOLD_GCC},
9501 {"msse2avx", no_argument, NULL, OPTION_MSSE2AVX},
9502 {"msse-check", required_argument, NULL, OPTION_MSSE_CHECK},
9503 {"moperand-check", required_argument, NULL, OPTION_MOPERAND_CHECK},
9504 {"mavxscalar", required_argument, NULL, OPTION_MAVXSCALAR},
9505 {"madd-bnd-prefix", no_argument, NULL, OPTION_MADD_BND_PREFIX},
9506 {"mevexlig", required_argument, NULL, OPTION_MEVEXLIG},
9507 {"mevexwig", required_argument, NULL, OPTION_MEVEXWIG},
9508 {NULL, no_argument, NULL, 0}
9510 size_t md_longopts_size = sizeof (md_longopts);
9513 md_parse_option (int c, char *arg)
9521 optimize_align_code = 0;
9528 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9529 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
9530 should be emitted or not. FIXME: Not implemented. */
9534 /* -V: SVR4 argument to print version ID. */
9536 print_version_id ();
9539 /* -k: Ignore for FreeBSD compatibility. */
9544 /* -s: On i386 Solaris, this tells the native assembler to use
9545 .stab instead of .stab.excl. We always use .stab anyhow. */
9548 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9549 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9552 const char **list, **l;
9554 list = bfd_target_list ();
9555 for (l = list; *l != NULL; l++)
9556 if (CONST_STRNEQ (*l, "elf64-x86-64")
9557 || strcmp (*l, "coff-x86-64") == 0
9558 || strcmp (*l, "pe-x86-64") == 0
9559 || strcmp (*l, "pei-x86-64") == 0
9560 || strcmp (*l, "mach-o-x86-64") == 0)
9562 default_arch = "x86_64";
9566 as_fatal (_("no compiled in support for x86_64"));
9572 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9576 const char **list, **l;
9578 list = bfd_target_list ();
9579 for (l = list; *l != NULL; l++)
9580 if (CONST_STRNEQ (*l, "elf32-x86-64"))
9582 default_arch = "x86_64:32";
9586 as_fatal (_("no compiled in support for 32bit x86_64"));
9590 as_fatal (_("32bit x86_64 is only supported for ELF"));
9595 default_arch = "i386";
9599 #ifdef SVR4_COMMENT_CHARS
9604 n = (char *) xmalloc (strlen (i386_comment_chars) + 1);
9606 for (s = i386_comment_chars; *s != '\0'; s++)
9610 i386_comment_chars = n;
9616 arch = xstrdup (arg);
9620 as_fatal (_("invalid -march= option: `%s'"), arg);
9621 next = strchr (arch, '+');
9624 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9626 if (strcmp (arch, cpu_arch [j].name) == 0)
9629 if (! cpu_arch[j].flags.bitfield.cpui386)
9632 cpu_arch_name = cpu_arch[j].name;
9633 cpu_sub_arch_name = NULL;
9634 cpu_arch_flags = cpu_arch[j].flags;
9635 cpu_arch_isa = cpu_arch[j].type;
9636 cpu_arch_isa_flags = cpu_arch[j].flags;
9637 if (!cpu_arch_tune_set)
9639 cpu_arch_tune = cpu_arch_isa;
9640 cpu_arch_tune_flags = cpu_arch_isa_flags;
9644 else if (*cpu_arch [j].name == '.'
9645 && strcmp (arch, cpu_arch [j].name + 1) == 0)
9647 /* ISA entension. */
9648 i386_cpu_flags flags;
9650 if (!cpu_arch[j].negated)
9651 flags = cpu_flags_or (cpu_arch_flags,
9654 flags = cpu_flags_and_not (cpu_arch_flags,
9656 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
9658 if (cpu_sub_arch_name)
9660 char *name = cpu_sub_arch_name;
9661 cpu_sub_arch_name = concat (name,
9663 (const char *) NULL);
9667 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
9668 cpu_arch_flags = flags;
9669 cpu_arch_isa_flags = flags;
9675 if (j >= ARRAY_SIZE (cpu_arch))
9676 as_fatal (_("invalid -march= option: `%s'"), arg);
9680 while (next != NULL );
9685 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9686 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9688 if (strcmp (arg, cpu_arch [j].name) == 0)
9690 cpu_arch_tune_set = 1;
9691 cpu_arch_tune = cpu_arch [j].type;
9692 cpu_arch_tune_flags = cpu_arch[j].flags;
9696 if (j >= ARRAY_SIZE (cpu_arch))
9697 as_fatal (_("invalid -mtune= option: `%s'"), arg);
9700 case OPTION_MMNEMONIC:
9701 if (strcasecmp (arg, "att") == 0)
9703 else if (strcasecmp (arg, "intel") == 0)
9706 as_fatal (_("invalid -mmnemonic= option: `%s'"), arg);
9709 case OPTION_MSYNTAX:
9710 if (strcasecmp (arg, "att") == 0)
9712 else if (strcasecmp (arg, "intel") == 0)
9715 as_fatal (_("invalid -msyntax= option: `%s'"), arg);
9718 case OPTION_MINDEX_REG:
9719 allow_index_reg = 1;
9722 case OPTION_MNAKED_REG:
9723 allow_naked_reg = 1;
9726 case OPTION_MOLD_GCC:
9730 case OPTION_MSSE2AVX:
9734 case OPTION_MSSE_CHECK:
9735 if (strcasecmp (arg, "error") == 0)
9736 sse_check = check_error;
9737 else if (strcasecmp (arg, "warning") == 0)
9738 sse_check = check_warning;
9739 else if (strcasecmp (arg, "none") == 0)
9740 sse_check = check_none;
9742 as_fatal (_("invalid -msse-check= option: `%s'"), arg);
9745 case OPTION_MOPERAND_CHECK:
9746 if (strcasecmp (arg, "error") == 0)
9747 operand_check = check_error;
9748 else if (strcasecmp (arg, "warning") == 0)
9749 operand_check = check_warning;
9750 else if (strcasecmp (arg, "none") == 0)
9751 operand_check = check_none;
9753 as_fatal (_("invalid -moperand-check= option: `%s'"), arg);
9756 case OPTION_MAVXSCALAR:
9757 if (strcasecmp (arg, "128") == 0)
9759 else if (strcasecmp (arg, "256") == 0)
9762 as_fatal (_("invalid -mavxscalar= option: `%s'"), arg);
9765 case OPTION_MADD_BND_PREFIX:
9769 case OPTION_MEVEXLIG:
9770 if (strcmp (arg, "128") == 0)
9772 else if (strcmp (arg, "256") == 0)
9774 else if (strcmp (arg, "512") == 0)
9777 as_fatal (_("invalid -mevexlig= option: `%s'"), arg);
9780 case OPTION_MEVEXWIG:
9781 if (strcmp (arg, "0") == 0)
9783 else if (strcmp (arg, "1") == 0)
9786 as_fatal (_("invalid -mevexwig= option: `%s'"), arg);
9795 #define MESSAGE_TEMPLATE \
9799 show_arch (FILE *stream, int ext, int check)
9801 static char message[] = MESSAGE_TEMPLATE;
9802 char *start = message + 27;
9804 int size = sizeof (MESSAGE_TEMPLATE);
9811 left = size - (start - message);
9812 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
9814 /* Should it be skipped? */
9815 if (cpu_arch [j].skip)
9818 name = cpu_arch [j].name;
9819 len = cpu_arch [j].len;
9822 /* It is an extension. Skip if we aren't asked to show it. */
9833 /* It is an processor. Skip if we show only extension. */
9836 else if (check && ! cpu_arch[j].flags.bitfield.cpui386)
9838 /* It is an impossible processor - skip. */
9842 /* Reserve 2 spaces for ", " or ",\0" */
9845 /* Check if there is any room. */
9853 p = mempcpy (p, name, len);
9857 /* Output the current message now and start a new one. */
9860 fprintf (stream, "%s\n", message);
9862 left = size - (start - message) - len - 2;
9864 gas_assert (left >= 0);
9866 p = mempcpy (p, name, len);
9871 fprintf (stream, "%s\n", message);
9875 md_show_usage (FILE *stream)
9877 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9878 fprintf (stream, _("\
9880 -V print assembler version number\n\
9883 fprintf (stream, _("\
9884 -n Do not optimize code alignment\n\
9885 -q quieten some warnings\n"));
9886 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9887 fprintf (stream, _("\
9890 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9891 || defined (TE_PE) || defined (TE_PEP))
9892 fprintf (stream, _("\
9893 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
9895 #ifdef SVR4_COMMENT_CHARS
9896 fprintf (stream, _("\
9897 --divide do not treat `/' as a comment character\n"));
9899 fprintf (stream, _("\
9900 --divide ignored\n"));
9902 fprintf (stream, _("\
9903 -march=CPU[,+EXTENSION...]\n\
9904 generate code for CPU and EXTENSION, CPU is one of:\n"));
9905 show_arch (stream, 0, 1);
9906 fprintf (stream, _("\
9907 EXTENSION is combination of:\n"));
9908 show_arch (stream, 1, 0);
9909 fprintf (stream, _("\
9910 -mtune=CPU optimize for CPU, CPU is one of:\n"));
9911 show_arch (stream, 0, 0);
9912 fprintf (stream, _("\
9913 -msse2avx encode SSE instructions with VEX prefix\n"));
9914 fprintf (stream, _("\
9915 -msse-check=[none|error|warning]\n\
9916 check SSE instructions\n"));
9917 fprintf (stream, _("\
9918 -moperand-check=[none|error|warning]\n\
9919 check operand combinations for validity\n"));
9920 fprintf (stream, _("\
9921 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
9923 fprintf (stream, _("\
9924 -mevexlig=[128|256|512] encode scalar EVEX instructions with specific vector\n\
9926 fprintf (stream, _("\
9927 -mevexwig=[0|1] encode EVEX instructions with specific EVEX.W value\n\
9928 for EVEX.W bit ignored instructions\n"));
9929 fprintf (stream, _("\
9930 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
9931 fprintf (stream, _("\
9932 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
9933 fprintf (stream, _("\
9934 -mindex-reg support pseudo index registers\n"));
9935 fprintf (stream, _("\
9936 -mnaked-reg don't require `%%' prefix for registers\n"));
9937 fprintf (stream, _("\
9938 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
9939 fprintf (stream, _("\
9940 -madd-bnd-prefix add BND prefix for all valid branches\n"));
9943 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
9944 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
9945 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
9947 /* Pick the target format to use. */
9950 i386_target_format (void)
9952 if (!strncmp (default_arch, "x86_64", 6))
9954 update_code_flag (CODE_64BIT, 1);
9955 if (default_arch[6] == '\0')
9956 x86_elf_abi = X86_64_ABI;
9958 x86_elf_abi = X86_64_X32_ABI;
9960 else if (!strcmp (default_arch, "i386"))
9961 update_code_flag (CODE_32BIT, 1);
9963 as_fatal (_("unknown architecture"));
9965 if (cpu_flags_all_zero (&cpu_arch_isa_flags))
9966 cpu_arch_isa_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9967 if (cpu_flags_all_zero (&cpu_arch_tune_flags))
9968 cpu_arch_tune_flags = cpu_arch[flag_code == CODE_64BIT].flags;
9970 switch (OUTPUT_FLAVOR)
9972 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
9973 case bfd_target_aout_flavour:
9974 return AOUT_TARGET_FORMAT;
9976 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
9977 # if defined (TE_PE) || defined (TE_PEP)
9978 case bfd_target_coff_flavour:
9979 return flag_code == CODE_64BIT ? "pe-x86-64" : "pe-i386";
9980 # elif defined (TE_GO32)
9981 case bfd_target_coff_flavour:
9984 case bfd_target_coff_flavour:
9988 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
9989 case bfd_target_elf_flavour:
9993 switch (x86_elf_abi)
9996 format = ELF_TARGET_FORMAT;
9999 use_rela_relocations = 1;
10001 format = ELF_TARGET_FORMAT64;
10003 case X86_64_X32_ABI:
10004 use_rela_relocations = 1;
10006 disallow_64bit_reloc = 1;
10007 format = ELF_TARGET_FORMAT32;
10010 if (cpu_arch_isa == PROCESSOR_L1OM)
10012 if (x86_elf_abi != X86_64_ABI)
10013 as_fatal (_("Intel L1OM is 64bit only"));
10014 return ELF_TARGET_L1OM_FORMAT;
10016 if (cpu_arch_isa == PROCESSOR_K1OM)
10018 if (x86_elf_abi != X86_64_ABI)
10019 as_fatal (_("Intel K1OM is 64bit only"));
10020 return ELF_TARGET_K1OM_FORMAT;
10026 #if defined (OBJ_MACH_O)
10027 case bfd_target_mach_o_flavour:
10028 if (flag_code == CODE_64BIT)
10030 use_rela_relocations = 1;
10032 return "mach-o-x86-64";
10035 return "mach-o-i386";
10043 #endif /* OBJ_MAYBE_ more than one */
10045 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
10047 i386_elf_emit_arch_note (void)
10049 if (IS_ELF && cpu_arch_name != NULL)
10052 asection *seg = now_seg;
10053 subsegT subseg = now_subseg;
10054 Elf_Internal_Note i_note;
10055 Elf_External_Note e_note;
10056 asection *note_secp;
10059 /* Create the .note section. */
10060 note_secp = subseg_new (".note", 0);
10061 bfd_set_section_flags (stdoutput,
10063 SEC_HAS_CONTENTS | SEC_READONLY);
10065 /* Process the arch string. */
10066 len = strlen (cpu_arch_name);
10068 i_note.namesz = len + 1;
10070 i_note.type = NT_ARCH;
10071 p = frag_more (sizeof (e_note.namesz));
10072 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
10073 p = frag_more (sizeof (e_note.descsz));
10074 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
10075 p = frag_more (sizeof (e_note.type));
10076 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
10077 p = frag_more (len + 1);
10078 strcpy (p, cpu_arch_name);
10080 frag_align (2, 0, 0);
10082 subseg_set (seg, subseg);
10088 md_undefined_symbol (char *name)
10090 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
10091 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
10092 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
10093 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
10097 if (symbol_find (name))
10098 as_bad (_("GOT already in symbol table"));
10099 GOT_symbol = symbol_new (name, undefined_section,
10100 (valueT) 0, &zero_address_frag);
10107 /* Round up a section size to the appropriate boundary. */
10110 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size)
10112 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
10113 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
10115 /* For a.out, force the section size to be aligned. If we don't do
10116 this, BFD will align it for us, but it will not write out the
10117 final bytes of the section. This may be a bug in BFD, but it is
10118 easier to fix it here since that is how the other a.out targets
10122 align = bfd_get_section_alignment (stdoutput, segment);
10123 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
10130 /* On the i386, PC-relative offsets are relative to the start of the
10131 next instruction. That is, the address of the offset, plus its
10132 size, since the offset is always the last part of the insn. */
10135 md_pcrel_from (fixS *fixP)
10137 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
10143 s_bss (int ignore ATTRIBUTE_UNUSED)
10147 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10149 obj_elf_section_change_hook ();
10151 temp = get_absolute_expression ();
10152 subseg_set (bss_section, (subsegT) temp);
10153 demand_empty_rest_of_line ();
10159 i386_validate_fix (fixS *fixp)
10161 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
10163 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
10167 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
10172 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
10174 fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64;
10176 fixp->fx_subsy = 0;
10181 tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
10184 bfd_reloc_code_real_type code;
10186 switch (fixp->fx_r_type)
10188 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10189 case BFD_RELOC_SIZE32:
10190 case BFD_RELOC_SIZE64:
10191 if (S_IS_DEFINED (fixp->fx_addsy)
10192 && !S_IS_EXTERNAL (fixp->fx_addsy))
10194 /* Resolve size relocation against local symbol to size of
10195 the symbol plus addend. */
10196 valueT value = S_GET_SIZE (fixp->fx_addsy) + fixp->fx_offset;
10197 if (fixp->fx_r_type == BFD_RELOC_SIZE32
10198 && !fits_in_unsigned_long (value))
10199 as_bad_where (fixp->fx_file, fixp->fx_line,
10200 _("symbol size computation overflow"));
10201 fixp->fx_addsy = NULL;
10202 fixp->fx_subsy = NULL;
10203 md_apply_fix (fixp, (valueT *) &value, NULL);
10208 case BFD_RELOC_X86_64_PLT32:
10209 case BFD_RELOC_X86_64_PLT32_BND:
10210 case BFD_RELOC_X86_64_GOT32:
10211 case BFD_RELOC_X86_64_GOTPCREL:
10212 case BFD_RELOC_386_PLT32:
10213 case BFD_RELOC_386_GOT32:
10214 case BFD_RELOC_386_GOTOFF:
10215 case BFD_RELOC_386_GOTPC:
10216 case BFD_RELOC_386_TLS_GD:
10217 case BFD_RELOC_386_TLS_LDM:
10218 case BFD_RELOC_386_TLS_LDO_32:
10219 case BFD_RELOC_386_TLS_IE_32:
10220 case BFD_RELOC_386_TLS_IE:
10221 case BFD_RELOC_386_TLS_GOTIE:
10222 case BFD_RELOC_386_TLS_LE_32:
10223 case BFD_RELOC_386_TLS_LE:
10224 case BFD_RELOC_386_TLS_GOTDESC:
10225 case BFD_RELOC_386_TLS_DESC_CALL:
10226 case BFD_RELOC_X86_64_TLSGD:
10227 case BFD_RELOC_X86_64_TLSLD:
10228 case BFD_RELOC_X86_64_DTPOFF32:
10229 case BFD_RELOC_X86_64_DTPOFF64:
10230 case BFD_RELOC_X86_64_GOTTPOFF:
10231 case BFD_RELOC_X86_64_TPOFF32:
10232 case BFD_RELOC_X86_64_TPOFF64:
10233 case BFD_RELOC_X86_64_GOTOFF64:
10234 case BFD_RELOC_X86_64_GOTPC32:
10235 case BFD_RELOC_X86_64_GOT64:
10236 case BFD_RELOC_X86_64_GOTPCREL64:
10237 case BFD_RELOC_X86_64_GOTPC64:
10238 case BFD_RELOC_X86_64_GOTPLT64:
10239 case BFD_RELOC_X86_64_PLTOFF64:
10240 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10241 case BFD_RELOC_X86_64_TLSDESC_CALL:
10242 case BFD_RELOC_RVA:
10243 case BFD_RELOC_VTABLE_ENTRY:
10244 case BFD_RELOC_VTABLE_INHERIT:
10246 case BFD_RELOC_32_SECREL:
10248 code = fixp->fx_r_type;
10250 case BFD_RELOC_X86_64_32S:
10251 if (!fixp->fx_pcrel)
10253 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
10254 code = fixp->fx_r_type;
10258 if (fixp->fx_pcrel)
10260 switch (fixp->fx_size)
10263 as_bad_where (fixp->fx_file, fixp->fx_line,
10264 _("can not do %d byte pc-relative relocation"),
10266 code = BFD_RELOC_32_PCREL;
10268 case 1: code = BFD_RELOC_8_PCREL; break;
10269 case 2: code = BFD_RELOC_16_PCREL; break;
10271 code = (fixp->fx_r_type == BFD_RELOC_X86_64_PC32_BND
10272 ? fixp-> fx_r_type : BFD_RELOC_32_PCREL);
10275 case 8: code = BFD_RELOC_64_PCREL; break;
10281 switch (fixp->fx_size)
10284 as_bad_where (fixp->fx_file, fixp->fx_line,
10285 _("can not do %d byte relocation"),
10287 code = BFD_RELOC_32;
10289 case 1: code = BFD_RELOC_8; break;
10290 case 2: code = BFD_RELOC_16; break;
10291 case 4: code = BFD_RELOC_32; break;
10293 case 8: code = BFD_RELOC_64; break;
10300 if ((code == BFD_RELOC_32
10301 || code == BFD_RELOC_32_PCREL
10302 || code == BFD_RELOC_X86_64_32S)
10304 && fixp->fx_addsy == GOT_symbol)
10307 code = BFD_RELOC_386_GOTPC;
10309 code = BFD_RELOC_X86_64_GOTPC32;
10311 if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL)
10313 && fixp->fx_addsy == GOT_symbol)
10315 code = BFD_RELOC_X86_64_GOTPC64;
10318 rel = (arelent *) xmalloc (sizeof (arelent));
10319 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
10320 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
10322 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
10324 if (!use_rela_relocations)
10326 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
10327 vtable entry to be used in the relocation's section offset. */
10328 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
10329 rel->address = fixp->fx_offset;
10330 #if defined (OBJ_COFF) && defined (TE_PE)
10331 else if (fixp->fx_addsy && S_IS_WEAK (fixp->fx_addsy))
10332 rel->addend = fixp->fx_addnumber - (S_GET_VALUE (fixp->fx_addsy) * 2);
10337 /* Use the rela in 64bit mode. */
10340 if (disallow_64bit_reloc)
10343 case BFD_RELOC_X86_64_DTPOFF64:
10344 case BFD_RELOC_X86_64_TPOFF64:
10345 case BFD_RELOC_64_PCREL:
10346 case BFD_RELOC_X86_64_GOTOFF64:
10347 case BFD_RELOC_X86_64_GOT64:
10348 case BFD_RELOC_X86_64_GOTPCREL64:
10349 case BFD_RELOC_X86_64_GOTPC64:
10350 case BFD_RELOC_X86_64_GOTPLT64:
10351 case BFD_RELOC_X86_64_PLTOFF64:
10352 as_bad_where (fixp->fx_file, fixp->fx_line,
10353 _("cannot represent relocation type %s in x32 mode"),
10354 bfd_get_reloc_code_name (code));
10360 if (!fixp->fx_pcrel)
10361 rel->addend = fixp->fx_offset;
10365 case BFD_RELOC_X86_64_PLT32:
10366 case BFD_RELOC_X86_64_PLT32_BND:
10367 case BFD_RELOC_X86_64_GOT32:
10368 case BFD_RELOC_X86_64_GOTPCREL:
10369 case BFD_RELOC_X86_64_TLSGD:
10370 case BFD_RELOC_X86_64_TLSLD:
10371 case BFD_RELOC_X86_64_GOTTPOFF:
10372 case BFD_RELOC_X86_64_GOTPC32_TLSDESC:
10373 case BFD_RELOC_X86_64_TLSDESC_CALL:
10374 rel->addend = fixp->fx_offset - fixp->fx_size;
10377 rel->addend = (section->vma
10379 + fixp->fx_addnumber
10380 + md_pcrel_from (fixp));
10385 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
10386 if (rel->howto == NULL)
10388 as_bad_where (fixp->fx_file, fixp->fx_line,
10389 _("cannot represent relocation type %s"),
10390 bfd_get_reloc_code_name (code));
10391 /* Set howto to a garbage value so that we can keep going. */
10392 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
10393 gas_assert (rel->howto != NULL);
10399 #include "tc-i386-intel.c"
10402 tc_x86_parse_to_dw2regnum (expressionS *exp)
10404 int saved_naked_reg;
10405 char saved_register_dot;
10407 saved_naked_reg = allow_naked_reg;
10408 allow_naked_reg = 1;
10409 saved_register_dot = register_chars['.'];
10410 register_chars['.'] = '.';
10411 allow_pseudo_reg = 1;
10412 expression_and_evaluate (exp);
10413 allow_pseudo_reg = 0;
10414 register_chars['.'] = saved_register_dot;
10415 allow_naked_reg = saved_naked_reg;
10417 if (exp->X_op == O_register && exp->X_add_number >= 0)
10419 if ((addressT) exp->X_add_number < i386_regtab_size)
10421 exp->X_op = O_constant;
10422 exp->X_add_number = i386_regtab[exp->X_add_number]
10423 .dw2_regnum[flag_code >> 1];
10426 exp->X_op = O_illegal;
10431 tc_x86_frame_initial_instructions (void)
10433 static unsigned int sp_regno[2];
10435 if (!sp_regno[flag_code >> 1])
10437 char *saved_input = input_line_pointer;
10438 char sp[][4] = {"esp", "rsp"};
10441 input_line_pointer = sp[flag_code >> 1];
10442 tc_x86_parse_to_dw2regnum (&exp);
10443 gas_assert (exp.X_op == O_constant);
10444 sp_regno[flag_code >> 1] = exp.X_add_number;
10445 input_line_pointer = saved_input;
10448 cfi_add_CFA_def_cfa (sp_regno[flag_code >> 1], -x86_cie_data_alignment);
10449 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);
10453 x86_dwarf2_addr_size (void)
10455 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
10456 if (x86_elf_abi == X86_64_X32_ABI)
10459 return bfd_arch_bits_per_address (stdoutput) / 8;
10463 i386_elf_section_type (const char *str, size_t len)
10465 if (flag_code == CODE_64BIT
10466 && len == sizeof ("unwind") - 1
10467 && strncmp (str, "unwind", 6) == 0)
10468 return SHT_X86_64_UNWIND;
10475 i386_solaris_fix_up_eh_frame (segT sec)
10477 if (flag_code == CODE_64BIT)
10478 elf_section_type (sec) = SHT_X86_64_UNWIND;
10484 tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size)
10488 exp.X_op = O_secrel;
10489 exp.X_add_symbol = symbol;
10490 exp.X_add_number = 0;
10491 emit_expr (&exp, size);
10495 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10496 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10499 x86_64_section_letter (int letter, char **ptr_msg)
10501 if (flag_code == CODE_64BIT)
10504 return SHF_X86_64_LARGE;
10506 *ptr_msg = _("bad .section directive: want a,l,w,x,M,S,G,T in string");
10509 *ptr_msg = _("bad .section directive: want a,w,x,M,S,G,T in string");
10514 x86_64_section_word (char *str, size_t len)
10516 if (len == 5 && flag_code == CODE_64BIT && CONST_STRNEQ (str, "large"))
10517 return SHF_X86_64_LARGE;
10523 handle_large_common (int small ATTRIBUTE_UNUSED)
10525 if (flag_code != CODE_64BIT)
10527 s_comm_internal (0, elf_common_parse);
10528 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10532 static segT lbss_section;
10533 asection *saved_com_section_ptr = elf_com_section_ptr;
10534 asection *saved_bss_section = bss_section;
10536 if (lbss_section == NULL)
10538 flagword applicable;
10539 segT seg = now_seg;
10540 subsegT subseg = now_subseg;
10542 /* The .lbss section is for local .largecomm symbols. */
10543 lbss_section = subseg_new (".lbss", 0);
10544 applicable = bfd_applicable_section_flags (stdoutput);
10545 bfd_set_section_flags (stdoutput, lbss_section,
10546 applicable & SEC_ALLOC);
10547 seg_info (lbss_section)->bss = 1;
10549 subseg_set (seg, subseg);
10552 elf_com_section_ptr = &_bfd_elf_large_com_section;
10553 bss_section = lbss_section;
10555 s_comm_internal (0, elf_common_parse);
10557 elf_com_section_ptr = saved_com_section_ptr;
10558 bss_section = saved_bss_section;
10561 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */