1 /* linux/drivers/video/samsung/s5p-dsim.c
3 * Samsung MIPI-DSIM driver.
5 * InKi Dae, <inki.dae@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * Modified by Samsung Electronics (UK) on May 2010
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/errno.h>
18 #include <linux/clk.h>
19 #include <linux/mutex.h>
20 #include <linux/wait.h>
24 #include <linux/ctype.h>
25 #include <linux/platform_device.h>
27 #include <linux/irq.h>
28 #include <linux/memory.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/kthread.h>
32 #include <linux/workqueue.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/gpio.h>
35 #include <plat/clock.h>
36 #include <plat/regs-dsim.h>
37 #include <plat/gpio-cfg.h>
39 #include <mach/dsim.h>
40 #include <mach/mipi_ddi.h>
41 #include <mach/irqs.h>
44 #include "s5p_dsim_lowlevel.h"
47 #ifdef CONFIG_HAS_WAKELOCK
48 #include <linux/wakelock.h>
49 #include <linux/earlysuspend.h>
50 #include <linux/suspend.h>
53 struct mipi_lcd_info {
54 struct list_head list;
55 struct mipi_lcd_driver *mipi_drv;
58 static DEFINE_MUTEX(dsim_rd_wr_mutex);
59 static DECLARE_COMPLETION(dsim_rd_comp);
60 static DECLARE_COMPLETION(dsim_wr_comp);
62 #define MIPI_RESP_ERR 0x02
63 #define MIPI_RESP_EOTP 0x08
64 #define MIPI_RESP_GENERIC_RD_1 0x11
65 #define MIPI_RESP_GENERIC_RD_2 0x12
66 #define MIPI_RESP_GENERIC_RD_LONG 0x1A
67 #define MIPI_RESP_DCS_RD_LONG 0x1C
68 #define MIPI_RESP_DCS_RD_1 0x21
69 #define MIPI_RESP_DCS_RD_2 0x22
71 #define MIPI_CMD_GENERIC_WR_0 0x03
72 #define MIPI_CMD_GENERIC_WR_1 0x13
73 #define MIPI_CMD_GENERIC_WR_2 0x23
74 #define MIPI_CMD_GENERIC_WR_LONG 0x29
76 #define MIPI_CMD_DSI_WR_0 0x05
77 #define MIPI_CMD_DSI_WR_1 0x15
78 #define MIPI_CMD_DSI_WR_LONG 0x39
80 #define MIPI_CMD_GENERIC_RD_0 0x04
81 #define MIPI_CMD_GENERIC_RD_1 0x14
82 #define MIPI_CMD_GENERIC_RD_2 0x24
84 #define MIPI_CMD_DSI_RD_0 0x06
86 #define MIPI_CMD_DSI_SET_PKT_SZ 0x37
88 #define DSIM_TIMEOUT msecs_to_jiffies(250)
89 #define DSIM_RX_FIFO_READ_DONE 0x30800002
90 #define DSIM_MAX_RX_FIFO 20
92 #define S5P_DSIM_INT_SFR_FIFO_EMPTY 29
93 #define S5P_DSIM_INT_BTA 25
94 #define S5P_DSIM_INT_MSK_FRAME_DONE 24
95 #define S5P_DSIM_INT_RX_TIMEOUT 21
96 #define S5P_DSIM_INT_BTA_TIMEOUT 20
97 #define S5P_DSIM_INT_RX_DONE 18
98 #define S5P_DSIM_INT_RX_TE 17
99 #define S5P_DSIM_INT_RX_ACK 16
100 #define S5P_DSIM_INT_RX_ECC_ERR 15
101 #define S5P_DSIM_IMT_RX_CRC_ERR 14
103 static LIST_HEAD(lcd_info_list);
104 static DEFINE_MUTEX(mipi_lock);
105 static struct dsim_global *g_dsim;
107 static struct s5p_platform_dsim *to_dsim_plat(struct device *dev)
109 struct platform_device *pdev = to_platform_device(dev);
111 return (struct s5p_platform_dsim *)pdev->dev.platform_data;
114 static void s5p_dsim_frame_done_interrupt_enable(struct dsim_global *dsim, u8 enable)
119 if (!dsim->mipi_ddi_pd->resume_complete)
122 intmsk = readl(dsim->reg_base + S5P_DSIM_INTMSK);
124 if (state == 0) /* enable Frame Done interrupts */
125 intmsk &= ~(0x01 << S5P_DSIM_INT_MSK_FRAME_DONE);
126 else /* disable Frame Done interrupts */
127 intmsk |= (0x01 << S5P_DSIM_INT_MSK_FRAME_DONE);
129 writel(intmsk, dsim->reg_base + S5P_DSIM_INTMSK);
132 void set_dsim_lcd_enabled(u8 enable)
134 struct dsim_global *dsim = g_dsim;
136 dsim->dsim_lcd_info->lcd_enabled = enable;
137 if (dsim->dsim_info->hs_toggle)
138 s5p_dsim_frame_done_interrupt_enable(dsim, enable);
141 void set_dsim_hs_clk_toggle_count(u8 count)
143 struct dsim_global *dsim = g_dsim;
145 dsim->dsim_toggle_per_frame_count = count;
146 if (dsim->dsim_lcd_info->lcd_enabled) {
147 if (dsim->dsim_info->hs_toggle) {
148 s5p_dsim_frame_done_interrupt_enable(dsim, 1);
149 schedule_delayed_work(&dsim->check_hs_toggle_work, msecs_to_jiffies(60000));
151 s5p_dsim_frame_done_interrupt_enable(dsim, count ? 1 : 0);
155 static void dsim_work_q_handler(struct work_struct *work)
157 struct dsim_global *dsim =
158 container_of(work, struct dsim_global, dsim_work.work);
160 s5p_dsim_frame_done_interrupt_enable(dsim, 1);
163 static void dsim_check_hs_toggle_work_q_handler(struct work_struct *work)
165 struct dsim_global *dsim =
166 container_of(work, struct dsim_global, check_hs_toggle_work.work);
168 if (dsim->dsim_info->hs_toggle) {
169 dev_info(dsim->dev, "check_hs_toggle\n");
170 schedule_delayed_work(&dsim->check_hs_toggle_work, msecs_to_jiffies(60000));
174 unsigned char s5p_dsim_wr_data(void *ptr,
175 unsigned int data_id, unsigned int data0, unsigned int data1)
177 struct dsim_global *dsim = ptr;
178 unsigned int dsim_base = dsim->reg_base;
180 if (dsim->state == DSIM_STATE_ULPS) {
181 dev_err(dsim->dev, "DSIM state: ULPS\n");
185 if (dsim->mipi_ddi_pd->resume_complete == 0) {
186 dev_err(dsim->dev, "DSIM Status: SUSPEND\n");
190 mutex_lock(&dsim_rd_wr_mutex);
193 /* short packet types of packet types for command. */
194 case GEN_SHORT_WR_NO_PARA:
195 case GEN_SHORT_WR_1_PARA:
196 case GEN_SHORT_WR_2_PARA:
199 case SET_MAX_RTN_PKT_SIZE:
200 s5p_dsim_wr_tx_header(dsim_base, (unsigned char) data_id,
201 (unsigned char) data0, (unsigned char) data1);
202 mutex_unlock(&dsim_rd_wr_mutex);
203 return DSIM_TRUE; /* response should be implemented */
204 /* general command */
209 s5p_dsim_wr_tx_header(dsim_base, (unsigned char) data_id,
210 (unsigned char) data0, (unsigned char) data1);
211 mutex_unlock(&dsim_rd_wr_mutex);
212 return DSIM_TRUE; /* response should be implemented. */
213 /* packet types for video data */
219 mutex_unlock(&dsim_rd_wr_mutex);
222 /* short and response packet types for command */
227 s5p_dsim_clear_interrupt(dsim_base, 0xffffffff);
228 s5p_dsim_wr_tx_header(dsim_base, (unsigned char) data_id,
229 (unsigned char) data0, (unsigned char) data1);
230 mutex_unlock(&dsim_rd_wr_mutex);
231 return DSIM_FALSE; /* response should be implemented. */
233 /* long packet type and null packet */
236 mutex_unlock(&dsim_rd_wr_mutex);
242 u32* pWordPtr = (u32 *)data0;
243 INIT_COMPLETION(dsim_wr_comp);
246 s5p_dsim_wr_tx_data(dsim_base, pWordPtr[uCnt]);
247 } while (((data1-1) / 4) > uCnt++);
249 /* put data into header fifo */
250 s5p_dsim_wr_tx_header(dsim_base, (unsigned char) data_id,
251 (unsigned char) (((unsigned short) data1) & 0xff),
252 (unsigned char) ((((unsigned short) data1) & 0xff00) >> 8));
254 if (!wait_for_completion_interruptible_timeout(&dsim_wr_comp, DSIM_TIMEOUT)) {
255 dev_err(dsim->dev, "[DSIM:ERROR] %s Timeout\n", __func__);
256 mutex_unlock(&dsim_rd_wr_mutex);
259 mutex_unlock(&dsim_rd_wr_mutex);
262 /* packet typo for video data */
267 mutex_unlock(&dsim_rd_wr_mutex);
268 return DSIM_TRUE; /* response should be implemented. */
270 dev_warn(dsim->dev, "data id %x is not supported current DSI spec\n", data_id);
271 mutex_unlock(&dsim_rd_wr_mutex);
276 int s5p_dsim_rd_data(void *ptr, u8 addr, u16 count, u8 *buf)
284 struct dsim_global *dsim = ptr;
285 unsigned int reg_base = dsim->reg_base;
287 if (dsim->mipi_ddi_pd->resume_complete == 0) {
288 dev_err(dsim->dev, "DSIM Status: SUSPEND\n");
292 mutex_lock(&dsim_rd_wr_mutex);
293 INIT_COMPLETION(dsim_rd_comp);
297 response = MIPI_RESP_GENERIC_RD_1;
300 response = MIPI_RESP_GENERIC_RD_2;
303 response = MIPI_RESP_GENERIC_RD_LONG;
307 /* set return packet size */
308 txhd = MIPI_CMD_DSI_SET_PKT_SZ | count << 8;
310 writel(txhd, reg_base + S5P_DSIM_PKTHDR);
312 /* set address to read */
313 txhd = MIPI_CMD_GENERIC_RD_1 | addr << 8;
315 writel(txhd, reg_base + S5P_DSIM_PKTHDR);
317 if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp, DSIM_TIMEOUT)) {
318 dev_err(dsim->dev, "ERROR:%s timout\n", __func__);
319 mutex_unlock(&dsim_rd_wr_mutex);
323 rxhd = readl(reg_base + S5P_DSIM_RXFIFO);
324 dev_info(dsim->dev, "rxhd : %x\n", rxhd);
325 if ((u8)(rxhd & 0xff) != response) {
326 dev_err(dsim->dev, "[DSIM:ERROR]:%s wrong response rxhd : %x, response:%x\n"
327 , __func__, rxhd, response);
330 /* for short packet */
332 for (i = 0; i < count; i++)
333 buf[i] = (rxhd >> (8+(i*8))) & 0xff;
336 /* for long packet */
337 rxsize = (u16)((rxhd & 0x00ffff00) >> 8);
338 dev_info(dsim->dev, "rcv size : %d\n", rxsize);
339 if (rxsize != count) {
340 dev_err(dsim->dev, "[DSIM:ERROR]:%s received data size mismatch received : %d, requested : %d\n",
341 __func__, rxsize, count);
345 for (i = 0; i < rxsize>>2; i++) {
346 temp = readl(reg_base + S5P_DSIM_RXFIFO);
347 dev_info(dsim->dev, "pkt : %08x\n", temp);
348 for (j = 0; j < 4; j++) {
349 buf[(i*4)+j] = (u8)(temp>>(j*8))&0xff;
350 /* printk("Value : %02x\n",(temp>>(j*8))&0xff); */
354 temp = readl(reg_base + S5P_DSIM_RXFIFO);
355 dev_info(dsim->dev, "pkt-l : %08x\n", temp);
356 for (j = 0; j < rxsize%4; j++) {
357 buf[(i*4)+j] = (u8)(temp>>(j*8))&0xff;
358 /* printk("Value : %02x\n",(temp>>(j*8))&0xff); */
363 temp = readl(reg_base + S5P_DSIM_RXFIFO);
365 if (temp != DSIM_RX_FIFO_READ_DONE) {
366 dev_warn(dsim->dev, "[DSIM:WARN]:%s Can't found RX FIFO READ DONE FLAG : %x\n", __func__, temp);
370 mutex_unlock(&dsim_rd_wr_mutex);
376 temp = readl(reg_base+S5P_DSIM_RXFIFO);
377 if ((temp == DSIM_RX_FIFO_READ_DONE) || (i > DSIM_MAX_RX_FIFO))
379 dev_info(dsim->dev, "[DSIM:INFO] : %s clear rx fifo : %08x\n", __func__, temp);
382 dev_info(dsim->dev, "[DSIM:INFO] : %s done count : %d, temp : %08x\n", __func__, i, temp);
384 mutex_unlock(&dsim_rd_wr_mutex);
389 int s5p_dsim_dcs_rd_data(void *ptr, u8 addr, u16 count, u8 *buf)
397 struct dsim_global *dsim = ptr;
398 unsigned int reg_base = dsim->reg_base;
400 if (dsim->mipi_ddi_pd->resume_complete == 0) {
401 dev_err(dsim->dev, "DSIM Status: SUSPEND\n");
405 mutex_lock(&dsim_rd_wr_mutex);
406 INIT_COMPLETION(dsim_rd_comp);
410 response = MIPI_RESP_DCS_RD_1;
413 response = MIPI_RESP_DCS_RD_2;
416 response = MIPI_RESP_DCS_RD_LONG;
420 /* set return packet size */
421 txhd = MIPI_CMD_DSI_SET_PKT_SZ | count << 8;
423 writel(txhd, reg_base + S5P_DSIM_PKTHDR);
425 /* set address to read */
426 txhd = MIPI_CMD_DSI_RD_0 | addr << 8;
428 writel(txhd, reg_base + S5P_DSIM_PKTHDR);
430 if (!wait_for_completion_interruptible_timeout(&dsim_rd_comp, DSIM_TIMEOUT)) {
431 dev_err(dsim->dev, "ERROR:%s timout\n", __func__);
432 mutex_unlock(&dsim_rd_wr_mutex);
436 rxhd = readl(reg_base + S5P_DSIM_RXFIFO);
437 dev_info(dsim->dev, "rxhd : %x\n", rxhd);
438 if ((u8)(rxhd & 0xff) != response) {
439 dev_err(dsim->dev, "[DSIM:ERROR]:%s wrong response rxhd : %x, response:%x\n"
440 , __func__, rxhd, response);
443 /* for short packet */
445 for (i = 0; i < count; i++)
446 buf[i] = (rxhd >> (8+(i*8))) & 0xff;
449 /* for long packet */
450 rxsize = (u16)((rxhd & 0x00ffff00) >> 8);
451 dev_info(dsim->dev, "rcv size : %d\n", rxsize);
452 if (rxsize != count) {
453 dev_err(dsim->dev, "[DSIM:ERROR]:%s received data size mismatch received : %d, requested : %d\n",
454 __func__, rxsize, count);
458 for (i = 0; i < rxsize>>2; i++) {
459 temp = readl(reg_base + S5P_DSIM_RXFIFO);
460 dev_info(dsim->dev, "pkt : %08x\n", temp);
461 for (j = 0; j < 4; j++) {
462 buf[(i*4)+j] = (u8)(temp>>(j*8))&0xff;
463 /* printk("Value : %02x\n",(temp>>(j*8))&0xff); */
467 temp = readl(reg_base + S5P_DSIM_RXFIFO);
468 dev_info(dsim->dev, "pkt-l : %08x\n", temp);
469 for (j = 0; j < rxsize%4; j++) {
470 buf[(i*4)+j] = (u8)(temp>>(j*8))&0xff;
471 /* printk("Value : %02x\n",(temp>>(j*8))&0xff); */
476 mutex_unlock(&dsim_rd_wr_mutex);
480 mutex_unlock(&dsim_rd_wr_mutex);
485 static irqreturn_t s5p_dsim_isr(int irq, void *dev_id)
488 unsigned int intsrc = 0;
489 unsigned int intmsk = 0;
490 struct dsim_global *dsim = NULL;
492 dsim = (struct dsim_global *)dev_id;
494 printk(KERN_ERR "%s:error:wrong parameter\n", __func__);
498 intsrc = readl(dsim->reg_base + S5P_DSIM_INTSRC);
499 intmsk = readl(dsim->reg_base + S5P_DSIM_INTMSK);
501 intmsk = ~(intmsk) & intsrc;
503 for (i = 0; i < 32; i++) {
504 if (intmsk & (0x01<<i)) {
506 case S5P_DSIM_INT_BTA:
507 /* printk("S5P_DSIM_INT_BTA\n"); */
509 case S5P_DSIM_INT_RX_TIMEOUT:
510 /* printk("S5P_DSIM_INT_RX_TIMEOUT\n"); */
512 case S5P_DSIM_INT_BTA_TIMEOUT:
513 /* printk("S5P_DSIM_INT_BTA_TIMEOUT\n"); */
515 case S5P_DSIM_INT_RX_DONE:
516 complete_all(&dsim_rd_comp);
517 /* printk("S5P_DSIM_INT_RX_DONE\n"); */
519 case S5P_DSIM_INT_RX_TE:
520 /* printk("S5P_DSIM_INT_RX_TE\n"); */
522 case S5P_DSIM_INT_RX_ACK:
523 /* printk("S5P_DSIM_INT_RX_ACK\n"); */
525 case S5P_DSIM_INT_RX_ECC_ERR:
526 /* printk("S5P_DSIM_INT_RX_ECC_ERR\n"); */
528 case S5P_DSIM_IMT_RX_CRC_ERR:
529 /* printk("S5P_DSIM_IMT_RX_CRC_ERR\n"); */
531 case S5P_DSIM_INT_SFR_FIFO_EMPTY:
532 /* printk("S5P_DSIM_INT_SFR_FIFO_EMPTY\n"); */
533 complete_all(&dsim_wr_comp);
535 case S5P_DSIM_INT_MSK_FRAME_DONE:
536 /* printk("S5P_DSIM_INT_MSK_FRAME_DONE\n"); */
537 if (dsim->dsim_lcd_info->lcd_enabled && dsim->mipi_ddi_pd->resume_complete) {
538 if (completion_done(&dsim_wr_comp) && completion_done(&dsim_rd_comp)) {
539 if (s3cfb_vsync_status_check()) {
540 s5p_dsim_toggle_hs_clock(dsim->reg_base);
541 if (!dsim->dsim_toggle_per_frame_count) {
542 s5p_dsim_frame_done_interrupt_enable(dsim, 0);
543 if (likely(dsim->dsim_info->hs_toggle))
544 schedule_delayed_work(&dsim->dsim_work, dsim->dsim_info->hs_toggle);
546 if (dsim->dsim_toggle_per_frame_count)
547 dsim->dsim_toggle_per_frame_count--;
556 writel(intsrc, dsim->reg_base + S5P_DSIM_INTSRC);
560 static void s5p_dsim_init_header_fifo(struct dsim_global *dsim)
564 for (cnt = 0; cnt < DSIM_HEADER_FIFO_SZ; cnt++)
565 dsim->header_fifo_index[cnt] = -1;
569 static unsigned char s5p_dsim_pll_on(unsigned int dsim_base, unsigned char enable)
572 int sw_timeout = 1000;
573 s5p_dsim_clear_interrupt(dsim_base, DSIM_PLL_STABLE);
574 s5p_dsim_enable_pll(dsim_base, 1);
577 if (s5p_dsim_is_pll_stable(dsim_base))
583 s5p_dsim_enable_pll(dsim_base, 0);
588 static unsigned long s5p_dsim_change_pll(struct dsim_global *dsim, unsigned char pre_divider,
589 unsigned short main_divider, unsigned char scaler)
591 unsigned long dfin_pll, dfvco, dpll_out;
592 unsigned char freq_band;
593 unsigned char temp0 = 0, temp1 = 0;
594 unsigned int dsim_base = dsim->reg_base;
596 dfin_pll = (MIPI_FIN / pre_divider);
598 if (dfin_pll < 6 * 1000 * 1000 || dfin_pll > 12 * 1000 * 1000) {
599 dev_warn(dsim->dev, "warning!!\n");
600 dev_warn(dsim->dev, "fin_pll range is 6MHz ~ 12MHz\n");
601 dev_warn(dsim->dev, "fin_pll of mipi dphy pll is %luMHz\n", (dfin_pll / 1000000));
603 s5p_dsim_enable_afc(dsim_base, 0, 0);
605 if (dfin_pll < 7 * 1000000)
606 s5p_dsim_enable_afc(dsim_base, 1, 0x1);
607 else if (dfin_pll < 8 * 1000000)
608 s5p_dsim_enable_afc(dsim_base, 1, 0x0);
609 else if (dfin_pll < 9 * 1000000)
610 s5p_dsim_enable_afc(dsim_base, 1, 0x3);
611 else if (dfin_pll < 10 * 1000000)
612 s5p_dsim_enable_afc(dsim_base, 1, 0x2);
613 else if (dfin_pll < 11 * 1000000)
614 s5p_dsim_enable_afc(dsim_base, 1, 0x5);
616 s5p_dsim_enable_afc(dsim_base, 1, 0x4);
619 dfvco = dfin_pll * main_divider;
620 dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
621 dfvco, dfin_pll, main_divider);
622 if (dfvco < 500000000 || dfvco > 1000000000) {
623 dev_warn(dsim->dev, "Caution!!\n");
624 dev_warn(dsim->dev, "fvco range is 500MHz ~ 1000MHz\n");
625 dev_warn(dsim->dev, "fvco of mipi dphy pll is %luMHz\n", (dfvco / 1000000));
628 dpll_out = dfvco / (1 << scaler);
629 dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
630 dpll_out, dfvco, scaler);
631 if (dpll_out < 100 * 1000000)
633 else if (dpll_out < 120 * 1000000)
635 else if (dpll_out < 170 * 1000000)
637 else if (dpll_out < 220 * 1000000)
639 else if (dpll_out < 270 * 1000000)
641 else if (dpll_out < 320 * 1000000)
643 else if (dpll_out < 390 * 1000000)
645 else if (dpll_out < 450 * 1000000)
647 else if (dpll_out < 510 * 1000000)
649 else if (dpll_out < 560 * 1000000)
651 else if (dpll_out < 640 * 1000000)
653 else if (dpll_out < 690 * 1000000)
655 else if (dpll_out < 770 * 1000000)
657 else if (dpll_out < 870 * 1000000)
659 else if (dpll_out < 950 * 1000000)
664 dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
666 s5p_dsim_pll_freq(dsim_base, pre_divider, main_divider, scaler);
668 s5p_dsim_hs_zero_ctrl(dsim_base, temp0);
669 s5p_dsim_prep_ctrl(dsim_base, temp1);
672 s5p_dsim_pll_freq_band(dsim_base, freq_band);
675 s5p_dsim_pll_stable_time(dsim_base, dsim->dsim_info->pll_stable_time);
678 dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n", (dpll_out / 1000000));
683 static void s5p_dsim_set_clock(struct dsim_global *dsim,
684 unsigned char byte_clk_sel, unsigned char enable)
686 unsigned int esc_div;
687 unsigned long esc_clk_error_rate;
688 unsigned int dsim_base = dsim->reg_base;
691 dsim->e_clk_src = byte_clk_sel;
693 /* Escape mode clock and byte clock source */
694 s5p_dsim_set_byte_clock_src(dsim_base, byte_clk_sel);
696 /* DPHY, DSIM Link : D-PHY clock out */
697 if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
698 dsim->hs_clk = s5p_dsim_change_pll(dsim, dsim->dsim_info->p,
699 dsim->dsim_info->m, dsim->dsim_info->s);
700 dsim->byte_clk = dsim->hs_clk / 8;
701 s5p_dsim_enable_pll_bypass(dsim_base, 0);
702 s5p_dsim_pll_on(dsim_base, 1);
703 usleep_range(1000, 1000);
704 /* DPHY : D-PHY clock out, DSIM link : external clock out */
705 } else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
706 dev_warn(dsim->dev, "this project is not supported external clock source for MIPI DSIM\n");
707 else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
708 dev_warn(dsim->dev, "this project is not supported external clock source for MIPI DSIM\n");
710 /* escape clock divider */
711 esc_div = dsim->byte_clk / (dsim->dsim_info->esc_clk);
712 dev_dbg(dsim->dev, "esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
713 esc_div, dsim->byte_clk, dsim->dsim_info->esc_clk);
714 if ((dsim->byte_clk / esc_div) >= 20000000 ||
715 (dsim->byte_clk / esc_div) > dsim->dsim_info->esc_clk)
718 dsim->escape_clk = dsim->byte_clk / esc_div;
719 dev_dbg(dsim->dev, "escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
720 dsim->escape_clk, dsim->byte_clk, esc_div);
723 * enable escclk on lane
725 s5p_dsim_enable_byte_clock(dsim_base, DSIM_TRUE);
727 /* enable byte clk and escape clock */
728 s5p_dsim_set_esc_clk_prs(dsim_base, 1, esc_div);
729 /* escape clock on lane */
730 s5p_dsim_enable_esc_clk_on_lane(dsim_base, (DSIM_LANE_CLOCK | dsim->data_lane), 1);
732 dev_dbg(dsim->dev, "byte clock is %luMHz\n", (dsim->byte_clk / 1000000));
733 dev_dbg(dsim->dev, "escape clock that user's need is %lu\n", (dsim->dsim_info->esc_clk / 1000000));
734 dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
735 dev_dbg(dsim->dev, "escape clock is %luMHz\n", ((dsim->byte_clk / esc_div) / 1000000));
737 if ((dsim->byte_clk / esc_div) > dsim->escape_clk) {
738 esc_clk_error_rate = dsim->escape_clk / (dsim->byte_clk / esc_div);
739 dev_warn(dsim->dev, "error rate is %lu over\n", (esc_clk_error_rate / 100));
740 } else if ((dsim->byte_clk / esc_div) < (dsim->escape_clk)) {
741 esc_clk_error_rate = (dsim->byte_clk / esc_div) / dsim->escape_clk;
742 dev_warn(dsim->dev, "error rate is %lu under\n", (esc_clk_error_rate / 100));
745 s5p_dsim_enable_esc_clk_on_lane(dsim_base, (DSIM_LANE_CLOCK | dsim->data_lane), 0);
746 s5p_dsim_set_esc_clk_prs(dsim_base, 0, 0);
748 s5p_dsim_enable_byte_clock(dsim_base, DSIM_FALSE);
750 if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
751 s5p_dsim_pll_on(dsim_base, 0);
755 static int s5p_dsim_late_resume_init_dsim(struct dsim_global *dsim)
757 unsigned int dsim_base = dsim->reg_base;
759 if (dsim->pd->init_d_phy)
760 dsim->pd->init_d_phy(dsim->reg_base);
762 dsim->state = DSIM_STATE_RESET;
764 switch (dsim->dsim_info->e_no_data_lane) {
765 case DSIM_DATA_LANE_1:
766 dsim->data_lane = DSIM_LANE_DATA0;
768 case DSIM_DATA_LANE_2:
769 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
771 case DSIM_DATA_LANE_3:
772 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
775 case DSIM_DATA_LANE_4:
776 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
777 DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
780 dev_info(dsim->dev, "data lane is invalid\n");
784 s5p_dsim_init_header_fifo(dsim);
785 s5p_dsim_sw_reset(dsim_base);
786 s5p_dsim_dp_dn_swap(dsim_base, dsim->dsim_info->e_lane_swap);
788 /* enable only frame done interrupt */
789 /* s5p_dsim_clear_interrupt(dsim_base, AllDsimIntr); */
790 /* s5p_dsim_set_interrupt_mask(dsim->reg_base, AllDsimIntr, 1); */
796 static int s5p_dsim_init_dsim(struct dsim_global *dsim)
798 unsigned int dsim_base = dsim->reg_base;
800 if (dsim->pd->init_d_phy)
801 dsim->pd->init_d_phy(dsim->reg_base);
803 dsim->state = DSIM_STATE_RESET;
805 switch (dsim->dsim_info->e_no_data_lane) {
806 case DSIM_DATA_LANE_1:
807 dsim->data_lane = DSIM_LANE_DATA0;
809 case DSIM_DATA_LANE_2:
810 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
812 case DSIM_DATA_LANE_3:
813 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
816 case DSIM_DATA_LANE_4:
817 dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
818 DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
821 dev_info(dsim->dev, "data lane is invalid\n");
825 s5p_dsim_init_header_fifo(dsim);
826 s5p_dsim_dp_dn_swap(dsim_base, dsim->dsim_info->e_lane_swap);
828 /* enable only frame done interrupt */
829 /* s5p_dsim_clear_interrupt(dsim_base, AllDsimIntr); */
830 /* s5p_dsim_set_interrupt_mask(dsim->reg_base, AllDsimIntr, 1); */
836 static void s5p_dsim_set_display_mode(struct dsim_global *dsim,
837 struct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd)
839 struct s3cfb_lcd *main_lcd_panel_info = NULL, *sub_lcd_panel_info = NULL;
840 struct s3cfb_lcd_timing *main_timing = NULL;
841 unsigned int dsim_base = dsim->reg_base;
843 if (main_lcd != NULL) {
844 if (main_lcd->lcd_panel_info != NULL) {
845 main_lcd_panel_info =
846 (struct s3cfb_lcd *) main_lcd->lcd_panel_info;
848 s5p_dsim_set_main_disp_resol(dsim_base,
849 main_lcd_panel_info->height,
850 main_lcd_panel_info->width);
852 dev_warn(dsim->dev, "lcd panel info of main lcd is NULL\n");
854 dev_err(dsim->dev, "main lcd is NULL\n");
858 /* in case of VIDEO MODE (RGB INTERFACE) */
859 if (dsim->dsim_lcd_info->e_interface == (u32)DSIM_VIDEO) {
861 main_timing = &main_lcd_panel_info->timing;
862 if (main_timing == NULL) {
863 dev_err(dsim->dev, "main_timing is NULL\n");
867 s5p_dsim_set_main_disp_vporch(dsim_base,
868 main_timing->cmd_allow_len,
869 main_timing->stable_vfp, (u16) main_timing->v_bp);
870 s5p_dsim_set_main_disp_hporch(dsim_base,
871 main_timing->h_fp, (u16) main_timing->h_bp);
872 s5p_dsim_set_main_disp_sync_area(dsim_base,
873 main_timing->v_sw, (u16) main_timing->h_sw);
875 /* in case of COMMAND MODE (CPU or I80 INTERFACE) */
877 if (sub_lcd != NULL) {
878 if (sub_lcd->lcd_panel_info != NULL) {
881 sub_lcd->lcd_panel_info;
883 s5p_dsim_set_sub_disp_resol(dsim_base,
884 sub_lcd_panel_info->height,
885 sub_lcd_panel_info->width);
887 dev_warn(dsim->dev, "lcd panel info of sub lcd is NULL\n");
891 s5p_dsim_display_config(dsim_base, dsim->dsim_lcd_info, NULL);
894 static int s5p_dsim_init_link(struct dsim_global *dsim)
896 unsigned int time_out = 100;
897 unsigned int dsim_base = dsim->reg_base;
899 switch (dsim->state) {
900 case DSIM_STATE_RESET:
901 case DSIM_STATE_INIT:
902 s5p_dsim_init_fifo_pointer(dsim_base, 0x0);
903 usleep_range(10000, 10000);
904 s5p_dsim_init_fifo_pointer(dsim_base, 0x1f);
906 /* dsi configuration */
907 s5p_dsim_init_config(dsim_base, dsim->dsim_lcd_info, NULL, dsim->dsim_info);
908 s5p_dsim_enable_lane(dsim_base, DSIM_LANE_CLOCK, 1);
909 s5p_dsim_enable_lane(dsim_base, dsim->data_lane, 1);
911 /* set clock configuration */
912 s5p_dsim_set_clock(dsim, dsim->dsim_info->e_byte_clk, 1);
913 usleep_range(5000, 5000);
914 /* check clock and data lane state is stop state */
915 while (!(s5p_dsim_is_lane_state(dsim_base, DSIM_LANE_CLOCK) == DSIM_LANE_STATE_STOP) &&
916 !(s5p_dsim_is_lane_state(dsim_base, dsim->data_lane) == DSIM_LANE_STATE_STOP)) {
919 dev_info(dsim->dev, "DSI Master state is not stop state!!!\n");
920 dev_info(dsim->dev, "Please check initialization process\n");
927 /* dev_info(dsim->dev, "initialization of DSI Master is successful\n"); */
928 /* dev_info(dsim->dev, "DSI Master state is stop state\n"); */
931 dsim->state = DSIM_STATE_STOP;
933 /* BTA sequence counters */
934 s5p_dsim_set_stop_state_counter(dsim_base, dsim->dsim_info->stop_holding_cnt);
935 s5p_dsim_set_bta_timeout(dsim_base, dsim->dsim_info->bta_timeout);
936 s5p_dsim_set_lpdr_timeout(dsim_base, dsim->dsim_info->rx_timeout);
938 /* default LPDT by both cpu and lcd controller */
939 s5p_dsim_set_data_mode(dsim_base, DSIM_TRANSFER_BOTH, DSIM_STATE_STOP);
943 dev_info(dsim->dev, "DSI Master is already init\n");
949 static unsigned char s5p_dsim_set_hs_enable(struct dsim_global *dsim)
952 unsigned int dsim_base = dsim->reg_base;
954 if (dsim->state == DSIM_STATE_STOP) {
955 if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
956 dsim->state = DSIM_STATE_HSCLKEN;
957 s5p_dsim_set_data_mode(dsim_base, DSIM_TRANSFER_BOTH, DSIM_STATE_HSCLKEN);
958 s5p_dsim_enable_hs_clock(dsim_base, 1);
962 dev_warn(dsim->dev, "clock source is external bypass\n");
964 dev_warn(dsim->dev, "DSIM is not stop state\n");
970 static unsigned char s5p_dsim_set_stopstate(struct dsim_global *dsim)
973 unsigned int dsim_base = dsim->reg_base;
975 if (dsim->state == DSIM_STATE_HSCLKEN) {
976 if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
977 dsim->state = DSIM_STATE_STOP;
978 s5p_dsim_enable_hs_clock(dsim_base, 0);
981 dev_warn(dsim->dev, "clock source is external bypass\n");
982 } else if (dsim->state == DSIM_STATE_ULPS) {
983 /* will be update for exiting ulps */
985 } else if (dsim->state == DSIM_STATE_STOP) {
986 dev_warn(dsim->dev, "DSIM is already stop state\n");
989 dev_warn(dsim->dev, "DSIM is not stop state\n");
995 static unsigned char s5p_dsim_set_data_transfer_mode(struct dsim_global *dsim,
996 unsigned char data_path, unsigned char hs_enable)
999 unsigned int dsim_base = dsim->reg_base;
1002 if (dsim->state == DSIM_STATE_HSCLKEN) {
1003 s5p_dsim_set_data_mode(dsim_base, data_path, DSIM_STATE_HSCLKEN);
1006 dev_err(dsim->dev, "HS Clock lane is not enabled\n");
1010 if (dsim->state == DSIM_STATE_INIT || dsim->state == DSIM_STATE_ULPS) {
1011 dev_err(dsim->dev, "DSI Master is not STOP or HSDT state\n");
1014 s5p_dsim_set_data_mode(dsim_base, data_path, DSIM_STATE_STOP);
1022 int s5p_dsim_register_lcd_driver(struct mipi_lcd_driver *lcd_drv)
1024 struct mipi_lcd_info *lcd_info = NULL;
1025 struct dsim_global *dsim = g_dsim;
1027 lcd_info = kmalloc(sizeof(struct mipi_lcd_info), GFP_KERNEL);
1028 if (lcd_info == NULL)
1031 lcd_info->mipi_drv = kmalloc(sizeof(struct mipi_lcd_driver), GFP_KERNEL);
1032 if (lcd_info->mipi_drv == NULL) {
1037 memcpy(lcd_info->mipi_drv, lcd_drv, sizeof(struct mipi_lcd_driver));
1039 mutex_lock(&mipi_lock);
1040 list_add_tail(&lcd_info->list, &lcd_info_list);
1041 mutex_unlock(&mipi_lock);
1043 dev_dbg(dsim->dev, "registered lcd panel driver(%s) to mipi-dsi driver\n", lcd_drv->name);
1048 static struct mipi_lcd_driver *scan_mipi_driver(struct dsim_global *dsim, const char *name)
1050 struct mipi_lcd_info *lcd_info;
1051 struct mipi_lcd_driver *mipi_drv = NULL;
1053 mutex_lock(&mipi_lock);
1055 dev_dbg(dsim->dev, "find lcd panel driver(%s)\n", name);
1057 list_for_each_entry(lcd_info, &lcd_info_list, list) {
1058 mipi_drv = lcd_info->mipi_drv;
1060 if ((strcmp(mipi_drv->name, name)) == 0) {
1061 mutex_unlock(&mipi_lock);
1062 dev_dbg(dsim->dev, "found!!!(%s)\n", mipi_drv->name);
1067 dev_warn(dsim->dev, "failed to find lcd panel driver(%s)\n", name);
1069 mutex_unlock(&mipi_lock);
1074 static void s5p_dsim_interrupt_mask_set(struct dsim_global *dsim)
1078 int_stat = readl(dsim->reg_base + S5P_DSIM_INTMSK);
1080 int_stat &= ~((0x01<<S5P_DSIM_INT_BTA) | (0x01<<S5P_DSIM_INT_RX_TIMEOUT) |
1081 (0x01<<S5P_DSIM_INT_BTA_TIMEOUT) | (0x01 << S5P_DSIM_INT_RX_DONE) |
1082 (0x01<<S5P_DSIM_INT_RX_TE) | (0x01<<S5P_DSIM_INT_RX_ACK) |
1083 (0x01<<S5P_DSIM_INT_RX_ECC_ERR) | (0x01<<S5P_DSIM_IMT_RX_CRC_ERR) |
1084 (0x01<<S5P_DSIM_INT_SFR_FIFO_EMPTY));
1086 writel(int_stat, dsim->reg_base + S5P_DSIM_INTMSK);
1089 static int s5p_dsim_fifo_clear(struct dsim_global *dsim)
1091 int dsim_count = 0, ret;
1093 writel(SwRstRelease, dsim->reg_base + S5P_DSIM_INTSRC);
1095 writel(DSIM_FUNCRST, dsim->reg_base + S5P_DSIM_SWRST);
1098 if (++dsim_count > 90000) {
1099 dev_err(dsim->dev, "dsim fifo clear fail re_try dsim resume\n");
1104 if (readl(dsim->reg_base + S5P_DSIM_INTSRC) & SwRstRelease) {
1113 #ifdef CONFIG_HAS_EARLYSUSPEND
1114 void s5p_dsim_early_suspend(void)
1118 struct dsim_global *dsim = g_dsim;
1120 dev_info(dsim->dev, "+%s\n", __func__);
1122 if (dsim->mipi_ddi_pd->resume_complete == 0)
1125 dsim->mipi_ddi_pd->resume_complete = 0;
1126 dsim->dsim_lcd_info->lcd_enabled = 0;
1128 /* int_stat = readl(dsim->reg_base + S5P_DSIM_INTMSK); */
1130 int_stat |= ((0x01<<S5P_DSIM_INT_BTA) | (0x01<<S5P_DSIM_INT_RX_TIMEOUT) |
1131 (0x01<<S5P_DSIM_INT_BTA_TIMEOUT) | (0x01 << S5P_DSIM_INT_RX_DONE) |
1132 (0x01<<S5P_DSIM_INT_RX_TE) | (0x01<<S5P_DSIM_INT_RX_ACK) |
1133 (0x01<<S5P_DSIM_INT_RX_ECC_ERR) | (0x01<<S5P_DSIM_IMT_RX_CRC_ERR) |
1134 (0x01<<S5P_DSIM_INT_SFR_FIFO_EMPTY) | (0x01 << S5P_DSIM_INT_MSK_FRAME_DONE));
1136 writel(int_stat, dsim->reg_base + S5P_DSIM_INTMSK);
1138 /* disable_irq(dsim->irq); */
1139 state.event = PM_EVENT_SUSPEND;
1141 if (dsim->mipi_drv->suspend)
1142 dsim->mipi_drv->suspend(dsim->dev, state);
1144 if (dsim->mipi_ddi_pd->lcd_power_on)
1145 dsim->mipi_ddi_pd->lcd_power_on(dsim->dev, 0);
1147 s5p_dsim_enable_hs_clock(dsim->reg_base, 0);
1148 s5p_dsim_set_clock(dsim, dsim->dsim_info->e_byte_clk, 0);
1150 #if defined(CONFIG_CPU_EXYNOS4210)
1151 writel(0x1, dsim->reg_base + S5P_DSIM_SWRST);
1154 if (dsim->pd->exit_d_phy)
1155 dsim->pd->exit_d_phy(dsim->reg_base);
1157 clk_disable(dsim->clock);
1159 if (dsim->pd->mipi_power)
1160 dsim->pd->mipi_power(0);
1162 dev_info(dsim->dev, "-%s\n", __func__);
1167 void s5p_dsim_late_resume(void)
1169 struct dsim_global *dsim = g_dsim;
1171 dev_info(dsim->dev, "+%s\n", __func__);
1173 /* MIPI SIGNAL ON */
1174 if (dsim->pd->mipi_power)
1175 dsim->pd->mipi_power(1);
1177 clk_enable(dsim->clock);
1178 usleep_range(10000, 10000);
1180 if (dsim->mipi_ddi_pd->lcd_power_on)
1181 dsim->mipi_ddi_pd->lcd_power_on(dsim->dev, 1);
1182 usleep_range(25000, 25000);
1184 if (dsim->mipi_ddi_pd->lcd_reset)
1185 dsim->mipi_ddi_pd->lcd_reset();
1186 usleep_range(5000, 5000);
1188 s5p_dsim_late_resume_init_dsim(dsim);
1189 s5p_dsim_init_link(dsim);
1190 usleep_range(10000, 10000);
1191 s5p_dsim_set_hs_enable(dsim);
1192 s5p_dsim_set_data_transfer_mode(dsim, DSIM_TRANSFER_BYCPU, 1);
1193 s5p_dsim_set_display_mode(dsim, dsim->dsim_lcd_info, NULL);
1194 s5p_dsim_set_data_transfer_mode(dsim, DSIM_TRANSFER_BYLCDC, 1);
1195 /* s5p_dsim_set_interrupt_mask(dsim->reg_base, AllDsimIntr, 0); */
1197 #if defined(CONFIG_CPU_EXYNOS4210)
1198 if (s5p_dsim_fifo_clear(dsim) == 0)
1199 dev_err(dsim->dev, "dsim fifo clear fail!!!\n");
1202 s5p_dsim_interrupt_mask_set(dsim);
1204 dsim->mipi_ddi_pd->resume_complete = 1;
1206 dev_info(dsim->dev, "-%s\n", __func__);
1213 static int s5p_dsim_suspend(struct platform_device *pdev, pm_message_t state)
1215 struct dsim_global *dsim = platform_get_drvdata(pdev);
1217 dev_info(&pdev->dev, "%s\n", __func__);
1219 dsim->mipi_ddi_pd->resume_complete = 0;
1221 if (dsim->mipi_drv->suspend)
1222 dsim->mipi_drv->suspend(&pdev->dev, state);
1224 dev_warn(&pdev->dev, "suspend func is null\n");
1226 clk_disable(dsim->clock);
1228 if (dsim->pd->mipi_power)
1229 dsim->pd->mipi_power(0);
1231 dev_warn(&pdev->dev, "mipi_power func is null\n");
1236 static int s5p_dsim_resume(struct platform_device *pdev)
1240 struct dsim_global *dsim = platform_get_drvdata(pdev);
1242 dev_info(&pdev->dev, "%s\n", __func__);
1244 if (dsim->pd->mipi_power)
1245 dsim->pd->mipi_power(1);
1247 dev_warn(&pdev->dev, "mipi_power func is null\n");
1249 usleep_range(10000, 10000);
1251 clk_enable(dsim->clock);
1253 if (dsim->mipi_drv->resume)
1254 dsim->mipi_drv->resume(&pdev->dev);
1256 dev_warn(&pdev->dev, "resume func is null\n");
1258 s5p_dsim_init_dsim(dsim);
1259 s5p_dsim_init_link(dsim);
1261 s5p_dsim_set_hs_enable(dsim);
1262 s5p_dsim_set_data_transfer_mode(dsim, DSIM_TRANSFER_BYCPU, 1);
1266 /* initialize lcd panel */
1267 if (dsim->mipi_drv->init)
1268 dsim->mipi_drv->init(&pdev->dev);
1270 dev_warn(&pdev->dev, "init func is null\n");
1272 s5p_dsim_set_display_mode(dsim, dsim->dsim_lcd_info, NULL);
1274 s5p_dsim_set_data_transfer_mode(dsim, DSIM_TRANSFER_BYLCDC, 1);
1276 int_stat = readl(dsim->reg_base + S5P_DSIM_INTMSK);
1278 int_stat &= ~((0x01<<S5P_DSIM_INT_BTA) | (0x01<<S5P_DSIM_INT_RX_TIMEOUT) |
1279 (0x01<<S5P_DSIM_INT_BTA_TIMEOUT) | (0x01 << S5P_DSIM_INT_RX_DONE) |
1280 (0x01<<S5P_DSIM_INT_RX_TE) | (0x01<<S5P_DSIM_INT_RX_ACK) |
1281 (0x01<<S5P_DSIM_INT_RX_ECC_ERR) | (0x01<<S5P_DSIM_IMT_RX_CRC_ERR) |
1282 (0x01<<S5P_DSIM_INT_SFR_FIFO_EMPTY));
1284 writel(int_stat, dsim->reg_base + S5P_DSIM_INTMSK);
1286 dsim->mipi_ddi_pd->resume_complete = 1;
1291 #define s5p_dsim_suspend NULL
1292 #define s5p_dsim_resume NULL
1296 u32 read_dsim_register(u32 num)
1298 struct dsim_global *dsim = g_dsim;
1300 return readl(dsim->reg_base + (num*4));
1303 static ssize_t hs_toggle_show(struct device *dev,
1304 struct device_attribute *attr, char *buf)
1307 struct dsim_global *dsim = container_of(dev, struct dsim_global, panel);
1309 sprintf(temp, "%d\n", jiffies_to_msecs(dsim->dsim_info->hs_toggle));
1315 static int hs_toggle_store(struct device *dev,
1316 struct device_attribute *attr, const char *buf, size_t size)
1320 struct dsim_global *dsim = container_of(dev, struct dsim_global, panel);
1322 rc = strict_strtoul(buf, (unsigned int)0, (unsigned long *)&value);
1326 dev_info(dev, "%s - %d, %d\n", __func__, jiffies_to_msecs(dsim->dsim_info->hs_toggle), value);
1329 dsim->dsim_info->hs_toggle = msecs_to_jiffies(3000);
1331 dsim->dsim_info->hs_toggle = 0;
1336 static DEVICE_ATTR(hs_toggle, 0644, hs_toggle_show, hs_toggle_store);
1338 static ssize_t dsim_dump_show(struct device *dev,
1339 struct device_attribute *attr, char *buf)
1343 struct dsim_global *dsim = dev_get_drvdata(dev);
1345 for (i = 0; i < 25; i++) {
1346 reg_val = readl(dsim->reg_base + i*4);
1347 sprintf(temp, "[DSIM]0x11C8_00%02X = 0x%08X\n", (i*4), reg_val);
1353 static DEVICE_ATTR(dsim_dump, 0444, dsim_dump_show, NULL);
1355 static struct dsim_ops s5p_dsim_ops = {
1356 .cmd_write = s5p_dsim_wr_data,
1357 .cmd_read = s5p_dsim_rd_data,
1358 .cmd_dcs_read = s5p_dsim_dcs_rd_data,
1359 .suspend = s5p_dsim_early_suspend,
1360 .resume = s5p_dsim_late_resume,
1363 static int s5p_dsim_probe(struct platform_device *pdev)
1365 struct resource *res;
1368 struct dsim_global *dsim;
1370 dsim = kzalloc(sizeof(struct dsim_global), GFP_KERNEL);
1372 pr_err("failed to allocate for dsim_global\n");
1379 dsim->pd = to_dsim_plat(&pdev->dev);
1381 dev_err(&pdev->dev, "platform data is NULL\n");
1386 dsim->dev = &pdev->dev;
1388 /* set dsim config data, dsim lcd config data and lcd panel data. */
1389 dsim->dsim_info = dsim->pd->dsim_info;
1390 dsim->dsim_lcd_info = dsim->pd->dsim_lcd_info;
1391 dsim->lcd_panel_info = (struct s3cfb_lcd *) dsim->dsim_lcd_info->lcd_panel_info;
1392 dsim->mipi_ddi_pd = (struct mipi_ddi_platform_data *) dsim->dsim_lcd_info->mipi_ddi_pd;
1393 dsim->mipi_ddi_pd->te_irq = dsim->pd->te_irq;
1395 if (dsim->pd->mipi_power)
1396 dsim->pd->mipi_power(1);
1398 strcpy(dsim->pd->lcd_panel_name, dsim->lcd_panel_info->name);
1401 dsim->clock = clk_get(&pdev->dev, dsim->pd->clk_name);
1402 if (IS_ERR(dsim->clock)) {
1403 dev_err(&pdev->dev, "failed to get dsim clock source\n");
1408 clk_enable(dsim->clock);
1411 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1413 dev_err(&pdev->dev, "failed to get io memory region\n");
1415 goto err_clk_disable;
1418 /* request mem region */
1419 res = request_mem_region(res->start,
1420 res->end - res->start + 1, pdev->name);
1422 dev_err(&pdev->dev, "failed to request io memory region\n");
1424 goto err_clk_disable;
1427 /* ioremap for register block */
1428 dsim->reg_base = (unsigned int)ioremap(res->start,
1429 res->end - res->start + 1);
1430 if (!dsim->reg_base) {
1431 dev_err(&pdev->dev, "failed to remap io region\n");
1433 goto err_clk_disable;
1436 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1438 dev_err(&pdev->dev, "failed to request dsim irq resource\n");
1440 goto err_clk_disable;
1442 /* dsim->irq = res->start; */
1444 /* clear interrupt */
1445 /* int_stat = readl(dsim->reg_base + S5P_DSIM_INTSRC); */
1446 int_stat = 0xffffffff;
1447 writel(int_stat, dsim->reg_base + S5P_DSIM_INTSRC);
1449 /* enable interrupts */
1450 int_stat = readl(dsim->reg_base + S5P_DSIM_INTMSK);
1452 int_stat &= ~((0x01<<S5P_DSIM_INT_BTA) | (0x01<<S5P_DSIM_INT_RX_TIMEOUT) |
1453 (0x01<<S5P_DSIM_INT_BTA_TIMEOUT) | (0x01 << S5P_DSIM_INT_RX_DONE) |
1454 (0x01<<S5P_DSIM_INT_RX_TE) | (0x01<<S5P_DSIM_INT_RX_ACK) |
1455 (0x01<<S5P_DSIM_INT_RX_ECC_ERR) | (0x01<<S5P_DSIM_IMT_RX_CRC_ERR) |
1456 (0x01<<S5P_DSIM_INT_SFR_FIFO_EMPTY));
1458 writel(int_stat, dsim->reg_base + S5P_DSIM_INTMSK);
1460 init_completion(&dsim_rd_comp);
1461 init_completion(&dsim_wr_comp);
1462 mutex_init(&dsim_rd_wr_mutex);
1464 dsim->mipi_ddi_pd->resume_complete = 1;
1465 dsim->dsim_lcd_info->lcd_enabled = 1;
1467 ret = request_irq(res->start, (void *)s5p_dsim_isr, IRQF_DISABLED, pdev->name, dsim);
1469 dev_err(&pdev->dev, "failed to request dsim irq\n");
1471 goto err_clk_disable;
1474 INIT_DELAYED_WORK(&dsim->dsim_work, dsim_work_q_handler);
1475 INIT_DELAYED_WORK(&dsim->check_hs_toggle_work, dsim_check_hs_toggle_work_q_handler);
1477 dsim->ops = &s5p_dsim_ops;
1479 platform_set_drvdata(pdev, dsim);
1481 dsim->panel.parent = &pdev->dev;
1482 dev_set_name(&dsim->panel, dsim->pd->lcd_panel_name);
1483 ret = device_register(&dsim->panel);
1485 dev_err(&pdev->dev, "faild device register\n");
1490 /* find lcd panel driver registered to mipi-dsi driver. */
1491 dsim->mipi_drv = scan_mipi_driver(dsim, dsim->pd->lcd_panel_name);
1492 if (dsim->mipi_drv == NULL) {
1493 dev_err(&pdev->dev, "mipi_drv is NULL\n");
1498 ret = dsim->mipi_drv->probe(&dsim->panel);
1500 dev_err(&pdev->dev, "faild probe\n");
1505 dsim->state = DSIM_STATE_HSCLKEN;
1507 ret = device_create_file(&(pdev->dev), &dev_attr_dsim_dump);
1509 dev_err(&pdev->dev, "failed to add sysfs entries, %d\n", __LINE__);
1511 if (!dsim->dsim_info->hs_toggle) {
1512 ret = device_create_file(&dsim->panel, &dev_attr_hs_toggle);
1514 dev_err(&pdev->dev, "failed to add sysfs entries, %d\n", __LINE__);
1517 if (dsim->dsim_info->hs_toggle)
1518 s5p_dsim_frame_done_interrupt_enable(dsim, 1);
1520 dev_info(&pdev->dev, "mipi-dsi driver has been probed\n");
1523 #ifdef CONFIG_HAS_WAKELOCK
1524 #ifdef CONFIG_HAS_EARLYSUSPEND
1525 dsim->early_suspend.suspend = s5p_dsim_early_suspend;
1526 dsim->early_suspend.resume = s5p_dsim_late_resume;
1527 dsim->early_suspend.level = EARLY_SUSPEND_LEVEL_DISABLE_FB - 1;
1528 register_early_suspend(&dsim->early_suspend);
1535 free_irq(res->start, &dsim);
1536 dsim->pd->mipi_power(0);
1539 clk_disable(dsim->clock);
1549 static int s5p_dsim_remove(struct platform_device *pdev)
1554 static struct platform_driver s5p_dsim_driver = {
1555 .probe = s5p_dsim_probe,
1556 .remove = s5p_dsim_remove,
1557 #ifndef CONFIG_HAS_EARLYSUSPEND
1558 .suspend = s5p_dsim_suspend,
1559 .resume = s5p_dsim_resume,
1563 .owner = THIS_MODULE,
1567 static int s5p_dsim_register(void)
1569 return platform_driver_register(&s5p_dsim_driver);
1572 static void s5p_dsim_unregister(void)
1574 platform_driver_unregister(&s5p_dsim_driver);
1577 module_init(s5p_dsim_register);
1578 module_exit(s5p_dsim_unregister);
1580 MODULE_AUTHOR("InKi Dae <inki.dae@samsung.com>");
1581 MODULE_DESCRIPTION("Samusung MIPI-DSIM driver");
1582 MODULE_LICENSE("GPL");