drivers/ram/stm32mp1/stm32mp1_ram.c

   1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
   2 /*
   3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
   4  */
   5
   6 #define LOG_CATEGORY UCLASS_RAM
   7
   8 #include <common.h>
   9 #include <clk.h>
  10 #include <dm.h>
  11 #include <init.h>
  12 #include <log.h>
  13 #include <ram.h>
  14 #include <regmap.h>
  15 #include <syscon.h>
  16 #include <asm/io.h>
  17 #include <dm/device_compat.h>
  18 #include "stm32mp1_ddr.h"
  19
  20 static const char *const clkname[] = {
  21         "ddrc1",
  22         "ddrc2",
  23         "ddrcapb",
  24         "ddrphycapb",
  25         "ddrphyc" /* LAST clock => used for get_rate() */
  26 };
  27
  28 int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
  29 {
  30         unsigned long ddrphy_clk;
  31         unsigned long ddr_clk;
  32         struct clk clk;
  33         int ret;
  34         unsigned int idx;
  35
  36         for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
  37                 ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
  38
  39                 if (!ret)
  40                         ret = clk_enable(&clk);
  41
  42                 if (ret) {
  43                         log_err("error for %s : %d\n", clkname[idx], ret);
  44                         return ret;
  45                 }
  46         }
  47
  48         priv->clk = clk;
  49         ddrphy_clk = clk_get_rate(&priv->clk);
  50
  51         log_debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
  52                   mem_speed, (u32)(ddrphy_clk / 1000));
  53         /* max 10% frequency delta */
  54         ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
  55         if (ddr_clk > (mem_speed * 100)) {
  56                 log_err("DDR expected freq %d kHz, current is %d kHz\n",
  57                         mem_speed, (u32)(ddrphy_clk / 1000));
  58                 return -EINVAL;
  59         }
  60
  61         return 0;
  62 }
  63
  64 __weak int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
  65                                                 const char *name)
  66 {
  67         return 0;       /* Always match */
  68 }
  69
  70 static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev)
  71 {
  72         const char *name;
  73         ofnode node;
  74
  75         dev_for_each_subnode(node, dev) {
  76                 name = ofnode_get_property(node, "compatible", NULL);
  77
  78                 if (!board_stm32mp1_ddr_config_name_match(dev, name))
  79                         return node;
  80         }
  81
  82         return dev_ofnode(dev);
  83 }
  84
  85 static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
  86 {
  87         struct ddr_info *priv = dev_get_priv(dev);
  88         int ret;
  89         unsigned int idx;
  90         struct clk axidcg;
  91         struct stm32mp1_ddr_config config;
  92         ofnode node = stm32mp1_ddr_get_ofnode(dev);
  93
  94 #define PARAM(x, y, z)                                                  \
  95         {       .name = x,                                              \
  96                 .offset = offsetof(struct stm32mp1_ddr_config, y),      \
  97                 .size = sizeof(config.y) / sizeof(u32),                 \
  98         }
  99
 100 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
 101 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
 102
 103         const struct {
 104                 const char *name; /* name in DT */
 105                 const u32 offset; /* offset in config struct */
 106                 const u32 size;   /* size of parameters */
 107         } param[] = {
 108                 CTL_PARAM(reg),
 109                 CTL_PARAM(timing),
 110                 CTL_PARAM(map),
 111                 CTL_PARAM(perf),
 112                 PHY_PARAM(reg),
 113                 PHY_PARAM(timing)
 114         };
 115
 116         config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
 117         config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
 118         config.info.name = ofnode_read_string(node, "st,mem-name");
 119         if (!config.info.name) {
 120                 dev_dbg(dev, "no st,mem-name\n");
 121                 return -EINVAL;
 122         }
 123         printf("RAM: %s\n", config.info.name);
 124
 125         for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
 126                 ret = ofnode_read_u32_array(node, param[idx].name,
 127                                          (void *)((u32)&config +
 128                                                   param[idx].offset),
 129                                          param[idx].size);
 130                 dev_dbg(dev, "%s: %s[0x%x] = %d\n", __func__,
 131                         param[idx].name, param[idx].size, ret);
 132                 if (ret) {
 133                         dev_err(dev, "Cannot read %s, error=%d\n",
 134                                 param[idx].name, ret);
 135                         return -EINVAL;
 136                 }
 137         }
 138
 139         ret = clk_get_by_name(dev, "axidcg", &axidcg);
 140         if (ret) {
 141                 dev_dbg(dev, "%s: Cannot found axidcg\n", __func__);
 142                 return -EINVAL;
 143         }
 144         clk_disable(&axidcg); /* disable clock gating during init */
 145
 146         stm32mp1_ddr_init(priv, &config);
 147
 148         clk_enable(&axidcg); /* enable clock gating */
 149
 150         /* check size */
 151         dev_dbg(dev, "get_ram_size(%x, %x)\n",
 152                 (u32)priv->info.base, (u32)STM32_DDR_SIZE);
 153
 154         priv->info.size = get_ram_size((long *)priv->info.base,
 155                                        STM32_DDR_SIZE);
 156
 157         dev_dbg(dev, "info.size: %x\n", (u32)priv->info.size);
 158
 159         /* check memory access for all memory */
 160         if (config.info.size != priv->info.size) {
 161                 printf("DDR invalid size : 0x%x, expected 0x%x\n",
 162                        priv->info.size, config.info.size);
 163                 return -EINVAL;
 164         }
 165         return 0;
 166 }
 167
 168 static int stm32mp1_ddr_probe(struct udevice *dev)
 169 {
 170         struct ddr_info *priv = dev_get_priv(dev);
 171         struct regmap *map;
 172         int ret;
 173
 174         priv->dev = dev;
 175
 176         ret = regmap_init_mem(dev_ofnode(dev), &map);
 177         if (ret)
 178                 return log_ret(ret);
 179
 180         priv->ctl = regmap_get_range(map, 0);
 181         priv->phy = regmap_get_range(map, 1);
 182
 183         priv->rcc = STM32_RCC_BASE;
 184
 185         priv->info.base = STM32_DDR_BASE;
 186
 187         if (IS_ENABLED(CONFIG_SPL_BUILD)) {
 188                 priv->info.size = 0;
 189                 ret = stm32mp1_ddr_setup(dev);
 190
 191                 return log_ret(ret);
 192         }
 193
 194         ofnode node = stm32mp1_ddr_get_ofnode(dev);
 195         priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
 196         return 0;
 197 }
 198
 199 static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
 200 {
 201         struct ddr_info *priv = dev_get_priv(dev);
 202
 203         *info = priv->info;
 204
 205         return 0;
 206 }
 207
 208 static struct ram_ops stm32mp1_ddr_ops = {
 209         .get_info = stm32mp1_ddr_get_info,
 210 };
 211
 212 static const struct udevice_id stm32mp1_ddr_ids[] = {
 213         { .compatible = "st,stm32mp1-ddr" },
 214         { }
 215 };
 216
 217 U_BOOT_DRIVER(ddr_stm32mp1) = {
 218         .name = "stm32mp1_ddr",
 219         .id = UCLASS_RAM,
 220         .of_match = stm32mp1_ddr_ids,
 221         .ops = &stm32mp1_ddr_ops,
 222         .probe = stm32mp1_ddr_probe,
 223         .priv_auto      = sizeof(struct ddr_info),
 224 };