1 // SPDX-License-Identifier: GPL-2.0+
3 * Atmel DataFlash probing
5 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
6 * Haikun Wang (haikun.wang@freescale.com)
15 #include <spi_flash.h>
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/math64.h>
21 #include "sf_internal.h"
23 #define CMD_READ_ID 0x9f
24 /* reads can bypass the buffers */
25 #define OP_READ_CONTINUOUS 0xE8
26 #define OP_READ_PAGE 0xD2
28 /* group B requests can run even while status reports "busy" */
29 #define OP_READ_STATUS 0xD7 /* group B */
31 /* move data between host and buffer */
32 #define OP_READ_BUFFER1 0xD4 /* group B */
33 #define OP_READ_BUFFER2 0xD6 /* group B */
34 #define OP_WRITE_BUFFER1 0x84 /* group B */
35 #define OP_WRITE_BUFFER2 0x87 /* group B */
38 #define OP_ERASE_PAGE 0x81
39 #define OP_ERASE_BLOCK 0x50
41 /* move data between buffer and flash */
42 #define OP_TRANSFER_BUF1 0x53
43 #define OP_TRANSFER_BUF2 0x55
44 #define OP_MREAD_BUFFER1 0xD4
45 #define OP_MREAD_BUFFER2 0xD6
46 #define OP_MWERASE_BUFFER1 0x83
47 #define OP_MWERASE_BUFFER2 0x86
48 #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
49 #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
51 /* write to buffer, then write-erase to flash */
52 #define OP_PROGRAM_VIA_BUF1 0x82
53 #define OP_PROGRAM_VIA_BUF2 0x85
55 /* compare buffer to flash */
56 #define OP_COMPARE_BUF1 0x60
57 #define OP_COMPARE_BUF2 0x61
59 /* read flash to buffer, then write-erase to flash */
60 #define OP_REWRITE_VIA_BUF1 0x58
61 #define OP_REWRITE_VIA_BUF2 0x59
64 * newer chips report JEDEC manufacturer and device IDs; chip
65 * serial number and OTP bits; and per-sector writeprotect.
67 #define OP_READ_ID 0x9F
68 #define OP_READ_SECURITY 0x77
69 #define OP_WRITE_SECURITY_REVC 0x9A
70 #define OP_WRITE_SECURITY 0x9B /* revision D */
72 #define DATAFLASH_SHIFT_EXTID 24
73 #define DATAFLASH_SHIFT_ID 40
77 unsigned short page_offset; /* offset in flash address */
80 /* Return the status of the DataFlash device */
81 static inline int dataflash_status(struct spi_slave *spi)
84 u8 opcode = OP_READ_STATUS;
88 * NOTE: at45db321c over 25 MHz wants to write
89 * a dummy byte after the opcode...
91 ret = spi_write_then_read(spi, &opcode, 1, NULL, &status, 1);
92 return ret ? -EIO : status;
96 * Poll the DataFlash device until it is READY.
97 * This usually takes 5-20 msec or so; more for sector erase.
100 static int dataflash_waitready(struct spi_slave *spi)
103 int timeout = 2 * CONFIG_SYS_HZ;
106 timebase = get_timer(0);
108 status = dataflash_status(spi);
112 if (status & (1 << 7)) /* RDY/nBSY */
116 } while (get_timer(timebase) < timeout);
121 /* Erase pages of flash */
122 static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
124 struct dataflash *dataflash;
125 struct spi_flash *spi_flash;
126 struct spi_slave *spi;
132 dataflash = dev_get_priv(dev);
133 spi_flash = dev_get_uclass_priv(dev);
134 spi = spi_flash->spi;
136 blocksize = spi_flash->page_size << 3;
138 memset(dataflash->command, 0 , sizeof(dataflash->command));
139 command = dataflash->command;
141 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
143 div_u64_rem(len, spi_flash->page_size, &rem);
145 printf("%s: len(0x%x) isn't the multiple of page size(0x%x)\n",
146 dev->name, len, spi_flash->page_size);
149 div_u64_rem(offset, spi_flash->page_size, &rem);
151 printf("%s: offset(0x%x) isn't the multiple of page size(0x%x)\n",
152 dev->name, offset, spi_flash->page_size);
156 status = spi_claim_bus(spi);
158 debug("dataflash: unable to claim SPI bus\n");
163 unsigned int pageaddr;
166 * Calculate flash page address; use block erase (for speed) if
167 * we're at a block boundary and need to erase the whole block.
169 pageaddr = div_u64(offset, spi_flash->page_size);
170 do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
171 pageaddr = pageaddr << dataflash->page_offset;
173 command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
174 command[1] = (uint8_t)(pageaddr >> 16);
175 command[2] = (uint8_t)(pageaddr >> 8);
178 debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
179 dev->name, do_block ? "block" : "page",
180 command[0], command[1], command[2], command[3],
183 status = spi_write_then_read(spi, command, 4, NULL, NULL, 0);
185 debug("%s: erase send command error!\n", dev->name);
189 status = dataflash_waitready(spi);
191 debug("%s: erase waitready error!\n", dev->name);
199 offset += spi_flash->page_size;
200 len -= spi_flash->page_size;
204 spi_release_bus(spi);
210 * Read from the DataFlash device.
211 * offset : Start offset in flash device
212 * len : Amount to read
213 * buf : Buffer containing the data
215 static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
218 struct dataflash *dataflash;
219 struct spi_flash *spi_flash;
220 struct spi_slave *spi;
225 dataflash = dev_get_priv(dev);
226 spi_flash = dev_get_uclass_priv(dev);
227 spi = spi_flash->spi;
229 memset(dataflash->command, 0 , sizeof(dataflash->command));
230 command = dataflash->command;
232 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
233 debug("READ: (%x) %x %x %x\n",
234 command[0], command[1], command[2], command[3]);
236 /* Calculate flash page/byte address */
237 addr = (((unsigned)offset / spi_flash->page_size)
238 << dataflash->page_offset)
239 + ((unsigned)offset % spi_flash->page_size);
241 status = spi_claim_bus(spi);
243 debug("dataflash: unable to claim SPI bus\n");
248 * Continuous read, max clock = f(car) which may be less than
249 * the peak rate available. Some chips support commands with
250 * fewer "don't care" bytes. Both buffers stay unchanged.
252 command[0] = OP_READ_CONTINUOUS;
253 command[1] = (uint8_t)(addr >> 16);
254 command[2] = (uint8_t)(addr >> 8);
255 command[3] = (uint8_t)(addr >> 0);
257 /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
258 status = spi_write_then_read(spi, command, 8, NULL, buf, len);
260 spi_release_bus(spi);
266 * Write to the DataFlash device.
267 * offset : Start offset in flash device
268 * len : Amount to write
269 * buf : Buffer containing the data
271 int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
274 struct dataflash *dataflash;
275 struct spi_flash *spi_flash;
276 struct spi_slave *spi;
278 unsigned int pageaddr, addr, to, writelen;
279 size_t remaining = len;
280 u_char *writebuf = (u_char *)buf;
281 int status = -EINVAL;
283 dataflash = dev_get_priv(dev);
284 spi_flash = dev_get_uclass_priv(dev);
285 spi = spi_flash->spi;
287 memset(dataflash->command, 0 , sizeof(dataflash->command));
288 command = dataflash->command;
290 debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
292 pageaddr = ((unsigned)offset / spi_flash->page_size);
293 to = ((unsigned)offset % spi_flash->page_size);
294 if (to + len > spi_flash->page_size)
295 writelen = spi_flash->page_size - to;
299 status = spi_claim_bus(spi);
301 debug("dataflash: unable to claim SPI bus\n");
305 while (remaining > 0) {
306 debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
310 * (a) each page in a sector must be rewritten at least
311 * once every 10K sibling erase/program operations.
312 * (b) for pages that are already erased, we could
313 * use WRITE+MWRITE not PROGRAM for ~30% speedup.
314 * (c) WRITE to buffer could be done while waiting for
315 * a previous MWRITE/MWERASE to complete ...
316 * (d) error handling here seems to be mostly missing.
318 * Two persistent bits per page, plus a per-sector counter,
319 * could support (a) and (b) ... we might consider using
320 * the second half of sector zero, which is just one block,
321 * to track that state. (On AT91, that sector should also
322 * support boot-from-DataFlash.)
325 addr = pageaddr << dataflash->page_offset;
327 /* (1) Maybe transfer partial page to Buffer1 */
328 if (writelen != spi_flash->page_size) {
329 command[0] = OP_TRANSFER_BUF1;
330 command[1] = (addr & 0x00FF0000) >> 16;
331 command[2] = (addr & 0x0000FF00) >> 8;
334 debug("TRANSFER: (%x) %x %x %x\n",
335 command[0], command[1], command[2], command[3]);
337 status = spi_write_then_read(spi, command, 4,
340 debug("%s: write(<pagesize) command error!\n",
345 status = dataflash_waitready(spi);
347 debug("%s: write(<pagesize) waitready error!\n",
353 /* (2) Program full page via Buffer1 */
355 command[0] = OP_PROGRAM_VIA_BUF1;
356 command[1] = (addr & 0x00FF0000) >> 16;
357 command[2] = (addr & 0x0000FF00) >> 8;
358 command[3] = (addr & 0x000000FF);
360 debug("PROGRAM: (%x) %x %x %x\n",
361 command[0], command[1], command[2], command[3]);
363 status = spi_write_then_read(spi, command, 4,
364 writebuf, NULL, writelen);
366 debug("%s: write send command error!\n", dev->name);
370 status = dataflash_waitready(spi);
372 debug("%s: write waitready error!\n", dev->name);
376 #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
377 /* (3) Compare to Buffer1 */
378 addr = pageaddr << dataflash->page_offset;
379 command[0] = OP_COMPARE_BUF1;
380 command[1] = (addr & 0x00FF0000) >> 16;
381 command[2] = (addr & 0x0000FF00) >> 8;
384 debug("COMPARE: (%x) %x %x %x\n",
385 command[0], command[1], command[2], command[3]);
387 status = spi_write_then_read(spi, command, 4,
388 writebuf, NULL, writelen);
390 debug("%s: write(compare) send command error!\n",
395 status = dataflash_waitready(spi);
397 /* Check result of the compare operation */
398 if (status & (1 << 6)) {
399 printf("dataflash: write compare page %u, err %d\n",
408 #endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
409 remaining = remaining - writelen;
412 writebuf += writelen;
414 if (remaining > spi_flash->page_size)
415 writelen = spi_flash->page_size;
417 writelen = remaining;
420 spi_release_bus(spi);
425 static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
426 int pagesize, int pageoffset, char revision)
428 struct spi_flash *spi_flash;
429 struct dataflash *dataflash;
431 dataflash = dev_get_priv(dev);
432 spi_flash = dev_get_uclass_priv(dev);
434 dataflash->page_offset = pageoffset;
436 spi_flash->name = name;
437 spi_flash->page_size = pagesize;
438 spi_flash->size = nr_pages * pagesize;
439 spi_flash->erase_size = pagesize;
441 #ifndef CONFIG_SPL_BUILD
442 printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
443 print_size(spi_flash->page_size, ", erase size ");
444 print_size(spi_flash->erase_size, ", total ");
445 print_size(spi_flash->size, "");
446 printf(", revision %c", revision);
453 struct data_flash_info {
457 * JEDEC id has a high byte of zero plus three data bytes:
458 * the manufacturer id, then a two byte device id.
462 /* The size listed here is what works with OP_ERASE_PAGE. */
468 #define SUP_EXTID 0x0004 /* supports extended ID data */
469 #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
470 #define IS_POW2PS 0x0001 /* uses 2^N byte pages */
473 static struct data_flash_info dataflash_data[] = {
475 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
476 * one with IS_POW2PS and the other without. The entry with the
477 * non-2^N byte page size can't name exact chip revisions without
478 * losing backwards compatibility for cmdlinepart.
480 * Those two entries have different name spelling format in order to
481 * show their difference obviously.
482 * The upper case refer to the chip isn't in normal 2^N bytes page-size
484 * The lower case refer to the chip is in normal 2^N bytes page-size
487 * These newer chips also support 128-byte security registers (with
488 * 64 bytes one-time-programmable) and software write-protection.
490 { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
491 { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
493 { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
494 { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
496 { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
497 { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
499 { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
500 { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
502 { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
503 { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
505 { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
507 { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
508 { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
510 { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
511 { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
513 { "AT45DB641E", 0x1f28000100ULL, 32768, 264, 9, SUP_EXTID | SUP_POW2PS},
514 { "at45db641e", 0x1f28000100ULL, 32768, 256, 8, SUP_EXTID | SUP_POW2PS | IS_POW2PS},
517 static struct data_flash_info *jedec_lookup(struct spi_slave *spi,
518 u64 jedec, bool use_extid)
521 struct data_flash_info *info;
524 for (info = dataflash_data;
525 info < dataflash_data + ARRAY_SIZE(dataflash_data);
527 if (use_extid && !(info->flags & SUP_EXTID))
530 if (info->jedec_id == jedec) {
531 if (info->flags & SUP_POW2PS) {
532 status = dataflash_status(spi);
534 debug("dataflash: status error %d\n",
536 return ERR_PTR(status);
539 if (info->flags & IS_POW2PS)
542 if (!(info->flags & IS_POW2PS))
551 return ERR_PTR(-ENODEV);
554 static struct data_flash_info *jedec_probe(struct spi_slave *spi)
558 uint8_t id[sizeof(jedec)] = {0};
559 const unsigned int id_size = 5;
560 struct data_flash_info *info;
561 u8 opcode = CMD_READ_ID;
564 * JEDEC also defines an optional "extended device information"
565 * string for after vendor-specific data, after the three bytes
566 * we use here. Supporting some chips might require using it.
568 * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
569 * That's not an error; only rev C and newer chips handle it, and
570 * only Atmel sells these chips.
572 tmp = spi_write_then_read(spi, &opcode, 1, NULL, id, id_size);
574 printf("dataflash: error %d reading JEDEC ID\n", tmp);
581 jedec = be64_to_cpup((__be64 *)id);
584 * First, try to match device using extended device
587 info = jedec_lookup(spi, jedec >> DATAFLASH_SHIFT_EXTID, true);
591 * If that fails, make another pass using regular ID
594 info = jedec_lookup(spi, jedec >> DATAFLASH_SHIFT_ID, false);
598 * Treat other chips as errors ... we won't know the right page
599 * size (it might be binary) even when we can tell which density
600 * class is involved (legacy chip id scheme).
602 printf("dataflash: JEDEC id 0x%016llx not handled\n", jedec);
603 return ERR_PTR(-ENODEV);
607 * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
608 * or else the ID code embedded in the status bits:
610 * Device Density ID code #Pages PageSize Offset
611 * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
612 * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
613 * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
614 * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
615 * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
616 * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
617 * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
618 * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
620 static int spi_dataflash_probe(struct udevice *dev)
622 struct spi_slave *spi = dev_get_parent_priv(dev);
623 struct spi_flash *spi_flash;
624 struct data_flash_info *info;
627 spi_flash = dev_get_uclass_priv(dev);
628 spi_flash->spi = spi;
629 spi_flash->dev = dev;
631 status = spi_claim_bus(spi);
636 * Try to detect dataflash by JEDEC ID.
637 * If it succeeds we know we have either a C or D part.
638 * D will support power of 2 pagesize option.
639 * Both support the security register, though with different
642 info = jedec_probe(spi);
644 goto err_jedec_probe;
646 status = add_dataflash(dev, info->name, info->nr_pages,
647 info->pagesize, info->pageoffset,
648 (info->flags & SUP_POW2PS) ? 'd' : 'c');
656 * Older chips support only legacy commands, identifing
657 * capacity using bits in the status byte.
659 status = dataflash_status(spi);
660 if (status <= 0 || status == 0xff) {
661 printf("dataflash: read status error %d\n", status);
662 if (status == 0 || status == 0xff)
664 goto err_jedec_probe;
668 * if there's a device there, assume it's dataflash.
669 * board setup should have set spi->max_speed_max to
670 * match f(car) for continuous reads, mode 0 or 3.
672 switch (status & 0x3c) {
673 case 0x0c: /* 0 0 1 1 x x */
674 status = add_dataflash(dev, "AT45DB011B", 512, 264, 9, 0);
676 case 0x14: /* 0 1 0 1 x x */
677 status = add_dataflash(dev, "AT45DB021B", 1024, 264, 9, 0);
679 case 0x1c: /* 0 1 1 1 x x */
680 status = add_dataflash(dev, "AT45DB041x", 2048, 264, 9, 0);
682 case 0x24: /* 1 0 0 1 x x */
683 status = add_dataflash(dev, "AT45DB081B", 4096, 264, 9, 0);
685 case 0x2c: /* 1 0 1 1 x x */
686 status = add_dataflash(dev, "AT45DB161x", 4096, 528, 10, 0);
688 case 0x34: /* 1 1 0 1 x x */
689 status = add_dataflash(dev, "AT45DB321x", 8192, 528, 10, 0);
691 case 0x38: /* 1 1 1 x x x */
693 status = add_dataflash(dev, "AT45DB642x", 8192, 1056, 11, 0);
695 /* obsolete AT45DB1282 not (yet?) supported */
697 printf("dataflash: unsupported device (%x)\n", status & 0x3c);
707 spi_release_bus(spi);
711 static const struct dm_spi_flash_ops spi_dataflash_ops = {
712 .read = spi_dataflash_read,
713 .write = spi_dataflash_write,
714 .erase = spi_dataflash_erase,
717 static const struct udevice_id spi_dataflash_ids[] = {
718 { .compatible = "atmel,at45", },
719 { .compatible = "atmel,dataflash", },
723 U_BOOT_DRIVER(spi_dataflash) = {
724 .name = "spi_dataflash",
725 .id = UCLASS_SPI_FLASH,
726 .of_match = spi_dataflash_ids,
727 .probe = spi_dataflash_probe,
728 .priv_auto = sizeof(struct dataflash),
729 .ops = &spi_dataflash_ops,