2 menuconfig MTD_RAW_NAND
3 bool "Raw NAND Device Support"
6 config SYS_NAND_SELF_INIT
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
12 config SPL_SYS_NAND_SELF_INIT
14 depends on !SPL_NAND_SIMPLE
16 This option, if enabled, provides more flexible and linux-like
17 NAND initialization process, in SPL.
19 config TPL_SYS_NAND_SELF_INIT
21 depends on TPL_NAND_SUPPORT
23 This option, if enabled, provides more flexible and linux-like
24 NAND initialization process, in SPL.
29 config SYS_MAX_NAND_DEVICE
30 int "Maximum number of NAND devices to support"
33 config SYS_NAND_DRIVER_ECC_LAYOUT
34 bool "Omit standard ECC layouts to save space"
36 Omit standard ECC layouts to save space. Select this if your driver
37 is known to provide its own ECC layout.
39 config SYS_NAND_USE_FLASH_BBT
40 bool "Enable BBT (Bad Block Table) support"
42 Enable the BBT (Bad Block Table) usage.
45 bool "Support Atmel NAND controller"
46 select SYS_NAND_SELF_INIT
47 imply SYS_NAND_USE_FLASH_BBT
49 Enable this driver for NAND flash platforms using an Atmel NAND
54 config ATMEL_NAND_HWECC
55 bool "Atmel Hardware ECC"
57 config ATMEL_NAND_HW_PMECC
58 bool "Atmel Programmable Multibit ECC (PMECC)"
59 select ATMEL_NAND_HWECC
61 The Programmable Multibit ECC (PMECC) controller is a programmable
62 binary BCH(Bose, Chaudhuri and Hocquenghem) encoder and decoder.
65 int "PMECC Correctable ECC Bits"
66 depends on ATMEL_NAND_HW_PMECC
69 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
71 config PMECC_SECTOR_SIZE
72 int "PMECC Sector Size"
73 depends on ATMEL_NAND_HW_PMECC
76 Sector size, in bytes, can be 512 or 1024.
78 config SPL_GENERATE_ATMEL_PMECC_HEADER
79 bool "Atmel PMECC Header Generation"
81 select ATMEL_NAND_HWECC
82 select ATMEL_NAND_HW_PMECC
84 Generate Programmable Multibit ECC (PMECC) header for SPL image.
89 bool "Support Broadcom NAND controller"
90 depends on OF_CONTROL && DM && DM_MTD
91 select SYS_NAND_SELF_INIT
93 Enable the driver for NAND flash on platforms using a Broadcom NAND
96 config NAND_BRCMNAND_6368
97 bool "Support Broadcom NAND controller on bcm6368"
98 depends on NAND_BRCMNAND && ARCH_BMIPS
100 Enable support for broadcom nand driver on bcm6368.
102 config NAND_BRCMNAND_6753
103 bool "Support Broadcom NAND controller on bcm6753"
104 depends on NAND_BRCMNAND && BCM6855
106 Enable support for broadcom nand driver on bcm6753.
108 config NAND_BRCMNAND_68360
109 bool "Support Broadcom NAND controller on bcm68360"
110 depends on NAND_BRCMNAND && BCM6856
112 Enable support for broadcom nand driver on bcm68360.
114 config NAND_BRCMNAND_6838
115 bool "Support Broadcom NAND controller on bcm6838"
116 depends on NAND_BRCMNAND && ARCH_BMIPS && SOC_BMIPS_BCM6838
118 Enable support for broadcom nand driver on bcm6838.
120 config NAND_BRCMNAND_6858
121 bool "Support Broadcom NAND controller on bcm6858"
122 depends on NAND_BRCMNAND && BCM6858
124 Enable support for broadcom nand driver on bcm6858.
126 config NAND_BRCMNAND_63158
127 bool "Support Broadcom NAND controller on bcm63158"
128 depends on NAND_BRCMNAND && BCM63158
130 Enable support for broadcom nand driver on bcm63158.
133 bool "Support TI Davinci NAND controller"
134 select SYS_NAND_SELF_INIT if TARGET_DA850EVM
136 Enable this driver for NAND flash controllers available in TI Davinci
137 and Keystone2 platforms
139 config KEYSTONE_RBL_NAND
140 depends on ARCH_KEYSTONE
145 depends on NAND_DAVINCI && ARCH_DAVINCI && SPL_NAND_SUPPORT
149 select SYS_NAND_SELF_INIT
152 config NAND_DENALI_DT
153 bool "Support Denali NAND controller as a DT device"
155 depends on OF_CONTROL && DM_MTD
157 Enable the driver for NAND flash on platforms using a Denali NAND
158 controller as a DT device.
161 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
162 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
163 select SPL_SYS_NAND_SELF_INIT
164 select SYS_NAND_SELF_INIT
167 Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
169 config NAND_FSL_ELBC_DT
170 bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver (DT mode)"
171 depends on NAND_FSL_ELBC
174 bool "Support Freescale Integrated Flash Controller NAND driver"
175 select TPL_SYS_NAND_SELF_INIT if TPL_NAND_SUPPORT
176 select TPL_NAND_INIT if TPL && !TPL_FRAMEWORK
177 select SPL_SYS_NAND_SELF_INIT
178 select SYS_NAND_SELF_INIT
181 Enable the Freescale Integrated Flash Controller NAND driver.
183 config NAND_LPC32XX_MLC
184 bool "Support LPC32XX_MLC controller"
185 select SYS_NAND_SELF_INIT
187 Enable the LPC32XX MLC NAND controller.
189 config NAND_LPC32XX_SLC
190 bool "Support LPC32XX_SLC controller"
192 Enable the LPC32XX SLC NAND controller.
194 config NAND_OMAP_GPMC
195 bool "Support OMAP GPMC NAND controller"
196 depends on ARCH_OMAP2PLUS
198 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
199 GPMC controller is used for parallel NAND flash devices, and can
200 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
201 and BCH16 ECC algorithms.
205 config NAND_OMAP_GPMC_PREFETCH
206 bool "Enable GPMC Prefetch"
209 On OMAP platforms that use the GPMC controller
210 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
211 uses the prefetch mode to speed up read operations.
214 bool "Enable ELM driver for OMAPxx and AMxx platforms."
217 ELM controller is used for ECC error detection (not ECC calculation)
218 of BCH4, BCH8 and BCH16 ECC algorithms.
219 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
220 thus such SoC platforms need to depend on software library for ECC error
221 detection. However ECC calculation on such plaforms would still be
222 done by GPMC controller.
226 default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
228 On OMAP platforms, this CONFIG specifies NAND ECC scheme.
229 It can take following values:
230 OMAP_ECC_HAM1_CODE_SW
231 1-bit Hamming code using software lib.
232 (for legacy devices only)
233 OMAP_ECC_HAM1_CODE_HW
234 1-bit Hamming code using GPMC hardware.
235 (for legacy devices only)
236 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW
237 4-bit BCH code (unsupported)
238 OMAP_ECC_BCH4_CODE_HW
239 4-bit BCH code (unsupported)
240 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
242 - ecc calculation using GPMC hardware engine,
243 - error detection using software library.
244 - requires CONFIG_BCH to enable software BCH library
245 (For legacy device which do not have ELM h/w engine)
246 OMAP_ECC_BCH8_CODE_HW
248 - ecc calculation using GPMC hardware engine,
249 - error detection using ELM hardware engine.
250 OMAP_ECC_BCH16_CODE_HW
252 - ecc calculation using GPMC hardware engine,
253 - error detection using ELM hardware engine.
255 How to select ECC scheme on OMAP and AMxx platforms ?
256 -----------------------------------------------------
257 Though higher ECC schemes have more capability to detect and correct
258 bit-flips, but still selection of ECC scheme is dependent on following
259 - hardware engines present in SoC.
260 Some legacy OMAP SoC do not have ELM h/w engine thus such
261 SoC cannot support BCHx_HW ECC schemes.
262 - size of OOB/Spare region
263 With higher ECC schemes, more OOB/Spare area is required to
264 store ECC. So choice of ECC scheme is limited by NAND oobsize.
266 In general following expression can help:
267 NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
269 NAND_OOBSIZE = number of bytes available in
270 OOB/spare area per NAND page.
271 NAND_PAGESIZE = bytes in main-area of NAND page.
272 ECC_BYTES = number of ECC bytes generated to
273 protect 512 bytes of data, which is:
274 3 for HAM1_xx ecc schemes
275 7 for BCH4_xx ecc schemes
276 14 for BCH8_xx ecc schemes
277 26 for BCH16_xx ecc schemes
279 example to check for BCH16 on 2K page NAND
282 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
283 Thus BCH16 cannot be supported on 2K page NAND.
285 However, for 4K pagesize NAND
289 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
290 Thus BCH16 can be supported on 4K page NAND.
292 config NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
293 bool "1-bit Hamming code using software lib"
295 config NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
296 bool "1-bit Hamming code using GPMC hardware"
298 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
299 bool "8-bit BCH code with HW calculation SW error detection"
301 config NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
302 bool "8-bit BCH code with HW calculation and error detection"
304 config NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
305 bool "16-bit BCH code with HW calculation and error detection"
309 config NAND_OMAP_ECCSCHEME
311 default 1 if NAND_OMAP_ECCSCHEME_HAM1_CODE_SW
312 default 2 if NAND_OMAP_ECCSCHEME_HAM1_CODE_HW
313 default 5 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW_DETECTION_SW
314 default 6 if NAND_OMAP_ECCSCHEME_BCH8_CODE_HW
315 default 7 if NAND_OMAP_ECCSCHEME_BCH16_CODE_HW
317 This must be kept in sync with the enum in
318 include/linux/mtd/omap_gpmc.h
322 config NAND_VF610_NFC
323 bool "Support for Freescale NFC for VF610"
324 select SYS_NAND_SELF_INIT
325 select SYS_NAND_DRIVER_ECC_LAYOUT
328 Enables support for NAND Flash Controller on some Freescale
329 processors like the VF610, MCF54418 or Kinetis K70.
330 The driver supports a maximum 2k page size. The driver
331 currently does not support hardware ECC.
335 config NAND_VF610_NFC_DT
336 bool "Support Vybrid's vf610 NAND controller as a DT device"
337 depends on OF_CONTROL && DM_MTD
339 Enable the driver for Vybrid's vf610 NAND flash on platforms
343 prompt "Hardware ECC strength"
344 depends on NAND_VF610_NFC
345 default SYS_NAND_VF610_NFC_45_ECC_BYTES
347 Select the ECC strength used in the hardware BCH ECC block.
349 config SYS_NAND_VF610_NFC_45_ECC_BYTES
350 bool "24-error correction (45 ECC bytes)"
352 config SYS_NAND_VF610_NFC_60_ECC_BYTES
353 bool "32-error correction (60 ECC bytes)"
360 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
361 select SYS_NAND_SELF_INIT
367 This enables the driver for the NAND flash device found on
368 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
371 bool "Support for NAND on Allwinner SoCs"
373 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
374 select SYS_NAND_SELF_INIT
375 select SYS_NAND_U_BOOT_LOCATIONS
376 select SPL_NAND_SUPPORT
377 select SPL_SYS_NAND_SELF_INIT
380 Enable support for NAND. This option enables the standard and
382 The SPL driver only supports reading from the NAND using DMA
387 config NAND_SUNXI_SPL_ECC_STRENGTH
388 int "Allwinner NAND SPL ECC Strength"
391 config NAND_SUNXI_SPL_ECC_SIZE
392 int "Allwinner NAND SPL ECC Step Size"
395 config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
396 int "Allwinner NAND SPL Usable Page Size"
402 bool "Configure Arasan Nand"
403 select SYS_NAND_SELF_INIT
407 This enables Nand driver support for Arasan nand flash
408 controller. This uses the hardware ECC for read and
412 bool "MXC NAND support"
413 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
416 This enables the NAND driver for the NAND flash controller on the
417 i.MX27 / i.MX31 / i.MX5 processors.
420 bool "MXS NAND support"
421 depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M
422 select SPL_SYS_NAND_SELF_INIT
423 select SYS_NAND_SELF_INIT
426 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
427 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7 || ARCH_IMX8 || ARCH_IMX8M
429 This enables NAND driver for the NAND flash controller on the
435 bool "Support MXS NAND controller as a DT device"
436 depends on OF_CONTROL && DM_MTD
438 Enable the driver for MXS NAND flash on platforms using
441 config NAND_MXS_USE_MINIMUM_ECC
442 bool "Use minimum ECC strength supported by the controller"
448 bool "Macronix raw NAND controller"
449 select SYS_NAND_SELF_INIT
451 This selects the Macronix raw NAND controller driver.
454 bool "Support for Zynq Nand controller"
455 select SPL_SYS_NAND_SELF_INIT
456 select SYS_NAND_SELF_INIT
460 This enables Nand driver support for Nand flash controller
463 config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
464 bool "Enable use of 1st stage bootloader timing for NAND"
467 This flag prevent U-boot reconfigure NAND flash controller and reuse
468 the NAND timing from 1st stage bootloader.
471 bool "Support for OcteonTX NAND controller"
472 select SYS_NAND_SELF_INIT
475 This enables Nand flash controller hardware found on the OcteonTX
478 config NAND_OCTEONTX_HW_ECC
479 bool "Support Hardware ECC for OcteonTX NAND controller"
480 depends on NAND_OCTEONTX
483 This enables Hardware BCH engine found on the OcteonTX processors to
484 support ECC for NAND flash controller.
486 config NAND_STM32_FMC2
487 bool "Support for NAND controller on STM32MP SoCs"
488 depends on ARCH_STM32MP
489 select SYS_NAND_SELF_INIT
492 Enables support for NAND Flash chips on SoCs containing the FMC2
493 NAND controller. This controller is found on STM32MP SoCs.
494 The controller supports a maximum 8k page size and supports
495 a maximum 8-bit correction error per sector of 512 bytes.
498 bool "Support for NAND controller on Cortina-Access SoCs"
499 depends on CORTINA_PLATFORM
500 select SYS_NAND_SELF_INIT
504 Enables support for NAND Flash chips on Coartina-Access SoCs platform
505 This controller is found on Presidio/Venus SoCs.
506 The controller supports a maximum 8k page size and supports
507 a maximum 40-bit error correction per sector of 1024 bytes.
510 bool "Support for NAND controller on Rockchip SoCs"
511 depends on ARCH_ROCKCHIP
512 select SYS_NAND_SELF_INIT
516 Enables support for NAND Flash chips on Rockchip SoCs platform.
517 This controller is found on Rockchip SoCs.
518 There are four different versions of NAND FLASH Controllers,
520 NFC v600: RK2928, RK3066, RK3188
521 NFC v622: RK3036, RK3128
522 NFC v800: RK3308, RV1108
523 NFC v900: PX30, RK3326
526 bool "Support for NAND controller on Tegra SoCs"
527 depends on ARCH_TEGRA
528 select SYS_NAND_SELF_INIT
531 Enables support for NAND Flash chips on Tegra SoCs platforms.
534 bool "Support for MediaTek MT7621 NAND flash controller"
535 depends on SOC_MT7621
536 select SYS_NAND_SELF_INIT
537 select SPL_SYS_NAND_SELF_INIT
540 This enables NAND driver for the NAND flash controller on MediaTek
542 The controller supports 4~12 bits correction per 512 bytes with a
543 maximum 4KB page size.
545 comment "Generic NAND options"
547 config SYS_NAND_BLOCK_SIZE
548 hex "NAND chip eraseblock size"
549 depends on ARCH_SUNXI || SPL_NAND_SUPPORT || TPL_NAND_SUPPORT
550 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && \
551 !NAND_FSL_IFC && !NAND_MT7621
553 Number of data bytes in one eraseblock for the NAND chip on the
554 board. This is the multiple of NAND_PAGE_SIZE and the number of
557 config SYS_NAND_ONFI_DETECTION
558 bool "Enable detection of ONFI compliant devices during probe"
560 Enables detection of ONFI compliant devices during probe.
561 And fetching device parameters flashed on device, by parsing
564 config SYS_NAND_PAGE_COUNT
565 hex "NAND chip page count"
566 depends on SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC || \
567 SPL_NAND_AM33XX_BCH || SPL_NAND_LOAD || SPL_NAND_SIMPLE)
569 Number of pages in the NAND chip.
571 config SYS_NAND_PAGE_SIZE
572 hex "NAND chip page size"
573 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
574 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
575 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
576 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC && !NAND_MT7621
578 Number of data bytes in one page for the NAND chip on the
579 board, not including the OOB area.
581 config SYS_NAND_OOBSIZE
582 hex "NAND chip OOB size"
583 depends on ARCH_SUNXI || NAND_OMAP_GPMC || NAND_LPC32XX_SLC || \
584 SPL_NAND_SIMPLE || (NAND_MXC && SPL_NAND_SUPPORT) || \
585 (NAND_ATMEL && SPL_NAND_SUPPORT) || SPL_GENERATE_ATMEL_PMECC_HEADER
586 depends on !NAND_MXS && !NAND_DENALI_DT && !NAND_LPC32XX_MLC
588 Number of bytes in the Out-Of-Band area for the NAND chip on
591 # Enhance depends when converting drivers to Kconfig which use this config
592 # option (mxc_nand, ndfc, omap_gpmc).
593 config SYS_NAND_BUSWIDTH_16BIT
594 bool "Use 16-bit NAND interface"
595 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
597 Indicates that NAND device has 16-bit wide data-bus. In absence of this
598 config, bus-width of NAND device is assumed to be either 8-bit and later
599 determined by reading ONFI params.
600 Above config is useful when NAND device's bus-width information cannot
601 be determined from on-chip ONFI params, like in following scenarios:
602 - SPL boot does not support reading of ONFI parameters. This is done to
603 keep SPL code foot-print small.
604 - In current U-Boot flow using nand_init(), driver initialization
605 happens in board_nand_init() which is called before any device probe
606 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
607 not available while configuring controller. So a static CONFIG_NAND_xx
608 is needed to know the device's bus-width in advance.
612 config SYS_NAND_5_ADDR_CYCLE
613 bool "Wait 5 address cycles during NAND commands"
614 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_SIMPLE || \
615 (SPL_NAND_SUPPORT && NAND_ATMEL)
618 Some controllers require waiting for 5 address cycles when issuing
619 some commands, on NAND chips larger than 128MiB.
622 prompt "NAND bad block marker/indicator position in the OOB"
623 depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
624 SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
625 default HAS_NAND_LARGE_BADBLOCK_POS
627 In the OOB, which position contains the badblock information.
629 config HAS_NAND_LARGE_BADBLOCK_POS
630 bool "Set the bad block marker/indicator to the 'large' position"
632 config HAS_NAND_SMALL_BADBLOCK_POS
633 bool "Set the bad block marker/indicator to the 'small' position"
637 config SYS_NAND_BAD_BLOCK_POS
639 default 0 if HAS_NAND_LARGE_BADBLOCK_POS
640 default 5 if HAS_NAND_SMALL_BADBLOCK_POS
642 config SYS_NAND_U_BOOT_LOCATIONS
643 bool "Define U-boot binaries locations in NAND"
645 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
646 This option should not be enabled when compiling U-boot for boards
647 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
650 config SYS_NAND_U_BOOT_OFFS
651 hex "Location in NAND to read U-Boot from"
652 default 0x800000 if NAND_SUNXI
653 depends on SYS_NAND_U_BOOT_LOCATIONS
655 Set the offset from the start of the nand where u-boot should be
658 config SYS_NAND_U_BOOT_OFFS_REDUND
659 hex "Location in NAND to read U-Boot from"
660 default SYS_NAND_U_BOOT_OFFS
661 depends on SYS_NAND_U_BOOT_LOCATIONS
663 Set the offset from the start of the nand where the redundant u-boot
664 should be loaded from.
666 config SPL_NAND_AM33XX_BCH
667 bool "Enables SPL-NAND driver which supports ELM based"
668 depends on SPL_NAND_SUPPORT && NAND_OMAP_GPMC && !OMAP34XX
671 Hardware ECC correction. This is useful for platforms which have ELM
672 hardware engine and use NAND boot mode.
673 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
674 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
675 SPL-NAND driver with software ECC correction support.
677 config SPL_NAND_DENALI
678 bool "Support Denali NAND controller for SPL"
679 depends on SPL_NAND_SUPPORT
681 This is a small implementation of the Denali NAND controller
684 config NAND_DENALI_SPARE_AREA_SKIP_BYTES
685 int "Number of bytes skipped in OOB area"
686 depends on SPL_NAND_DENALI
689 This option specifies the number of bytes to skip from the beginning
690 of OOB area before last ECC sector data starts. This is potentially
691 used to preserve the bad block marker in the OOB area.
693 config SPL_NAND_SIMPLE
694 bool "Use simple SPL NAND driver"
695 depends on !SPL_NAND_AM33XX_BCH && SPL_NAND_SUPPORT
697 Support for NAND boot using simple NAND drivers that
698 expose the cmd_ctrl() interface.