2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #include <linux/kernel.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/module.h>
16 #include <linux/ktime.h>
17 #include <linux/hrtimer.h>
18 #include <linux/tick.h>
19 #include <linux/slab.h>
20 #include <linux/sched.h>
21 #include <linux/list.h>
22 #include <linux/cpu.h>
23 #include <linux/cpufreq.h>
24 #include <linux/sysfs.h>
25 #include <linux/types.h>
27 #include <linux/debugfs.h>
28 #include <linux/acpi.h>
29 #include <trace/events/power.h>
31 #include <asm/div64.h>
33 #include <asm/cpu_device_id.h>
35 #define SAMPLE_COUNT 3
37 #define BYT_RATIOS 0x66a
38 #define BYT_VIDS 0x66b
39 #define BYT_TURBO_RATIOS 0x66c
40 #define BYT_TURBO_VIDS 0x66d
44 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
45 #define fp_toint(X) ((X) >> FRAC_BITS)
48 static inline int32_t mul_fp(int32_t x, int32_t y)
50 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
53 static inline int32_t div_fp(int32_t x, int32_t y)
55 return div_s64((int64_t)x << FRAC_BITS, (int64_t)y);
58 static inline int ceiling_fp(int32_t x)
63 mask = (1 << FRAC_BITS) - 1;
70 int32_t core_pct_busy;
107 struct timer_list timer;
109 struct pstate_data pstate;
113 ktime_t last_sample_time;
116 struct sample sample;
119 static struct cpudata **all_cpu_data;
120 struct pstate_adjust_policy {
129 struct pstate_funcs {
130 int (*get_max)(void);
131 int (*get_min)(void);
132 int (*get_turbo)(void);
133 int (*get_scaling)(void);
134 void (*set)(struct cpudata*, int pstate);
135 void (*get_vid)(struct cpudata *);
138 struct cpu_defaults {
139 struct pstate_adjust_policy pid_policy;
140 struct pstate_funcs funcs;
143 static struct pstate_adjust_policy pid_params;
144 static struct pstate_funcs pstate_funcs;
157 static struct perf_limits limits = {
160 .max_perf = int_tofp(1),
163 .max_policy_pct = 100,
164 .max_sysfs_pct = 100,
167 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
168 int deadband, int integral) {
169 pid->setpoint = setpoint;
170 pid->deadband = deadband;
171 pid->integral = int_tofp(integral);
172 pid->last_err = setpoint - busy;
175 static inline void pid_p_gain_set(struct _pid *pid, int percent)
177 pid->p_gain = div_fp(int_tofp(percent), int_tofp(100));
180 static inline void pid_i_gain_set(struct _pid *pid, int percent)
182 pid->i_gain = div_fp(int_tofp(percent), int_tofp(100));
185 static inline void pid_d_gain_set(struct _pid *pid, int percent)
188 pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
191 static signed int pid_calc(struct _pid *pid, int32_t busy)
194 int32_t pterm, dterm, fp_error;
195 int32_t integral_limit;
197 fp_error = int_tofp(pid->setpoint) - busy;
199 if (abs(fp_error) <= int_tofp(pid->deadband))
202 pterm = mul_fp(pid->p_gain, fp_error);
204 pid->integral += fp_error;
206 /* limit the integral term */
207 integral_limit = int_tofp(30);
208 if (pid->integral > integral_limit)
209 pid->integral = integral_limit;
210 if (pid->integral < -integral_limit)
211 pid->integral = -integral_limit;
213 dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
214 pid->last_err = fp_error;
216 result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
217 result = result + (1 << (FRAC_BITS-1));
218 return (signed int)fp_toint(result);
221 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
223 pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
224 pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
225 pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
234 static inline void intel_pstate_reset_all_pid(void)
237 for_each_online_cpu(cpu) {
238 if (all_cpu_data[cpu])
239 intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
243 /************************** debugfs begin ************************/
244 static int pid_param_set(void *data, u64 val)
247 intel_pstate_reset_all_pid();
250 static int pid_param_get(void *data, u64 *val)
255 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get,
256 pid_param_set, "%llu\n");
263 static struct pid_param pid_files[] = {
264 {"sample_rate_ms", &pid_params.sample_rate_ms},
265 {"d_gain_pct", &pid_params.d_gain_pct},
266 {"i_gain_pct", &pid_params.i_gain_pct},
267 {"deadband", &pid_params.deadband},
268 {"setpoint", &pid_params.setpoint},
269 {"p_gain_pct", &pid_params.p_gain_pct},
273 static struct dentry *debugfs_parent;
274 static void intel_pstate_debug_expose_params(void)
278 debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
279 if (IS_ERR_OR_NULL(debugfs_parent))
281 while (pid_files[i].name) {
282 debugfs_create_file(pid_files[i].name, 0660,
283 debugfs_parent, pid_files[i].value,
289 /************************** debugfs end ************************/
291 /************************** sysfs begin ************************/
292 #define show_one(file_name, object) \
293 static ssize_t show_##file_name \
294 (struct kobject *kobj, struct attribute *attr, char *buf) \
296 return sprintf(buf, "%u\n", limits.object); \
299 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
300 const char *buf, size_t count)
304 ret = sscanf(buf, "%u", &input);
307 limits.no_turbo = clamp_t(int, input, 0 , 1);
308 if (limits.turbo_disabled) {
309 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
310 limits.no_turbo = limits.turbo_disabled;
315 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
316 const char *buf, size_t count)
320 ret = sscanf(buf, "%u", &input);
324 limits.max_sysfs_pct = clamp_t(int, input, 0 , 100);
325 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
326 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
330 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
331 const char *buf, size_t count)
335 ret = sscanf(buf, "%u", &input);
338 limits.min_perf_pct = clamp_t(int, input, 0 , 100);
339 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
344 show_one(no_turbo, no_turbo);
345 show_one(max_perf_pct, max_perf_pct);
346 show_one(min_perf_pct, min_perf_pct);
348 define_one_global_rw(no_turbo);
349 define_one_global_rw(max_perf_pct);
350 define_one_global_rw(min_perf_pct);
352 static struct attribute *intel_pstate_attributes[] = {
359 static struct attribute_group intel_pstate_attr_group = {
360 .attrs = intel_pstate_attributes,
362 static struct kobject *intel_pstate_kobject;
364 static void intel_pstate_sysfs_expose_params(void)
368 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
369 &cpu_subsys.dev_root->kobj);
370 BUG_ON(!intel_pstate_kobject);
371 rc = sysfs_create_group(intel_pstate_kobject,
372 &intel_pstate_attr_group);
376 /************************** sysfs end ************************/
377 static int byt_get_min_pstate(void)
380 rdmsrl(BYT_RATIOS, value);
381 return (value >> 8) & 0x7F;
384 static int byt_get_max_pstate(void)
387 rdmsrl(BYT_RATIOS, value);
388 return (value >> 16) & 0x7F;
391 static int byt_get_turbo_pstate(void)
394 rdmsrl(BYT_TURBO_RATIOS, value);
398 static void byt_set_pstate(struct cpudata *cpudata, int pstate)
405 if (limits.no_turbo && !limits.turbo_disabled)
408 vid_fp = cpudata->vid.min + mul_fp(
409 int_tofp(pstate - cpudata->pstate.min_pstate),
412 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
413 vid = ceiling_fp(vid_fp);
415 if (pstate > cpudata->pstate.max_pstate)
416 vid = cpudata->vid.turbo;
420 wrmsrl(MSR_IA32_PERF_CTL, val);
423 #define BYT_BCLK_FREQS 5
424 static int byt_freq_table[BYT_BCLK_FREQS] = { 833, 1000, 1333, 1167, 800};
426 static int byt_get_scaling(void)
431 rdmsrl(MSR_FSB_FREQ, value);
434 BUG_ON(i > BYT_BCLK_FREQS);
436 return byt_freq_table[i] * 100;
439 static void byt_get_vid(struct cpudata *cpudata)
444 rdmsrl(BYT_VIDS, value);
445 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
446 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
447 cpudata->vid.ratio = div_fp(
448 cpudata->vid.max - cpudata->vid.min,
449 int_tofp(cpudata->pstate.max_pstate -
450 cpudata->pstate.min_pstate));
452 rdmsrl(BYT_TURBO_VIDS, value);
453 cpudata->vid.turbo = value & 0x7f;
457 static int core_get_min_pstate(void)
460 rdmsrl(MSR_PLATFORM_INFO, value);
461 return (value >> 40) & 0xFF;
464 static int core_get_max_pstate(void)
467 rdmsrl(MSR_PLATFORM_INFO, value);
468 return (value >> 8) & 0xFF;
471 static int core_get_turbo_pstate(void)
475 rdmsrl(MSR_NHM_TURBO_RATIO_LIMIT, value);
476 nont = core_get_max_pstate();
477 ret = ((value) & 255);
483 static inline int core_get_scaling(void)
488 static void core_set_pstate(struct cpudata *cpudata, int pstate)
493 if (limits.no_turbo && !limits.turbo_disabled)
496 wrmsrl(MSR_IA32_PERF_CTL, val);
499 static struct cpu_defaults core_params = {
501 .sample_rate_ms = 10,
509 .get_max = core_get_max_pstate,
510 .get_min = core_get_min_pstate,
511 .get_turbo = core_get_turbo_pstate,
512 .get_scaling = core_get_scaling,
513 .set = core_set_pstate,
517 static struct cpu_defaults byt_params = {
519 .sample_rate_ms = 10,
527 .get_max = byt_get_max_pstate,
528 .get_min = byt_get_min_pstate,
529 .get_turbo = byt_get_turbo_pstate,
530 .set = byt_set_pstate,
531 .get_scaling = byt_get_scaling,
532 .get_vid = byt_get_vid,
537 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
539 int max_perf = cpu->pstate.turbo_pstate;
543 max_perf = cpu->pstate.max_pstate;
545 max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
546 *max = clamp_t(int, max_perf_adj,
547 cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
549 min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
550 *min = clamp_t(int, min_perf,
551 cpu->pstate.min_pstate, max_perf);
554 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
556 int max_perf, min_perf;
558 intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
560 pstate = clamp_t(int, pstate, min_perf, max_perf);
562 if (pstate == cpu->pstate.current_pstate)
565 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
567 cpu->pstate.current_pstate = pstate;
569 pstate_funcs.set(cpu, pstate);
572 static inline void intel_pstate_pstate_increase(struct cpudata *cpu, int steps)
575 target = cpu->pstate.current_pstate + steps;
577 intel_pstate_set_pstate(cpu, target);
580 static inline void intel_pstate_pstate_decrease(struct cpudata *cpu, int steps)
583 target = cpu->pstate.current_pstate - steps;
584 intel_pstate_set_pstate(cpu, target);
587 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
589 sprintf(cpu->name, "Intel 2nd generation core");
591 cpu->pstate.min_pstate = pstate_funcs.get_min();
592 cpu->pstate.max_pstate = pstate_funcs.get_max();
593 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
594 cpu->pstate.scaling = pstate_funcs.get_scaling();
596 if (pstate_funcs.get_vid)
597 pstate_funcs.get_vid(cpu);
598 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
601 static inline void intel_pstate_calc_busy(struct cpudata *cpu,
602 struct sample *sample)
607 core_pct = int_tofp(sample->aperf) * int_tofp(100);
608 core_pct = div_u64_rem(core_pct, int_tofp(sample->mperf), &rem);
610 if ((rem << 1) >= int_tofp(sample->mperf))
613 sample->freq = fp_toint(
615 cpu->pstate.max_pstate * cpu->pstate.scaling / 100),
618 sample->core_pct_busy = (int32_t)core_pct;
621 static inline void intel_pstate_sample(struct cpudata *cpu)
625 rdmsrl(MSR_IA32_APERF, aperf);
626 rdmsrl(MSR_IA32_MPERF, mperf);
628 aperf = aperf >> FRAC_BITS;
629 mperf = mperf >> FRAC_BITS;
631 cpu->last_sample_time = cpu->sample.time;
632 cpu->sample.time = ktime_get();
633 cpu->sample.aperf = aperf;
634 cpu->sample.mperf = mperf;
635 cpu->sample.aperf -= cpu->prev_aperf;
636 cpu->sample.mperf -= cpu->prev_mperf;
638 intel_pstate_calc_busy(cpu, &cpu->sample);
640 cpu->prev_aperf = aperf;
641 cpu->prev_mperf = mperf;
644 static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
646 int sample_time, delay;
648 sample_time = pid_params.sample_rate_ms;
649 delay = msecs_to_jiffies(sample_time);
650 mod_timer_pinned(&cpu->timer, jiffies + delay);
653 static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
655 int32_t core_busy, max_pstate, current_pstate, sample_ratio;
659 core_busy = cpu->sample.core_pct_busy;
660 max_pstate = int_tofp(cpu->pstate.max_pstate);
661 current_pstate = int_tofp(cpu->pstate.current_pstate);
662 core_busy = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
664 sample_time = (pid_params.sample_rate_ms * USEC_PER_MSEC);
665 duration_us = (u32) ktime_us_delta(cpu->sample.time,
666 cpu->last_sample_time);
667 if (duration_us > sample_time * 3) {
668 sample_ratio = div_fp(int_tofp(sample_time),
669 int_tofp(duration_us));
670 core_busy = mul_fp(core_busy, sample_ratio);
676 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
684 busy_scaled = intel_pstate_get_scaled_busy(cpu);
686 ctl = pid_calc(pid, busy_scaled);
691 intel_pstate_pstate_increase(cpu, steps);
693 intel_pstate_pstate_decrease(cpu, steps);
696 static void intel_pstate_timer_func(unsigned long __data)
698 struct cpudata *cpu = (struct cpudata *) __data;
699 struct sample *sample;
701 intel_pstate_sample(cpu);
703 sample = &cpu->sample;
705 intel_pstate_adjust_busy_pstate(cpu);
707 trace_pstate_sample(fp_toint(sample->core_pct_busy),
708 fp_toint(intel_pstate_get_scaled_busy(cpu)),
709 cpu->pstate.current_pstate,
714 intel_pstate_set_sample_time(cpu);
717 #define ICPU(model, policy) \
718 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
719 (unsigned long)&policy }
721 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
722 ICPU(0x2a, core_params),
723 ICPU(0x2d, core_params),
724 ICPU(0x37, byt_params),
725 ICPU(0x3a, core_params),
726 ICPU(0x3c, core_params),
727 ICPU(0x3d, core_params),
728 ICPU(0x3e, core_params),
729 ICPU(0x3f, core_params),
730 ICPU(0x45, core_params),
731 ICPU(0x46, core_params),
732 ICPU(0x4c, byt_params),
733 ICPU(0x4f, core_params),
734 ICPU(0x56, core_params),
737 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
739 static int intel_pstate_init_cpu(unsigned int cpunum)
742 const struct x86_cpu_id *id;
745 id = x86_match_cpu(intel_pstate_cpu_ids);
749 all_cpu_data[cpunum] = kzalloc(sizeof(struct cpudata), GFP_KERNEL);
750 if (!all_cpu_data[cpunum])
753 cpu = all_cpu_data[cpunum];
756 intel_pstate_get_cpu_pstates(cpu);
758 init_timer_deferrable(&cpu->timer);
759 cpu->timer.function = intel_pstate_timer_func;
762 cpu->timer.expires = jiffies + HZ/100;
763 intel_pstate_busy_pid_reset(cpu);
764 intel_pstate_sample(cpu);
766 add_timer_on(&cpu->timer, cpunum);
768 pr_info("Intel pstate controlling: cpu %d\n", cpunum);
773 static unsigned int intel_pstate_get(unsigned int cpu_num)
775 struct sample *sample;
778 cpu = all_cpu_data[cpu_num];
781 sample = &cpu->sample;
785 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
789 cpu = all_cpu_data[policy->cpu];
791 if (!policy->cpuinfo.max_freq)
794 if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
795 limits.min_perf_pct = 100;
796 limits.min_perf = int_tofp(1);
797 limits.max_policy_pct = 100;
798 limits.max_perf_pct = 100;
799 limits.max_perf = int_tofp(1);
800 limits.no_turbo = limits.turbo_disabled;
803 limits.min_perf_pct = (policy->min * 100) / policy->cpuinfo.max_freq;
804 limits.min_perf_pct = clamp_t(int, limits.min_perf_pct, 0 , 100);
805 limits.min_perf = div_fp(int_tofp(limits.min_perf_pct), int_tofp(100));
807 limits.max_policy_pct = policy->max * 100 / policy->cpuinfo.max_freq;
808 limits.max_policy_pct = clamp_t(int, limits.max_policy_pct, 0 , 100);
809 limits.max_perf_pct = min(limits.max_policy_pct, limits.max_sysfs_pct);
810 limits.max_perf = div_fp(int_tofp(limits.max_perf_pct), int_tofp(100));
815 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
817 cpufreq_verify_within_cpu_limits(policy);
819 if ((policy->policy != CPUFREQ_POLICY_POWERSAVE) &&
820 (policy->policy != CPUFREQ_POLICY_PERFORMANCE))
826 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
828 int cpu = policy->cpu;
830 del_timer(&all_cpu_data[cpu]->timer);
831 kfree(all_cpu_data[cpu]);
832 all_cpu_data[cpu] = NULL;
836 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
842 rc = intel_pstate_init_cpu(policy->cpu);
846 cpu = all_cpu_data[policy->cpu];
848 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
849 if (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
850 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate) {
851 limits.turbo_disabled = 1;
854 if (limits.min_perf_pct == 100 && limits.max_perf_pct == 100)
855 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
857 policy->policy = CPUFREQ_POLICY_POWERSAVE;
859 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
860 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
862 /* cpuinfo and default policy values */
863 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
864 policy->cpuinfo.max_freq =
865 cpu->pstate.turbo_pstate * cpu->pstate.scaling;
866 policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
867 cpumask_set_cpu(policy->cpu, policy->cpus);
872 static struct cpufreq_driver intel_pstate_driver = {
873 .flags = CPUFREQ_CONST_LOOPS,
874 .verify = intel_pstate_verify_policy,
875 .setpolicy = intel_pstate_set_policy,
876 .get = intel_pstate_get,
877 .init = intel_pstate_cpu_init,
878 .exit = intel_pstate_cpu_exit,
879 .name = "intel_pstate",
882 static int __initdata no_load;
884 static int intel_pstate_msrs_not_valid(void)
886 /* Check that all the msr's we are using are valid. */
887 u64 aperf, mperf, tmp;
889 rdmsrl(MSR_IA32_APERF, aperf);
890 rdmsrl(MSR_IA32_MPERF, mperf);
892 if (!pstate_funcs.get_max() ||
893 !pstate_funcs.get_min() ||
894 !pstate_funcs.get_turbo())
897 rdmsrl(MSR_IA32_APERF, tmp);
901 rdmsrl(MSR_IA32_MPERF, tmp);
908 static void copy_pid_params(struct pstate_adjust_policy *policy)
910 pid_params.sample_rate_ms = policy->sample_rate_ms;
911 pid_params.p_gain_pct = policy->p_gain_pct;
912 pid_params.i_gain_pct = policy->i_gain_pct;
913 pid_params.d_gain_pct = policy->d_gain_pct;
914 pid_params.deadband = policy->deadband;
915 pid_params.setpoint = policy->setpoint;
918 static void copy_cpu_funcs(struct pstate_funcs *funcs)
920 pstate_funcs.get_max = funcs->get_max;
921 pstate_funcs.get_min = funcs->get_min;
922 pstate_funcs.get_turbo = funcs->get_turbo;
923 pstate_funcs.get_scaling = funcs->get_scaling;
924 pstate_funcs.set = funcs->set;
925 pstate_funcs.get_vid = funcs->get_vid;
928 #if IS_ENABLED(CONFIG_ACPI)
929 #include <acpi/processor.h>
931 static bool intel_pstate_no_acpi_pss(void)
935 for_each_possible_cpu(i) {
937 union acpi_object *pss;
938 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
939 struct acpi_processor *pr = per_cpu(processors, i);
944 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
945 if (ACPI_FAILURE(status))
948 pss = buffer.pointer;
949 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
960 struct hw_vendor_info {
962 char oem_id[ACPI_OEM_ID_SIZE];
963 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
966 /* Hardware vendor-specific info that has its own power management modes */
967 static struct hw_vendor_info vendor_info[] = {
968 {1, "HP ", "ProLiant"},
972 static bool intel_pstate_platform_pwr_mgmt_exists(void)
974 struct acpi_table_header hdr;
975 struct hw_vendor_info *v_info;
978 || ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
981 for (v_info = vendor_info; v_info->valid; v_info++) {
982 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE)
983 && !strncmp(hdr.oem_table_id, v_info->oem_table_id, ACPI_OEM_TABLE_ID_SIZE)
984 && intel_pstate_no_acpi_pss())
990 #else /* CONFIG_ACPI not enabled */
991 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
992 #endif /* CONFIG_ACPI */
994 static int __init intel_pstate_init(void)
997 const struct x86_cpu_id *id;
998 struct cpu_defaults *cpu_info;
1003 id = x86_match_cpu(intel_pstate_cpu_ids);
1008 * The Intel pstate driver will be ignored if the platform
1009 * firmware has its own power management modes.
1011 if (intel_pstate_platform_pwr_mgmt_exists())
1014 cpu_info = (struct cpu_defaults *)id->driver_data;
1016 copy_pid_params(&cpu_info->pid_policy);
1017 copy_cpu_funcs(&cpu_info->funcs);
1019 if (intel_pstate_msrs_not_valid())
1022 pr_info("Intel P-state driver initializing.\n");
1024 all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
1028 rc = cpufreq_register_driver(&intel_pstate_driver);
1032 intel_pstate_debug_expose_params();
1033 intel_pstate_sysfs_expose_params();
1038 for_each_online_cpu(cpu) {
1039 if (all_cpu_data[cpu]) {
1040 del_timer_sync(&all_cpu_data[cpu]->timer);
1041 kfree(all_cpu_data[cpu]);
1046 vfree(all_cpu_data);
1049 device_initcall(intel_pstate_init);
1051 static int __init intel_pstate_setup(char *str)
1056 if (!strcmp(str, "disable"))
1060 early_param("intel_pstate", intel_pstate_setup);
1062 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
1063 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
1064 MODULE_LICENSE("GPL");