1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
6 - compatible : Should be "st,stm32mp1-ddr"
7 - reg : controleur (DDRCTRL) and phy (DDRPHYC) base address
8 - clocks : controller clocks handle
9 - clock-names : associated controller clock names
10 the "ddrphyc" clock is used to check the DDR frequency
11 at phy level according the expected value in "mem-speed" field
13 the next attributes are DDR parameters, they are generated by DDR tools
14 included in STM32 Cube tool
18 - st,mem-name : name for DDR configuration, simple string for information
19 - st,mem-speed : DDR expected speed for the setting in kHz
20 - st,mem-size : DDR mem size in byte
23 controlleur attributes:
24 -----------------------
25 - st,ctl-reg : controleur values depending of the DDR type
27 for STM32MP15x: 25 values are requested in this order
54 - st,ctl-timing : controleur values depending of frequency and timing parameter
56 for STM32MP15x: 12 values are requested in this order
70 - st,ctl-map : controleur values depending of address mapping
71 for STM32MP15x: 9 values are requested in this order
82 - st,ctl-perf : controleur values depending of performance and scheduling
83 for STM32MP15x: 17 values are requested in this order
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
105 for STM32MP15x: 11 values are requested in this order
118 - st,phy-timing : phy values depending of frequency and timing parameter of DDR
119 for STM32MP15x: 10 values are requested in this order
141 compatible = "st,stm32mp1-ddr";
143 reg = <0x5A003000 0x550
146 clocks = <&rcc_clk AXIDCG>,
151 <&rcc_clk DDRPHYCAPB>;
153 clock-names = "axidcg",
160 st,mem-name = "DDR3 2x4Gb 533MHz";
161 st,mem-speed = <533000>;
162 st,mem-size = <0x40000000>;
166 0x00000010 /*MRCTRL0*/
167 0x00000000 /*MRCTRL1*/
168 0x00000000 /*DERATEEN*/
169 0x00800000 /*DERATEINT*/
170 0x00000000 /*PWRCTL*/
171 0x00400010 /*PWRTMG*/
172 0x00000000 /*HWLPCTL*/
173 0x00210000 /*RFSHCTL0*/
174 0x00000000 /*RFSHCTL3*/
175 0x00000000 /*CRCPARCTL0*/
176 0xC2000040 /*ZQCTL0*/
177 0x02050105 /*DFITMG0*/
178 0x00000202 /*DFITMG1*/
179 0x07000000 /*DFILPCFG0*/
180 0xC0400003 /*DFIUPD0*/
181 0x00000000 /*DFIUPD1*/
182 0x00000000 /*DFIUPD2*/
183 0x00000000 /*DFIPHYMSTR*/
184 0x00000001 /*ODTMAP*/
187 0x00000000 /*DBGCMD*/
188 0x00000000 /*POISONCFG*/
193 0x0080008A /*RFSHTMG*/
194 0x121B2414 /*DRAMTMG0*/
195 0x000D041B /*DRAMTMG1*/
196 0x0607080E /*DRAMTMG2*/
197 0x0050400C /*DRAMTMG3*/
198 0x07040407 /*DRAMTMG4*/
199 0x06060303 /*DRAMTMG5*/
200 0x02020002 /*DRAMTMG6*/
201 0x00000202 /*DRAMTMG7*/
202 0x00001005 /*DRAMTMG8*/
203 0x000D041B /*DRAMTMG1*/4
204 0x06000600 /*ODTCFG*/
208 0x00080808 /*ADDRMAP1*/
209 0x00000000 /*ADDRMAP2*/
210 0x00000000 /*ADDRMAP3*/
211 0x00001F1F /*ADDRMAP4*/
212 0x07070707 /*ADDRMAP5*/
213 0x0F070707 /*ADDRMAP6*/
214 0x00000000 /*ADDRMAP9*/
215 0x00000000 /*ADDRMAP10*/
216 0x00000000 /*ADDRMAP11*/
221 0x00001201 /*SCHED*/1
222 0x01000001 /*PERFHPR1*/
223 0x08000200 /*PERFLPR1*/
224 0x08000400 /*PERFWR1*/
225 0x00010000 /*PCFGR_0*/
226 0x00000000 /*PCFGW_0*/
227 0x02100B03 /*PCFGQOS0_0*/
228 0x00800100 /*PCFGQOS1_0*/
229 0x01100B03 /*PCFGWQOS0_0*/
230 0x01000200 /*PCFGWQOS1_0*/
231 0x00010000 /*PCFGR_1*/
232 0x00000000 /*PCFGW_1*/
233 0x02100B03 /*PCFGQOS0_1*/
234 0x00800000 /*PCFGQOS1_1*/
235 0x01100B03 /*PCFGWQOS0_1*/
236 0x01000200 /*PCFGWQOS1_1*/
241 0x10400812 /*ACIOCR*/
246 0x0000007B /*ZQ0CR1*/
247 0x0000CE81 /*DX0GCR*/
248 0x0000CE81 /*DX1GCR*/
249 0x0000CE81 /*DX2GCR*/
250 0x0000CE81 /*DX3GCR*/