1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Gateworks Corporation
5 * Author: Tim Harvey <tharvey@gateworks.com>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/mxc_i2c.h>
16 #include <fsl_esdhc_imx.h>
18 #include <linux/delay.h>
19 #include <power/pmic.h>
20 #include <power/ltc3676_pmic.h>
21 #include <power/pfuze100_pmic.h>
25 /* UART2: Serial Console */
26 static iomux_v3_cfg_t const uart2_pads[] = {
27 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
28 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
31 void setup_iomux_uart(void)
33 SETUP_IOMUX_PADS(uart2_pads);
37 static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
38 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
39 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
40 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
41 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
42 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
43 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
44 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
45 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
46 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
47 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
48 IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
50 /* 4-bit microSD on SD2 */
51 static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
52 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
53 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
54 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
55 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
56 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
57 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 /* 8-bit eMMC on SD2/NAND */
62 static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
63 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
64 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
65 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
66 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
67 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
68 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
69 IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
70 IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
71 IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
72 IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75 static iomux_v3_cfg_t const usdhc3_pads[] = {
76 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
79 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
80 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
81 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
82 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
88 * I2C2: PMIC,PCIe Switch,Clock,Mezz
89 * I2C3: Multimedia/Expansion
91 static struct i2c_pads_info mx6q_i2c_pad_info[] = {
94 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
95 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
96 .gp = IMX_GPIO_NR(3, 21)
99 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
100 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
101 .gp = IMX_GPIO_NR(3, 28)
105 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
106 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
107 .gp = IMX_GPIO_NR(4, 12)
110 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
111 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
112 .gp = IMX_GPIO_NR(4, 13)
116 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
117 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
118 .gp = IMX_GPIO_NR(1, 3)
121 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
122 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
123 .gp = IMX_GPIO_NR(1, 6)
128 static struct i2c_pads_info mx6dl_i2c_pad_info[] = {
131 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
132 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
133 .gp = IMX_GPIO_NR(3, 21)
136 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
137 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
138 .gp = IMX_GPIO_NR(3, 28)
142 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
143 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
144 .gp = IMX_GPIO_NR(4, 12)
147 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
148 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
149 .gp = IMX_GPIO_NR(4, 13)
153 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
154 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
155 .gp = IMX_GPIO_NR(1, 3)
158 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
159 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
160 .gp = IMX_GPIO_NR(1, 6)
165 void setup_ventana_i2c(int i2c)
167 struct i2c_pads_info *p;
169 if (is_cpu_type(MXC_CPU_MX6Q))
170 p = &mx6q_i2c_pad_info[i2c];
172 p = &mx6dl_i2c_pad_info[i2c];
174 setup_i2c(i2c, CONFIG_SYS_I2C_SPEED, 0x7f, p);
178 * Baseboard specific GPIO
180 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
182 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
184 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
186 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
188 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
191 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
193 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
195 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
197 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
199 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
201 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
203 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
205 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
207 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
209 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
211 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
214 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
216 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
218 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
220 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
222 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
224 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
226 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
228 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
230 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
232 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
234 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
237 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
239 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
241 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
243 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
245 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
247 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
249 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
251 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
253 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
255 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
257 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
259 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
262 static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
264 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
266 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
269 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
271 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
273 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
275 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
276 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
277 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
278 IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
279 IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
280 IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
282 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
284 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
286 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
289 static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
291 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
293 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
296 static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
298 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
300 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
302 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
304 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
306 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
308 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
310 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
312 IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
315 static iomux_v3_cfg_t const gw5901_gpio_pads[] = {
317 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
319 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
321 IOMUX_PADS(PAD_DISP0_DAT8__WDOG1_B | DIO_PAD_CFG),
323 IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
324 IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15 | DIO_PAD_CFG),
325 IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16 | DIO_PAD_CFG),
326 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
328 IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
330 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
332 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
335 static iomux_v3_cfg_t const gw5902_gpio_pads[] = {
337 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
339 IOMUX_PADS(PAD_SD3_CLK__GPIO7_IO03 | DIO_PAD_CFG),
341 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
343 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
345 IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
347 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
350 static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
352 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
354 IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
356 IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
358 IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
359 /* USBH1_PEN (EHCI) */
360 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
362 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
364 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
366 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
368 IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
370 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
372 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
374 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
376 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
379 static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
381 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
383 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
385 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
387 IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
389 IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
391 IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
393 IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
395 IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
397 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
399 IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
401 IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
403 IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
405 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
408 static iomux_v3_cfg_t const gw5905_gpio_pads[] = {
410 IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
412 IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
414 IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
416 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
418 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
420 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | DIO_PAD_CFG),
422 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
424 IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
425 /* USBH1_PEN (EHCI) */
426 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
428 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
430 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
431 /* GYRO_CONTROL/DATA_EN */
432 IOMUX_PADS(PAD_CSI0_DAT8__GPIO5_IO26 | DIO_PAD_CFG),
434 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
436 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
440 struct dio_cfg gw51xx_dio[] = {
442 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
448 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
450 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
454 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
456 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
460 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
462 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
467 struct dio_cfg gw52xx_dio[] = {
469 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
475 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
477 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
481 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
483 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
487 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
494 struct dio_cfg gw53xx_dio[] = {
496 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
502 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
504 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
508 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
510 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
514 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
521 struct dio_cfg gw54xx_dio[] = {
523 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
525 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
529 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
531 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
535 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
537 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
541 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
543 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
548 struct dio_cfg gw551x_dio[] = {
550 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
552 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
556 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
558 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
563 struct dio_cfg gw552x_dio[] = {
565 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
571 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
573 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
577 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
579 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
583 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
589 {IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) },
595 {IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) },
601 {IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) },
607 {IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) },
613 {IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) },
619 {IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) },
626 struct dio_cfg gw553x_dio[] = {
628 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
634 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
636 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
640 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
642 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
646 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
648 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
653 struct dio_cfg gw560x_dio[] = {
655 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
661 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
663 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
667 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
669 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
673 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
680 struct dio_cfg gw5901_dio[] = {
682 { IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
688 { IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
694 { IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
700 { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
707 struct dio_cfg gw5902_dio[] = {
709 { IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
715 { IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
721 { IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
727 { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
734 struct dio_cfg gw5903_dio[] = {
737 struct dio_cfg gw5904_dio[] = {
739 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
745 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
747 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
751 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
753 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
757 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
763 {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
769 {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
775 {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
781 {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
787 {IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) },
793 {IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) },
799 {IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) },
805 {IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) },
812 struct dio_cfg gw5906_dio[] = {
814 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
820 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
822 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
826 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
828 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
832 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
840 * Board Specific GPIO
842 struct ventana gpio_cfg[GW_UNKNOWN] = {
845 .gpio_pads = gw54xx_gpio_pads,
846 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
847 .dio_cfg = gw54xx_dio,
848 .dio_num = ARRAY_SIZE(gw54xx_dio),
849 .mezz_pwren = IMX_GPIO_NR(4, 7),
850 .mezz_irq = IMX_GPIO_NR(4, 9),
851 .rs485en = IMX_GPIO_NR(3, 24),
852 .dioi2c_en = IMX_GPIO_NR(4, 5),
853 .pcie_sson = IMX_GPIO_NR(1, 20),
854 .mmc_cd = IMX_GPIO_NR(7, 0),
859 .gpio_pads = gw51xx_gpio_pads,
860 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
861 .dio_cfg = gw51xx_dio,
862 .dio_num = ARRAY_SIZE(gw51xx_dio),
863 .mezz_pwren = IMX_GPIO_NR(2, 19),
864 .mezz_irq = IMX_GPIO_NR(2, 18),
865 .gps_shdn = IMX_GPIO_NR(1, 2),
866 .wdis = IMX_GPIO_NR(7, 12),
871 .gpio_pads = gw52xx_gpio_pads,
872 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
873 .dio_cfg = gw52xx_dio,
874 .dio_num = ARRAY_SIZE(gw52xx_dio),
875 .mezz_pwren = IMX_GPIO_NR(2, 19),
876 .mezz_irq = IMX_GPIO_NR(2, 18),
877 .gps_shdn = IMX_GPIO_NR(1, 27),
878 .usb_sel = IMX_GPIO_NR(1, 2),
879 .wdis = IMX_GPIO_NR(7, 12),
880 .msata_en = GP_MSATA_SEL,
881 .rs232_en = GP_RS232_EN,
882 .vsel_pin = IMX_GPIO_NR(6, 14),
883 .mmc_cd = IMX_GPIO_NR(7, 0),
888 .gpio_pads = gw53xx_gpio_pads,
889 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
890 .dio_cfg = gw53xx_dio,
891 .dio_num = ARRAY_SIZE(gw53xx_dio),
892 .mezz_pwren = IMX_GPIO_NR(2, 19),
893 .mezz_irq = IMX_GPIO_NR(2, 18),
894 .gps_shdn = IMX_GPIO_NR(1, 27),
895 .wdis = IMX_GPIO_NR(7, 12),
896 .msata_en = GP_MSATA_SEL,
897 .rs232_en = GP_RS232_EN,
898 .vsel_pin = IMX_GPIO_NR(6, 14),
899 .mmc_cd = IMX_GPIO_NR(7, 0),
904 .gpio_pads = gw54xx_gpio_pads,
905 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
906 .dio_cfg = gw54xx_dio,
907 .dio_num = ARRAY_SIZE(gw54xx_dio),
908 .mezz_pwren = IMX_GPIO_NR(2, 19),
909 .mezz_irq = IMX_GPIO_NR(2, 18),
910 .rs485en = IMX_GPIO_NR(7, 1),
911 .dioi2c_en = IMX_GPIO_NR(4, 5),
912 .pcie_sson = IMX_GPIO_NR(1, 20),
913 .wdis = IMX_GPIO_NR(5, 17),
914 .msata_en = GP_MSATA_SEL,
915 .rs232_en = GP_RS232_EN,
916 .vsel_pin = IMX_GPIO_NR(6, 14),
917 .mmc_cd = IMX_GPIO_NR(7, 0),
922 .gpio_pads = gw551x_gpio_pads,
923 .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
924 .dio_cfg = gw551x_dio,
925 .dio_num = ARRAY_SIZE(gw551x_dio),
926 .wdis = IMX_GPIO_NR(7, 12),
931 .gpio_pads = gw552x_gpio_pads,
932 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
933 .dio_cfg = gw552x_dio,
934 .dio_num = ARRAY_SIZE(gw552x_dio),
935 .usb_sel = IMX_GPIO_NR(1, 7),
936 .wdis = IMX_GPIO_NR(7, 12),
937 .msata_en = GP_MSATA_SEL,
942 .gpio_pads = gw553x_gpio_pads,
943 .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
944 .dio_cfg = gw553x_dio,
945 .dio_num = ARRAY_SIZE(gw553x_dio),
946 .wdis = IMX_GPIO_NR(7, 12),
947 .vsel_pin = IMX_GPIO_NR(6, 14),
948 .mmc_cd = IMX_GPIO_NR(7, 0),
953 .gpio_pads = gw560x_gpio_pads,
954 .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
955 .dio_cfg = gw560x_dio,
956 .dio_num = ARRAY_SIZE(gw560x_dio),
957 .mezz_pwren = IMX_GPIO_NR(2, 19),
958 .mezz_irq = IMX_GPIO_NR(2, 18),
959 .rs232_en = GP_RS232_EN,
960 .wdis = IMX_GPIO_NR(7, 12),
961 .mmc_cd = IMX_GPIO_NR(7, 0),
966 .gpio_pads = gw5901_gpio_pads,
967 .num_pads = ARRAY_SIZE(gw5901_gpio_pads)/2,
968 .dio_cfg = gw5901_dio,
973 .gpio_pads = gw5902_gpio_pads,
974 .num_pads = ARRAY_SIZE(gw5902_gpio_pads)/2,
975 .dio_cfg = gw5902_dio,
976 .rs232_en = GP_RS232_EN,
981 .gpio_pads = gw5903_gpio_pads,
982 .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
983 .dio_cfg = gw5903_dio,
984 .dio_num = ARRAY_SIZE(gw5903_dio),
985 .mmc_cd = IMX_GPIO_NR(6, 11),
990 .gpio_pads = gw5904_gpio_pads,
991 .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
992 .dio_cfg = gw5904_dio,
993 .dio_num = ARRAY_SIZE(gw5904_dio),
994 .mezz_pwren = IMX_GPIO_NR(2, 19),
995 .mezz_irq = IMX_GPIO_NR(2, 18),
1000 .gpio_pads = gw5905_gpio_pads,
1001 .num_pads = ARRAY_SIZE(gw5905_gpio_pads)/2,
1002 .wdis = IMX_GPIO_NR(7, 13),
1007 .gpio_pads = gw552x_gpio_pads,
1008 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
1009 .dio_cfg = gw5906_dio,
1010 .dio_num = ARRAY_SIZE(gw5906_dio),
1011 .usb_sel = IMX_GPIO_NR(1, 7),
1012 .wdis = IMX_GPIO_NR(7, 12),
1013 .msata_en = GP_MSATA_SEL,
1018 .gpio_pads = gw51xx_gpio_pads,
1019 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
1020 .dio_cfg = gw51xx_dio,
1021 .dio_num = ARRAY_SIZE(gw51xx_dio),
1022 .wdis = IMX_GPIO_NR(7, 12),
1027 .gpio_pads = gw53xx_gpio_pads,
1028 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
1029 .dio_cfg = gw53xx_dio,
1030 .dio_num = ARRAY_SIZE(gw53xx_dio),
1031 .mezz_pwren = IMX_GPIO_NR(2, 19),
1032 .mezz_irq = IMX_GPIO_NR(2, 18),
1033 .gps_shdn = IMX_GPIO_NR(1, 27),
1034 .wdis = IMX_GPIO_NR(7, 12),
1035 .msata_en = GP_MSATA_SEL,
1036 .rs232_en = GP_RS232_EN,
1041 .gpio_pads = gw5904_gpio_pads,
1042 .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
1043 .dio_cfg = gw5904_dio,
1044 .dio_num = ARRAY_SIZE(gw5904_dio),
1045 .mezz_pwren = IMX_GPIO_NR(2, 19),
1046 .mezz_irq = IMX_GPIO_NR(2, 18),
1050 #define SETUP_GPIO_OUTPUT(gpio, name, level) \
1051 gpio_request(gpio, name); \
1052 gpio_direction_output(gpio, level);
1053 #define SETUP_GPIO_INPUT(gpio, name) \
1054 gpio_request(gpio, name); \
1055 gpio_direction_input(gpio);
1056 void setup_iomux_gpio(int board, struct ventana_board_info *info)
1058 if (board >= GW_UNKNOWN)
1061 /* board specific iomux */
1062 imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads,
1063 gpio_cfg[board].num_pads);
1066 if (gpio_cfg[board].rs232_en) {
1067 gpio_request(gpio_cfg[board].rs232_en, "rs232_en#");
1068 gpio_direction_output(gpio_cfg[board].rs232_en, 0);
1071 /* MSATA Enable - default to PCI */
1072 if (gpio_cfg[board].msata_en) {
1073 gpio_request(gpio_cfg[board].msata_en, "msata_en");
1074 gpio_direction_output(gpio_cfg[board].msata_en, 0);
1077 /* Expansion Mezzanine IO */
1078 if (gpio_cfg[board].mezz_pwren) {
1079 gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
1080 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1082 if (gpio_cfg[board].mezz_irq) {
1083 gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#");
1084 gpio_direction_input(gpio_cfg[board].mezz_irq);
1087 /* RS485 Transmit Enable */
1088 if (gpio_cfg[board].rs485en) {
1089 gpio_request(gpio_cfg[board].rs485en, "rs485_en");
1090 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1094 if (gpio_cfg[board].gps_shdn) {
1095 gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn");
1096 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1100 if (gpio_cfg[board].dioi2c_en) {
1101 gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#");
1102 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1105 /* PCICK_SSON: disable spread-spectrum clock */
1106 if (gpio_cfg[board].pcie_sson) {
1107 gpio_request(gpio_cfg[board].pcie_sson, "pci_sson");
1108 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1111 /* USBOTG mux routing */
1112 if (gpio_cfg[board].usb_sel) {
1113 gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel");
1114 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1117 /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1118 if (gpio_cfg[board].wdis) {
1119 gpio_request(gpio_cfg[board].wdis, "wlan_dis");
1120 gpio_direction_output(gpio_cfg[board].wdis, 1);
1123 /* sense vselect pin to see if we support uhs-i */
1124 if (gpio_cfg[board].vsel_pin) {
1125 gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect");
1126 gpio_direction_input(gpio_cfg[board].vsel_pin);
1127 gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
1131 if (gpio_cfg[board].mmc_cd) {
1132 gpio_request(gpio_cfg[board].mmc_cd, "sd_cd");
1133 gpio_direction_input(gpio_cfg[board].mmc_cd);
1136 /* Anything else board specific */
1139 gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
1140 gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
1143 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can_stby", 0);
1146 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 2), "can1_stby", 0);
1147 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 3), "can2_stby", 0);
1148 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "5P0V_EN", 1);
1151 gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
1152 gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
1153 gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
1154 gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
1155 gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
1156 gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
1157 gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
1158 gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
1159 gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
1160 gpio_direction_input(IMX_GPIO_NR(4, 6));
1161 gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
1162 gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
1163 gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
1164 gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
1168 gpio_request(IMX_GPIO_NR(4, 23), "rs485_en");
1169 gpio_direction_output(IMX_GPIO_NR(4, 23), 0);
1170 gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
1171 gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
1172 gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
1173 gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
1174 gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
1175 gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
1176 gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
1177 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
1178 gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
1179 gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
1180 gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
1181 gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
1184 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "usb_pcisel", 0);
1185 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 9), "lvds_cabc", 1);
1186 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 14), "mipi_pdwn", 1);
1187 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 15), "mipi_rst#", 0);
1188 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(2, 3), "emmy_pdwn#", 1);
1189 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 5), "spk_shdn#", 0);
1190 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 0);
1191 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 6), "touch_irq", 0);
1192 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 5), "flash_en1", 0);
1193 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 6), "flash_en2", 0);
1194 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 14), "dect_rst#", 1);
1195 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 17), "codec_rst#", 0);
1196 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 26), "imu_den", 1);
1197 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "lvds_cabc", 0);
1200 * gauruntee touch controller comes out of reset with INT
1203 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 1);
1208 /* setup GPIO pinmux and default configuration per baseboard and env */
1209 void setup_board_gpio(int board, struct ventana_board_info *info)
1215 int quiet = simple_strtol(env_get("quiet"), NULL, 10);
1217 if (board >= GW_UNKNOWN)
1221 if (gpio_cfg[board].rs232_en) {
1222 gpio_direction_output(gpio_cfg[board].rs232_en,
1223 (hwconfig("rs232")) ? 0 : 1);
1227 if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
1228 gpio_direction_output(GP_MSATA_SEL,
1229 (hwconfig("msata")) ? 1 : 0);
1232 /* USBOTG Select (PCISKT or FrontPanel) */
1233 if (gpio_cfg[board].usb_sel) {
1234 gpio_direction_output(gpio_cfg[board].usb_sel,
1235 (hwconfig("usb_pcisel")) ? 1 : 0);
1239 * Configure DIO pinmux/padctl registers
1240 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1242 for (i = 0; i < gpio_cfg[board].dio_num; i++) {
1243 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1244 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1245 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1247 if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
1249 sprintf(arg, "dio%d", i);
1252 s = hwconfig_subarg(arg, "padctrl", &len);
1254 ctrl = MUX_PAD_CTRL(hextoul(s, NULL)
1255 & 0x1ffff) | MUX_MODE_SION;
1257 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1259 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
1260 (cfg->gpio_param/32)+1,
1264 imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1266 gpio_requestf(cfg->gpio_param, "dio%d", i);
1267 gpio_direction_input(cfg->gpio_param);
1268 } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
1270 if (!cfg->pwm_param) {
1271 printf("DIO%d: Error: pwm config invalid\n",
1276 printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
1277 imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1278 MUX_PAD_CTRL(ctrl));
1283 if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
1284 printf("MSATA: %s\n", (hwconfig("msata") ?
1285 "enabled" : "disabled"));
1287 if (gpio_cfg[board].rs232_en) {
1288 printf("RS232: %s\n", (hwconfig("rs232")) ?
1289 "enabled" : "disabled");
1294 /* setup board specific PMIC */
1295 void setup_pmic(void)
1298 struct ventana_board_info ventana_info;
1299 int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1300 const int i2c_pmic = 1;
1305 /* determine board revision */
1307 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1308 if (ventana_info.model[i] >= 'A') {
1309 rev = ventana_info.model[i];
1314 i2c_set_bus_num(i2c_pmic);
1316 /* configure PFUZE100 PMIC */
1317 if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) {
1318 debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR);
1319 power_pfuze100_init(i2c_pmic);
1320 p = pmic_get("PFUZE100");
1321 if (p && !pmic_probe(p)) {
1322 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
1323 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
1325 /* Set VGEN1 to 1.5V and enable */
1326 pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
1327 reg &= ~(LDO_VOL_MASK);
1328 reg |= (LDOA_1_50V | LDO_EN);
1329 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1331 /* Set SWBST to 5.0V and enable */
1332 pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
1333 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1334 reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
1335 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1337 if (board == GW54xx && (rev == 'G')) {
1339 pmic_reg_write(p, PFUZE100_VGEN5VOL, 0);
1341 /* Set VGEN6 to 2.5V and enable */
1342 pmic_reg_read(p, PFUZE100_VGEN6VOL, ®);
1343 reg &= ~(LDO_VOL_MASK);
1344 reg |= (LDOB_2_50V | LDO_EN);
1345 pmic_reg_write(p, PFUZE100_VGEN6VOL, reg);
1349 /* put all switchers in continuous mode */
1350 pmic_reg_read(p, PFUZE100_SW1ABMODE, ®);
1351 reg &= ~(SW_MODE_MASK);
1353 pmic_reg_write(p, PFUZE100_SW1ABMODE, reg);
1355 pmic_reg_read(p, PFUZE100_SW2MODE, ®);
1356 reg &= ~(SW_MODE_MASK);
1358 pmic_reg_write(p, PFUZE100_SW2MODE, reg);
1360 pmic_reg_read(p, PFUZE100_SW3AMODE, ®);
1361 reg &= ~(SW_MODE_MASK);
1363 pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
1365 pmic_reg_read(p, PFUZE100_SW3BMODE, ®);
1366 reg &= ~(SW_MODE_MASK);
1368 pmic_reg_write(p, PFUZE100_SW3BMODE, reg);
1370 pmic_reg_read(p, PFUZE100_SW4MODE, ®);
1371 reg &= ~(SW_MODE_MASK);
1373 pmic_reg_write(p, PFUZE100_SW4MODE, reg);
1376 /* configure LTC3676 PMIC */
1377 else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) {
1378 debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
1379 power_ltc3676_init(i2c_pmic);
1380 p = pmic_get("LTC3676_PMIC");
1381 if (!p || pmic_probe(p))
1383 puts("PMIC: LTC3676\n");
1385 * set board-specific scalar for max CPU frequency
1386 * per CPU based on the LDO enabled Operating Ranges
1387 * defined in the respective IMX6DQ and IMX6SDL
1388 * datasheets. The voltage resulting from the R1/R2
1389 * feedback inputs on Ventana is 1308mV. Note that this
1390 * is a bit shy of the Vmin of 1350mV in the datasheet
1391 * for LDO enabled mode but is as high as we can go.
1395 /* mask PGOOD during SW3 transition */
1396 pmic_reg_write(p, LTC3676_DVB3B,
1397 0x1f | LTC3676_PGOOD_MASK);
1398 /* set SW3 (VDD_ARM) */
1399 pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1402 /* mask PGOOD during SW3 transition */
1403 pmic_reg_write(p, LTC3676_DVB3B,
1404 0x1f | LTC3676_PGOOD_MASK);
1405 /* set SW3 (VDD_ARM) */
1406 pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1408 /* mask PGOOD during SW4 transition */
1409 pmic_reg_write(p, LTC3676_DVB4B,
1410 0x1f | LTC3676_PGOOD_MASK);
1411 /* set SW4 (VDD_SOC) */
1412 pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
1415 /* mask PGOOD during SW1 transition */
1416 pmic_reg_write(p, LTC3676_DVB1B,
1417 0x1f | LTC3676_PGOOD_MASK);
1418 /* set SW1 (VDD_ARM) */
1419 pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
1421 /* mask PGOOD during SW3 transition */
1422 pmic_reg_write(p, LTC3676_DVB3B,
1423 0x1f | LTC3676_PGOOD_MASK);
1424 /* set SW3 (VDD_SOC) */
1425 pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1428 /* mask PGOOD during SW1 transition */
1429 pmic_reg_write(p, LTC3676_DVB1B,
1430 0x1f | LTC3676_PGOOD_MASK);
1431 /* set SW1 (VDD_SOC) */
1432 pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
1434 /* mask PGOOD during SW3 transition */
1435 pmic_reg_write(p, LTC3676_DVB3B,
1436 0x1f | LTC3676_PGOOD_MASK);
1437 /* set SW3 (VDD_ARM) */
1438 pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1441 /* put all switchers in continuous mode */
1442 pmic_reg_write(p, LTC3676_BUCK1, 0xc0);
1443 pmic_reg_write(p, LTC3676_BUCK2, 0xc0);
1444 pmic_reg_write(p, LTC3676_BUCK3, 0xc0);
1445 pmic_reg_write(p, LTC3676_BUCK4, 0xc0);
1449 #include <fdt_support.h>
1450 #define WDOG1_ADDR 0x20bc000
1451 #define WDOG2_ADDR 0x20c0000
1452 #define GPIO3_ADDR 0x20a4000
1453 #define USDHC3_ADDR 0x2198000
1455 static void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
1457 int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1460 fdt_delprop(blob, off, "ext-reset-output");
1461 fdt_delprop(blob, off, "fsl,ext-reset-output");
1465 void ft_early_fixup(void *blob, int board_type)
1467 struct ventana_board_info *info = &ventana_info;
1471 /* determine board revision */
1472 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1473 if (ventana_info.model[i] >= 'A') {
1474 rev = ventana_info.model[i];
1480 * Board model specific fixups
1482 switch (board_type) {
1485 * disable wdog node for GW51xx-A/B to work around
1486 * errata causing wdog timer to be unreliable.
1488 if (rev >= 'A' && rev < 'C') {
1489 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1492 fdt_status_disabled(blob, i);
1495 /* GW51xx-E adds WDOG1_B external reset */
1497 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1501 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1502 if (info->model[4] == '2') {
1506 i = fdt_node_offset_by_compatible(blob, -1,
1509 range = (u32 *)fdt_getprop(blob, i,
1510 "reset-gpio", NULL);
1513 i = fdt_node_offset_by_compat_reg(blob,
1514 "fsl,imx6q-gpio", GPIO3_ADDR);
1516 handle = fdt_get_phandle(blob, i);
1518 range[0] = cpu_to_fdt32(handle);
1519 range[1] = cpu_to_fdt32(23);
1523 /* these have broken usd_vsel */
1524 if (strstr((const char *)info->model, "SP318-B") ||
1525 strstr((const char *)info->model, "SP331-B"))
1526 gpio_cfg[board_type].usd_vsel = 0;
1528 /* GW522x-B adds WDOG1_B external reset */
1530 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1533 /* GW520x-E adds WDOG1_B external reset */
1534 else if (info->model[4] == '0' && rev < 'E')
1535 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1539 /* GW53xx-E adds WDOG1_B external reset */
1541 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1546 * disable serial2 node for GW54xx for compatibility with older
1547 * 3.10.x kernel that improperly had this node enabled in the DT
1549 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
1552 /* GW54xx-E adds WDOG2_B external reset */
1554 ft_board_wdog_fixup(blob, WDOG2_ADDR);
1558 /* GW551x-C adds WDOG1_B external reset */
1560 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1564 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1566 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1570 /* remove no-1-8-v if UHS-I support is present */
1571 if (gpio_cfg[board_type].usd_vsel) {
1572 debug("Enabling UHS-I support\n");
1573 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1576 fdt_delprop(blob, i, "no-1-8-v");
1580 #ifdef CONFIG_FSL_ESDHC_IMX
1581 static struct fsl_esdhc_cfg usdhc_cfg[2];
1583 int board_mmc_init(struct bd_info *bis)
1585 struct ventana_board_info ventana_info;
1586 int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1589 switch (board_type) {
1594 /* usdhc3: 4bit microSD */
1595 SETUP_IOMUX_PADS(usdhc3_pads);
1596 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
1597 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
1598 usdhc_cfg[0].max_bus_width = 4;
1599 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
1601 /* usdhc2: 8-bit eMMC */
1602 SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
1603 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
1604 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
1605 usdhc_cfg[0].max_bus_width = 8;
1606 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
1609 /* usdhc3: 4-bit microSD */
1610 SETUP_IOMUX_PADS(usdhc3_pads);
1611 usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
1612 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
1613 usdhc_cfg[1].max_bus_width = 4;
1614 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
1616 /* usdhc3: 8-bit eMMC */
1617 SETUP_IOMUX_PADS(gw5904_emmc_pads);
1618 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
1619 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
1620 usdhc_cfg[0].max_bus_width = 8;
1621 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
1624 /* usdhc2: 4-bit microSD */
1625 SETUP_IOMUX_PADS(gw5904_mmc_pads);
1626 usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
1627 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
1628 usdhc_cfg[1].max_bus_width = 4;
1629 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
1633 /* usdhc3: 8bit eMMC */
1634 SETUP_IOMUX_PADS(gw5904_emmc_pads);
1635 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
1636 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
1637 usdhc_cfg[0].max_bus_width = 8;
1638 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
1640 /* doesn't have MMC */
1646 int board_mmc_getcd(struct mmc *mmc)
1648 struct ventana_board_info ventana_info;
1649 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
1650 int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1651 int gpio = gpio_cfg[board].mmc_cd;
1656 /* emmc is always present */
1657 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
1664 /* emmc is always present */
1665 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
1671 debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio));
1672 return !gpio_get_value(gpio);
1678 #endif /* CONFIG_FSL_ESDHC_IMX */