1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Gateworks Corporation
5 * Author: Tim Harvey <tharvey@gateworks.com>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/mx6-pins.h>
12 #include <asm/arch/sys_proto.h>
14 #include <asm/mach-imx/mxc_i2c.h>
16 #include <fsl_esdhc_imx.h>
18 #include <linux/delay.h>
19 #include <power/pmic.h>
20 #include <power/ltc3676_pmic.h>
21 #include <power/pfuze100_pmic.h>
25 /* UART2: Serial Console */
26 static iomux_v3_cfg_t const uart2_pads[] = {
27 IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
28 IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
31 void setup_iomux_uart(void)
33 SETUP_IOMUX_PADS(uart2_pads);
37 static iomux_v3_cfg_t const gw5904_emmc_pads[] = {
38 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
39 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
40 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
41 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
42 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
43 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
44 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
45 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
46 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
47 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
48 IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
50 /* 4-bit microSD on SD2 */
51 static iomux_v3_cfg_t const gw5904_mmc_pads[] = {
52 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
53 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
54 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
55 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
56 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
57 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
59 IOMUX_PADS(PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
61 /* 8-bit eMMC on SD2/NAND */
62 static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = {
63 IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
64 IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
65 IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
66 IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
67 IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
68 IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
69 IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
70 IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
71 IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
72 IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
75 static iomux_v3_cfg_t const usdhc3_pads[] = {
76 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
77 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
78 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
79 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
80 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
81 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
82 IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
88 * I2C2: PMIC,PCIe Switch,Clock,Mezz
89 * I2C3: Multimedia/Expansion
91 static struct i2c_pads_info mx6q_i2c_pad_info[] = {
94 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
95 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
96 .gp = IMX_GPIO_NR(3, 21)
99 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
100 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
101 .gp = IMX_GPIO_NR(3, 28)
105 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
106 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
107 .gp = IMX_GPIO_NR(4, 12)
110 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
111 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
112 .gp = IMX_GPIO_NR(4, 13)
116 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
117 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
118 .gp = IMX_GPIO_NR(1, 3)
121 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
122 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
123 .gp = IMX_GPIO_NR(1, 6)
128 static struct i2c_pads_info mx6dl_i2c_pad_info[] = {
131 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
132 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
133 .gp = IMX_GPIO_NR(3, 21)
136 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
137 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
138 .gp = IMX_GPIO_NR(3, 28)
142 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
143 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
144 .gp = IMX_GPIO_NR(4, 12)
147 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
148 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
149 .gp = IMX_GPIO_NR(4, 13)
153 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
154 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
155 .gp = IMX_GPIO_NR(1, 3)
158 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
159 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
160 .gp = IMX_GPIO_NR(1, 6)
165 void setup_ventana_i2c(int i2c)
167 struct i2c_pads_info *p;
169 if (is_cpu_type(MXC_CPU_MX6Q))
170 p = &mx6q_i2c_pad_info[i2c];
172 p = &mx6dl_i2c_pad_info[i2c];
174 setup_i2c(i2c, CONFIG_SYS_I2C_SPEED, 0x7f, p);
178 * Baseboard specific GPIO
180 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
182 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
184 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
186 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
188 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
191 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
193 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
195 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
197 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
199 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
201 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
203 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
205 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
207 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
209 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
212 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
214 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
216 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
218 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
220 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
222 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
224 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
226 IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG),
228 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
230 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
233 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
235 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
237 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
239 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
241 IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG),
243 IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG),
245 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
247 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
249 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
251 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
253 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
256 static iomux_v3_cfg_t const gw551x_gpio_pads[] = {
258 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
261 static iomux_v3_cfg_t const gw552x_gpio_pads[] = {
263 IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG),
265 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
267 IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG),
268 IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG),
269 IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG),
270 IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG),
271 IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG),
272 IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG),
274 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
276 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG),
278 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
281 static iomux_v3_cfg_t const gw553x_gpio_pads[] = {
283 IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG),
285 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
288 static iomux_v3_cfg_t const gw560x_gpio_pads[] = {
290 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
292 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
294 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
296 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
298 IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG),
300 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
302 IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG),
305 static iomux_v3_cfg_t const gw5901_gpio_pads[] = {
307 IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG),
309 IOMUX_PADS(PAD_DISP0_DAT8__WDOG1_B | DIO_PAD_CFG),
311 IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
312 IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15 | DIO_PAD_CFG),
313 IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16 | DIO_PAD_CFG),
314 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
316 IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
318 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
320 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
323 static iomux_v3_cfg_t const gw5902_gpio_pads[] = {
325 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
327 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
329 IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | DIO_PAD_CFG),
331 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
334 static iomux_v3_cfg_t const gw5903_gpio_pads[] = {
336 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
338 IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | DIO_PAD_CFG),
340 IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
342 IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04 | DIO_PAD_CFG),
343 /* USBH1_PEN (EHCI) */
344 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
346 IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG),
348 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
350 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
352 IOMUX_PADS(PAD_CSI0_DAT12__GPIO5_IO30 | DIO_PAD_CFG),
354 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
356 IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | DIO_PAD_CFG),
358 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
360 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
363 static iomux_v3_cfg_t const gw5904_gpio_pads[] = {
365 IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG),
367 IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)),
369 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
371 IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG),
373 IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG),
375 IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG),
377 IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG),
379 IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG),
381 IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG),
383 IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
385 IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
387 IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG),
389 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG),
392 static iomux_v3_cfg_t const gw5905_gpio_pads[] = {
394 IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03 | DIO_PAD_CFG),
396 IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG),
398 IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG),
400 IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG),
402 IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG),
404 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | DIO_PAD_CFG),
406 IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG),
408 IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | DIO_PAD_CFG),
409 /* USBH1_PEN (EHCI) */
410 IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG),
412 IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG),
414 IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG),
415 /* GYRO_CONTROL/DATA_EN */
416 IOMUX_PADS(PAD_CSI0_DAT8__GPIO5_IO26 | DIO_PAD_CFG),
418 IOMUX_PADS(PAD_KEY_COL1__GPIO4_IO08 | DIO_PAD_CFG),
420 IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG),
424 struct dio_cfg gw51xx_dio[] = {
426 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
432 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
434 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
438 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
440 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
444 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
446 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
451 struct dio_cfg gw52xx_dio[] = {
453 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
459 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
461 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
465 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
467 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
471 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
478 struct dio_cfg gw53xx_dio[] = {
480 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
486 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
488 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
492 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
494 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
498 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
505 struct dio_cfg gw54xx_dio[] = {
507 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
509 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
513 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
515 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
519 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
521 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
525 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
527 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
532 struct dio_cfg gw551x_dio[] = {
534 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
536 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
540 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
542 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
547 struct dio_cfg gw552x_dio[] = {
549 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
555 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
557 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
561 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
563 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
567 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
573 {IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) },
579 {IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) },
585 {IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) },
591 {IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) },
597 {IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) },
603 {IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) },
610 struct dio_cfg gw553x_dio[] = {
612 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
618 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
620 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
624 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
626 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
630 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
632 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
637 struct dio_cfg gw560x_dio[] = {
639 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
645 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
647 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
651 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
653 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
657 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
664 struct dio_cfg gw5901_dio[] = {
666 { IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
672 { IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
678 { IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
684 { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
691 struct dio_cfg gw5902_dio[] = {
693 { IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14) },
699 { IOMUX_PADS(PAD_DISP0_DAT21__GPIO5_IO15) },
705 { IOMUX_PADS(PAD_DISP0_DAT22__GPIO5_IO16) },
711 { IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17) },
718 struct dio_cfg gw5903_dio[] = {
721 struct dio_cfg gw5904_dio[] = {
723 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
729 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
731 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
735 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
737 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
741 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
747 {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) },
753 {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) },
759 {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) },
765 {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) },
771 {IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) },
777 {IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) },
783 {IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) },
789 {IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) },
796 struct dio_cfg gw5906_dio[] = {
798 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
804 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
806 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
810 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
812 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
816 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
824 * Board Specific GPIO
826 struct ventana gpio_cfg[GW_UNKNOWN] = {
829 .gpio_pads = gw54xx_gpio_pads,
830 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
831 .dio_cfg = gw54xx_dio,
832 .dio_num = ARRAY_SIZE(gw54xx_dio),
833 .mezz_pwren = IMX_GPIO_NR(4, 7),
834 .mezz_irq = IMX_GPIO_NR(4, 9),
835 .rs485en = IMX_GPIO_NR(3, 24),
836 .dioi2c_en = IMX_GPIO_NR(4, 5),
837 .pcie_sson = IMX_GPIO_NR(1, 20),
838 .mmc_cd = IMX_GPIO_NR(7, 0),
843 .gpio_pads = gw51xx_gpio_pads,
844 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
845 .dio_cfg = gw51xx_dio,
846 .dio_num = ARRAY_SIZE(gw51xx_dio),
847 .mezz_pwren = IMX_GPIO_NR(2, 19),
848 .mezz_irq = IMX_GPIO_NR(2, 18),
849 .gps_shdn = IMX_GPIO_NR(1, 2),
850 .wdis = IMX_GPIO_NR(7, 12),
855 .gpio_pads = gw52xx_gpio_pads,
856 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
857 .dio_cfg = gw52xx_dio,
858 .dio_num = ARRAY_SIZE(gw52xx_dio),
859 .mezz_pwren = IMX_GPIO_NR(2, 19),
860 .mezz_irq = IMX_GPIO_NR(2, 18),
861 .gps_shdn = IMX_GPIO_NR(1, 27),
862 .usb_sel = IMX_GPIO_NR(1, 2),
863 .wdis = IMX_GPIO_NR(7, 12),
864 .msata_en = GP_MSATA_SEL,
865 .rs232_en = GP_RS232_EN,
866 .vsel_pin = IMX_GPIO_NR(6, 14),
867 .mmc_cd = IMX_GPIO_NR(7, 0),
872 .gpio_pads = gw53xx_gpio_pads,
873 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
874 .dio_cfg = gw53xx_dio,
875 .dio_num = ARRAY_SIZE(gw53xx_dio),
876 .mezz_pwren = IMX_GPIO_NR(2, 19),
877 .mezz_irq = IMX_GPIO_NR(2, 18),
878 .gps_shdn = IMX_GPIO_NR(1, 27),
879 .wdis = IMX_GPIO_NR(7, 12),
880 .msata_en = GP_MSATA_SEL,
881 .rs232_en = GP_RS232_EN,
882 .vsel_pin = IMX_GPIO_NR(6, 14),
883 .mmc_cd = IMX_GPIO_NR(7, 0),
888 .gpio_pads = gw54xx_gpio_pads,
889 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
890 .dio_cfg = gw54xx_dio,
891 .dio_num = ARRAY_SIZE(gw54xx_dio),
892 .mezz_pwren = IMX_GPIO_NR(2, 19),
893 .mezz_irq = IMX_GPIO_NR(2, 18),
894 .rs485en = IMX_GPIO_NR(7, 1),
895 .dioi2c_en = IMX_GPIO_NR(4, 5),
896 .pcie_sson = IMX_GPIO_NR(1, 20),
897 .wdis = IMX_GPIO_NR(5, 17),
898 .msata_en = GP_MSATA_SEL,
899 .rs232_en = GP_RS232_EN,
900 .vsel_pin = IMX_GPIO_NR(6, 14),
901 .mmc_cd = IMX_GPIO_NR(7, 0),
906 .gpio_pads = gw551x_gpio_pads,
907 .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2,
908 .dio_cfg = gw551x_dio,
909 .dio_num = ARRAY_SIZE(gw551x_dio),
910 .wdis = IMX_GPIO_NR(7, 12),
915 .gpio_pads = gw552x_gpio_pads,
916 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
917 .dio_cfg = gw552x_dio,
918 .dio_num = ARRAY_SIZE(gw552x_dio),
919 .usb_sel = IMX_GPIO_NR(1, 7),
920 .wdis = IMX_GPIO_NR(7, 12),
921 .msata_en = GP_MSATA_SEL,
926 .gpio_pads = gw553x_gpio_pads,
927 .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2,
928 .dio_cfg = gw553x_dio,
929 .dio_num = ARRAY_SIZE(gw553x_dio),
930 .wdis = IMX_GPIO_NR(7, 12),
931 .vsel_pin = IMX_GPIO_NR(6, 14),
932 .mmc_cd = IMX_GPIO_NR(7, 0),
937 .gpio_pads = gw560x_gpio_pads,
938 .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2,
939 .dio_cfg = gw560x_dio,
940 .dio_num = ARRAY_SIZE(gw560x_dio),
941 .mezz_pwren = IMX_GPIO_NR(2, 19),
942 .mezz_irq = IMX_GPIO_NR(2, 18),
943 .rs232_en = GP_RS232_EN,
944 .wdis = IMX_GPIO_NR(7, 12),
945 .mmc_cd = IMX_GPIO_NR(7, 0),
950 .gpio_pads = gw5901_gpio_pads,
951 .num_pads = ARRAY_SIZE(gw5901_gpio_pads)/2,
952 .dio_cfg = gw5901_dio,
957 .gpio_pads = gw5902_gpio_pads,
958 .num_pads = ARRAY_SIZE(gw5902_gpio_pads)/2,
959 .dio_cfg = gw5902_dio,
960 .rs232_en = GP_RS232_EN,
965 .gpio_pads = gw5903_gpio_pads,
966 .num_pads = ARRAY_SIZE(gw5903_gpio_pads)/2,
967 .dio_cfg = gw5903_dio,
968 .dio_num = ARRAY_SIZE(gw5903_dio),
969 .mmc_cd = IMX_GPIO_NR(6, 11),
974 .gpio_pads = gw5904_gpio_pads,
975 .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
976 .dio_cfg = gw5904_dio,
977 .dio_num = ARRAY_SIZE(gw5904_dio),
978 .mezz_pwren = IMX_GPIO_NR(2, 19),
979 .mezz_irq = IMX_GPIO_NR(2, 18),
984 .gpio_pads = gw5905_gpio_pads,
985 .num_pads = ARRAY_SIZE(gw5905_gpio_pads)/2,
986 .wdis = IMX_GPIO_NR(7, 13),
991 .gpio_pads = gw552x_gpio_pads,
992 .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2,
993 .dio_cfg = gw5906_dio,
994 .dio_num = ARRAY_SIZE(gw5906_dio),
995 .usb_sel = IMX_GPIO_NR(1, 7),
996 .wdis = IMX_GPIO_NR(7, 12),
997 .msata_en = GP_MSATA_SEL,
1002 .gpio_pads = gw51xx_gpio_pads,
1003 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
1004 .dio_cfg = gw51xx_dio,
1005 .dio_num = ARRAY_SIZE(gw51xx_dio),
1006 .wdis = IMX_GPIO_NR(7, 12),
1011 .gpio_pads = gw53xx_gpio_pads,
1012 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
1013 .dio_cfg = gw53xx_dio,
1014 .dio_num = ARRAY_SIZE(gw53xx_dio),
1015 .mezz_pwren = IMX_GPIO_NR(2, 19),
1016 .mezz_irq = IMX_GPIO_NR(2, 18),
1017 .gps_shdn = IMX_GPIO_NR(1, 27),
1018 .wdis = IMX_GPIO_NR(7, 12),
1019 .msata_en = GP_MSATA_SEL,
1020 .rs232_en = GP_RS232_EN,
1025 .gpio_pads = gw5904_gpio_pads,
1026 .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2,
1027 .dio_cfg = gw5904_dio,
1028 .dio_num = ARRAY_SIZE(gw5904_dio),
1029 .mezz_pwren = IMX_GPIO_NR(2, 19),
1030 .mezz_irq = IMX_GPIO_NR(2, 18),
1034 #define SETUP_GPIO_OUTPUT(gpio, name, level) \
1035 gpio_request(gpio, name); \
1036 gpio_direction_output(gpio, level);
1037 #define SETUP_GPIO_INPUT(gpio, name) \
1038 gpio_request(gpio, name); \
1039 gpio_direction_input(gpio);
1040 void setup_iomux_gpio(int board, struct ventana_board_info *info)
1042 if (board >= GW_UNKNOWN)
1045 /* board specific iomux */
1046 imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads,
1047 gpio_cfg[board].num_pads);
1050 if (gpio_cfg[board].rs232_en) {
1051 gpio_request(gpio_cfg[board].rs232_en, "rs232_en#");
1052 gpio_direction_output(gpio_cfg[board].rs232_en, 0);
1055 /* MSATA Enable - default to PCI */
1056 if (gpio_cfg[board].msata_en) {
1057 gpio_request(gpio_cfg[board].msata_en, "msata_en");
1058 gpio_direction_output(gpio_cfg[board].msata_en, 0);
1061 /* Expansion Mezzanine IO */
1062 if (gpio_cfg[board].mezz_pwren) {
1063 gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr");
1064 gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
1066 if (gpio_cfg[board].mezz_irq) {
1067 gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#");
1068 gpio_direction_input(gpio_cfg[board].mezz_irq);
1071 /* RS485 Transmit Enable */
1072 if (gpio_cfg[board].rs485en) {
1073 gpio_request(gpio_cfg[board].rs485en, "rs485_en");
1074 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1078 if (gpio_cfg[board].gps_shdn) {
1079 gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn");
1080 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1084 if (gpio_cfg[board].dioi2c_en) {
1085 gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#");
1086 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1089 /* PCICK_SSON: disable spread-spectrum clock */
1090 if (gpio_cfg[board].pcie_sson) {
1091 gpio_request(gpio_cfg[board].pcie_sson, "pci_sson");
1092 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1095 /* USBOTG mux routing */
1096 if (gpio_cfg[board].usb_sel) {
1097 gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel");
1098 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1101 /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */
1102 if (gpio_cfg[board].wdis) {
1103 gpio_request(gpio_cfg[board].wdis, "wlan_dis");
1104 gpio_direction_output(gpio_cfg[board].wdis, 1);
1107 /* sense vselect pin to see if we support uhs-i */
1108 if (gpio_cfg[board].vsel_pin) {
1109 gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect");
1110 gpio_direction_input(gpio_cfg[board].vsel_pin);
1111 gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin);
1115 if (gpio_cfg[board].mmc_cd) {
1116 gpio_request(gpio_cfg[board].mmc_cd, "sd_cd");
1117 gpio_direction_input(gpio_cfg[board].mmc_cd);
1120 /* Anything else board specific */
1123 gpio_request(IMX_GPIO_NR(4, 26), "12p0_en");
1124 gpio_direction_output(IMX_GPIO_NR(4, 26), 1);
1127 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "5P0V_EN", 1);
1130 gpio_request(IMX_GPIO_NR(3, 31) , "usbh1-ehci_pwr");
1131 gpio_direction_output(IMX_GPIO_NR(3, 31), 1);
1132 gpio_request(IMX_GPIO_NR(4, 15) , "usbh2-otg_pwr");
1133 gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
1134 gpio_request(IMX_GPIO_NR(4, 7) , "usbdpc_pwr");
1135 gpio_direction_output(IMX_GPIO_NR(4, 15), 1);
1136 gpio_request(IMX_GPIO_NR(1, 25) , "rgmii_en");
1137 gpio_direction_output(IMX_GPIO_NR(1, 25), 1);
1138 gpio_request(IMX_GPIO_NR(4, 6) , "touch_irq#");
1139 gpio_direction_input(IMX_GPIO_NR(4, 6));
1140 gpio_request(IMX_GPIO_NR(4, 8) , "touch_rst");
1141 gpio_direction_output(IMX_GPIO_NR(4, 8), 1);
1142 gpio_request(IMX_GPIO_NR(1, 7) , "bklt_12ven");
1143 gpio_direction_output(IMX_GPIO_NR(1, 7), 1);
1147 gpio_request(IMX_GPIO_NR(4, 23), "rs485_en");
1148 gpio_direction_output(IMX_GPIO_NR(4, 23), 0);
1149 gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#");
1150 gpio_direction_output(IMX_GPIO_NR(5, 11), 1);
1151 gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#");
1152 gpio_direction_output(IMX_GPIO_NR(5, 12), 1);
1153 gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#");
1154 gpio_direction_output(IMX_GPIO_NR(5, 13), 1);
1155 gpio_request(IMX_GPIO_NR(1, 15), "m2_off#");
1156 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
1157 gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#");
1158 gpio_direction_output(IMX_GPIO_NR(1, 14), 1);
1159 gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#");
1160 gpio_direction_output(IMX_GPIO_NR(1, 13), 1);
1163 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 7), "usb_pcisel", 0);
1164 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 9), "lvds_cabc", 1);
1165 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 14), "mipi_pdwn", 1);
1166 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(1, 15), "mipi_rst#", 0);
1167 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(2, 3), "emmy_pdwn#", 1);
1168 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 5), "spk_shdn#", 0);
1169 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 0);
1170 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 6), "touch_irq", 0);
1171 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 5), "flash_en1", 0);
1172 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 6), "flash_en2", 0);
1173 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 14), "dect_rst#", 1);
1174 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 17), "codec_rst#", 0);
1175 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(5, 26), "imu_den", 1);
1176 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(7, 12), "lvds_cabc", 0);
1179 * gauruntee touch controller comes out of reset with INT
1182 SETUP_GPIO_OUTPUT(IMX_GPIO_NR(4, 8), "touch_rst", 1);
1187 /* setup GPIO pinmux and default configuration per baseboard and env */
1188 void setup_board_gpio(int board, struct ventana_board_info *info)
1194 int quiet = simple_strtol(env_get("quiet"), NULL, 10);
1196 if (board >= GW_UNKNOWN)
1200 if (gpio_cfg[board].rs232_en) {
1201 gpio_direction_output(gpio_cfg[board].rs232_en,
1202 (hwconfig("rs232")) ? 0 : 1);
1206 if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
1207 gpio_direction_output(GP_MSATA_SEL,
1208 (hwconfig("msata")) ? 1 : 0);
1211 /* USBOTG Select (PCISKT or FrontPanel) */
1212 if (gpio_cfg[board].usb_sel) {
1213 gpio_direction_output(gpio_cfg[board].usb_sel,
1214 (hwconfig("usb_pcisel")) ? 1 : 0);
1218 * Configure DIO pinmux/padctl registers
1219 * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1221 for (i = 0; i < gpio_cfg[board].dio_num; i++) {
1222 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1223 iomux_v3_cfg_t ctrl = DIO_PAD_CFG;
1224 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1226 if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1])
1228 sprintf(arg, "dio%d", i);
1231 s = hwconfig_subarg(arg, "padctrl", &len);
1233 ctrl = MUX_PAD_CTRL(hextoul(s, NULL)
1234 & 0x1ffff) | MUX_MODE_SION;
1236 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1238 printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i,
1239 (cfg->gpio_param/32)+1,
1243 imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1245 gpio_requestf(cfg->gpio_param, "dio%d", i);
1246 gpio_direction_input(cfg->gpio_param);
1247 } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") &&
1249 if (!cfg->pwm_param) {
1250 printf("DIO%d: Error: pwm config invalid\n",
1255 printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
1256 imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1257 MUX_PAD_CTRL(ctrl));
1262 if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) {
1263 printf("MSATA: %s\n", (hwconfig("msata") ?
1264 "enabled" : "disabled"));
1266 if (gpio_cfg[board].rs232_en) {
1267 printf("RS232: %s\n", (hwconfig("rs232")) ?
1268 "enabled" : "disabled");
1273 /* setup board specific PMIC */
1274 void setup_pmic(void)
1277 struct ventana_board_info ventana_info;
1278 int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1279 const int i2c_pmic = 1;
1284 /* determine board revision */
1286 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1287 if (ventana_info.model[i] >= 'A') {
1288 rev = ventana_info.model[i];
1293 i2c_set_bus_num(i2c_pmic);
1295 /* configure PFUZE100 PMIC */
1296 if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) {
1297 debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR);
1298 power_pfuze100_init(i2c_pmic);
1299 p = pmic_get("PFUZE100");
1300 if (p && !pmic_probe(p)) {
1301 pmic_reg_read(p, PFUZE100_DEVICEID, ®);
1302 printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
1304 /* Set VGEN1 to 1.5V and enable */
1305 pmic_reg_read(p, PFUZE100_VGEN1VOL, ®);
1306 reg &= ~(LDO_VOL_MASK);
1307 reg |= (LDOA_1_50V | LDO_EN);
1308 pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
1310 /* Set SWBST to 5.0V and enable */
1311 pmic_reg_read(p, PFUZE100_SWBSTCON1, ®);
1312 reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
1313 reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT));
1314 pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
1316 if (board == GW54xx && (rev == 'G')) {
1318 pmic_reg_write(p, PFUZE100_VGEN5VOL, 0);
1320 /* Set VGEN6 to 2.5V and enable */
1321 pmic_reg_read(p, PFUZE100_VGEN6VOL, ®);
1322 reg &= ~(LDO_VOL_MASK);
1323 reg |= (LDOB_2_50V | LDO_EN);
1324 pmic_reg_write(p, PFUZE100_VGEN6VOL, reg);
1328 /* put all switchers in continuous mode */
1329 pmic_reg_read(p, PFUZE100_SW1ABMODE, ®);
1330 reg &= ~(SW_MODE_MASK);
1332 pmic_reg_write(p, PFUZE100_SW1ABMODE, reg);
1334 pmic_reg_read(p, PFUZE100_SW2MODE, ®);
1335 reg &= ~(SW_MODE_MASK);
1337 pmic_reg_write(p, PFUZE100_SW2MODE, reg);
1339 pmic_reg_read(p, PFUZE100_SW3AMODE, ®);
1340 reg &= ~(SW_MODE_MASK);
1342 pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
1344 pmic_reg_read(p, PFUZE100_SW3BMODE, ®);
1345 reg &= ~(SW_MODE_MASK);
1347 pmic_reg_write(p, PFUZE100_SW3BMODE, reg);
1349 pmic_reg_read(p, PFUZE100_SW4MODE, ®);
1350 reg &= ~(SW_MODE_MASK);
1352 pmic_reg_write(p, PFUZE100_SW4MODE, reg);
1355 /* configure LTC3676 PMIC */
1356 else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) {
1357 debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR);
1358 power_ltc3676_init(i2c_pmic);
1359 p = pmic_get("LTC3676_PMIC");
1360 if (!p || pmic_probe(p))
1362 puts("PMIC: LTC3676\n");
1364 * set board-specific scalar for max CPU frequency
1365 * per CPU based on the LDO enabled Operating Ranges
1366 * defined in the respective IMX6DQ and IMX6SDL
1367 * datasheets. The voltage resulting from the R1/R2
1368 * feedback inputs on Ventana is 1308mV. Note that this
1369 * is a bit shy of the Vmin of 1350mV in the datasheet
1370 * for LDO enabled mode but is as high as we can go.
1374 /* mask PGOOD during SW3 transition */
1375 pmic_reg_write(p, LTC3676_DVB3B,
1376 0x1f | LTC3676_PGOOD_MASK);
1377 /* set SW3 (VDD_ARM) */
1378 pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1381 /* mask PGOOD during SW3 transition */
1382 pmic_reg_write(p, LTC3676_DVB3B,
1383 0x1f | LTC3676_PGOOD_MASK);
1384 /* set SW3 (VDD_ARM) */
1385 pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1387 /* mask PGOOD during SW4 transition */
1388 pmic_reg_write(p, LTC3676_DVB4B,
1389 0x1f | LTC3676_PGOOD_MASK);
1390 /* set SW4 (VDD_SOC) */
1391 pmic_reg_write(p, LTC3676_DVB4A, 0x1f);
1394 /* mask PGOOD during SW1 transition */
1395 pmic_reg_write(p, LTC3676_DVB1B,
1396 0x1f | LTC3676_PGOOD_MASK);
1397 /* set SW1 (VDD_ARM) */
1398 pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
1400 /* mask PGOOD during SW3 transition */
1401 pmic_reg_write(p, LTC3676_DVB3B,
1402 0x1f | LTC3676_PGOOD_MASK);
1403 /* set SW3 (VDD_SOC) */
1404 pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1407 /* mask PGOOD during SW1 transition */
1408 pmic_reg_write(p, LTC3676_DVB1B,
1409 0x1f | LTC3676_PGOOD_MASK);
1410 /* set SW1 (VDD_SOC) */
1411 pmic_reg_write(p, LTC3676_DVB1A, 0x1f);
1413 /* mask PGOOD during SW3 transition */
1414 pmic_reg_write(p, LTC3676_DVB3B,
1415 0x1f | LTC3676_PGOOD_MASK);
1416 /* set SW3 (VDD_ARM) */
1417 pmic_reg_write(p, LTC3676_DVB3A, 0x1f);
1420 /* put all switchers in continuous mode */
1421 pmic_reg_write(p, LTC3676_BUCK1, 0xc0);
1422 pmic_reg_write(p, LTC3676_BUCK2, 0xc0);
1423 pmic_reg_write(p, LTC3676_BUCK3, 0xc0);
1424 pmic_reg_write(p, LTC3676_BUCK4, 0xc0);
1428 #include <fdt_support.h>
1429 #define WDOG1_ADDR 0x20bc000
1430 #define WDOG2_ADDR 0x20c0000
1431 #define GPIO3_ADDR 0x20a4000
1432 #define USDHC3_ADDR 0x2198000
1434 static void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
1436 int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1439 fdt_delprop(blob, off, "ext-reset-output");
1440 fdt_delprop(blob, off, "fsl,ext-reset-output");
1444 void ft_early_fixup(void *blob, int board_type)
1446 struct ventana_board_info *info = &ventana_info;
1450 /* determine board revision */
1451 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1452 if (ventana_info.model[i] >= 'A') {
1453 rev = ventana_info.model[i];
1459 * Board model specific fixups
1461 switch (board_type) {
1464 * disable wdog node for GW51xx-A/B to work around
1465 * errata causing wdog timer to be unreliable.
1467 if (rev >= 'A' && rev < 'C') {
1468 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1471 fdt_status_disabled(blob, i);
1474 /* GW51xx-E adds WDOG1_B external reset */
1476 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1480 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1481 if (info->model[4] == '2') {
1485 i = fdt_node_offset_by_compatible(blob, -1,
1488 range = (u32 *)fdt_getprop(blob, i,
1489 "reset-gpio", NULL);
1492 i = fdt_node_offset_by_compat_reg(blob,
1493 "fsl,imx6q-gpio", GPIO3_ADDR);
1495 handle = fdt_get_phandle(blob, i);
1497 range[0] = cpu_to_fdt32(handle);
1498 range[1] = cpu_to_fdt32(23);
1502 /* these have broken usd_vsel */
1503 if (strstr((const char *)info->model, "SP318-B") ||
1504 strstr((const char *)info->model, "SP331-B"))
1505 gpio_cfg[board_type].usd_vsel = 0;
1507 /* GW522x-B adds WDOG1_B external reset */
1509 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1512 /* GW520x-E adds WDOG1_B external reset */
1513 else if (info->model[4] == '0' && rev < 'E')
1514 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1518 /* GW53xx-E adds WDOG1_B external reset */
1520 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1525 * disable serial2 node for GW54xx for compatibility with older
1526 * 3.10.x kernel that improperly had this node enabled in the DT
1528 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
1531 /* GW54xx-E adds WDOG2_B external reset */
1533 ft_board_wdog_fixup(blob, WDOG2_ADDR);
1537 /* GW551x-C adds WDOG1_B external reset */
1539 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1543 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1545 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1549 /* remove no-1-8-v if UHS-I support is present */
1550 if (gpio_cfg[board_type].usd_vsel) {
1551 debug("Enabling UHS-I support\n");
1552 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1555 fdt_delprop(blob, i, "no-1-8-v");
1559 #ifdef CONFIG_FSL_ESDHC_IMX
1560 static struct fsl_esdhc_cfg usdhc_cfg[2];
1562 int board_mmc_init(struct bd_info *bis)
1564 struct ventana_board_info ventana_info;
1565 int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1568 switch (board_type) {
1573 /* usdhc3: 4bit microSD */
1574 SETUP_IOMUX_PADS(usdhc3_pads);
1575 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
1576 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
1577 usdhc_cfg[0].max_bus_width = 4;
1578 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
1580 /* usdhc2: 8-bit eMMC */
1581 SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads);
1582 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
1583 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
1584 usdhc_cfg[0].max_bus_width = 8;
1585 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
1588 /* usdhc3: 4-bit microSD */
1589 SETUP_IOMUX_PADS(usdhc3_pads);
1590 usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR;
1591 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
1592 usdhc_cfg[1].max_bus_width = 4;
1593 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
1595 /* usdhc3: 8-bit eMMC */
1596 SETUP_IOMUX_PADS(gw5904_emmc_pads);
1597 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
1598 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
1599 usdhc_cfg[0].max_bus_width = 8;
1600 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
1603 /* usdhc2: 4-bit microSD */
1604 SETUP_IOMUX_PADS(gw5904_mmc_pads);
1605 usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
1606 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
1607 usdhc_cfg[1].max_bus_width = 4;
1608 return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
1612 /* usdhc3: 8bit eMMC */
1613 SETUP_IOMUX_PADS(gw5904_emmc_pads);
1614 usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
1615 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
1616 usdhc_cfg[0].max_bus_width = 8;
1617 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
1619 /* doesn't have MMC */
1625 int board_mmc_getcd(struct mmc *mmc)
1627 struct ventana_board_info ventana_info;
1628 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
1629 int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
1630 int gpio = gpio_cfg[board].mmc_cd;
1635 /* emmc is always present */
1636 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
1643 /* emmc is always present */
1644 if (cfg->esdhc_base == USDHC3_BASE_ADDR)
1650 debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio));
1651 return !gpio_get_value(gpio);
1657 #endif /* CONFIG_FSL_ESDHC_IMX */