arch/riscv/dts/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/clock/starfive,jh7110-crg.h>
   8 #include <dt-bindings/reset/starfive,jh7110-crg.h>
   9
  10 / {
  11         compatible = "starfive,jh7110";
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 S7_0: cpu@0 {
  20                         compatible = "sifive,s7", "riscv";
  21                         reg = <0>;
  22                         device_type = "cpu";
  23                         i-cache-block-size = <64>;
  24                         i-cache-sets = <64>;
  25                         i-cache-size = <16384>;
  26                         next-level-cache = <&ccache>;
  27                         riscv,isa = "rv64imac_zba_zbb";
  28                         status = "disabled";
  29
  30                         cpu0_intc: interrupt-controller {
  31                                 compatible = "riscv,cpu-intc";
  32                                 interrupt-controller;
  33                                 #interrupt-cells = <1>;
  34                         };
  35                 };
  36
  37                 U74_1: cpu@1 {
  38                         compatible = "sifive,u74-mc", "riscv";
  39                         reg = <1>;
  40                         d-cache-block-size = <64>;
  41                         d-cache-sets = <64>;
  42                         d-cache-size = <32768>;
  43                         d-tlb-sets = <1>;
  44                         d-tlb-size = <40>;
  45                         device_type = "cpu";
  46                         i-cache-block-size = <64>;
  47                         i-cache-sets = <64>;
  48                         i-cache-size = <32768>;
  49                         i-tlb-sets = <1>;
  50                         i-tlb-size = <40>;
  51                         mmu-type = "riscv,sv39";
  52                         next-level-cache = <&ccache>;
  53                         riscv,isa = "rv64imafdc_zba_zbb";
  54                         tlb-split;
  55
  56                         cpu1_intc: interrupt-controller {
  57                                 compatible = "riscv,cpu-intc";
  58                                 interrupt-controller;
  59                                 #interrupt-cells = <1>;
  60                         };
  61                 };
  62
  63                 U74_2: cpu@2 {
  64                         compatible = "sifive,u74-mc", "riscv";
  65                         reg = <2>;
  66                         d-cache-block-size = <64>;
  67                         d-cache-sets = <64>;
  68                         d-cache-size = <32768>;
  69                         d-tlb-sets = <1>;
  70                         d-tlb-size = <40>;
  71                         device_type = "cpu";
  72                         i-cache-block-size = <64>;
  73                         i-cache-sets = <64>;
  74                         i-cache-size = <32768>;
  75                         i-tlb-sets = <1>;
  76                         i-tlb-size = <40>;
  77                         mmu-type = "riscv,sv39";
  78                         next-level-cache = <&ccache>;
  79                         riscv,isa = "rv64imafdc_zba_zbb";
  80                         tlb-split;
  81
  82                         cpu2_intc: interrupt-controller {
  83                                 compatible = "riscv,cpu-intc";
  84                                 interrupt-controller;
  85                                 #interrupt-cells = <1>;
  86                         };
  87                 };
  88
  89                 U74_3: cpu@3 {
  90                         compatible = "sifive,u74-mc", "riscv";
  91                         reg = <3>;
  92                         d-cache-block-size = <64>;
  93                         d-cache-sets = <64>;
  94                         d-cache-size = <32768>;
  95                         d-tlb-sets = <1>;
  96                         d-tlb-size = <40>;
  97                         device_type = "cpu";
  98                         i-cache-block-size = <64>;
  99                         i-cache-sets = <64>;
 100                         i-cache-size = <32768>;
 101                         i-tlb-sets = <1>;
 102                         i-tlb-size = <40>;
 103                         mmu-type = "riscv,sv39";
 104                         next-level-cache = <&ccache>;
 105                         riscv,isa = "rv64imafdc_zba_zbb";
 106                         tlb-split;
 107
 108                         cpu3_intc: interrupt-controller {
 109                                 compatible = "riscv,cpu-intc";
 110                                 interrupt-controller;
 111                                 #interrupt-cells = <1>;
 112                         };
 113                 };
 114
 115                 U74_4: cpu@4 {
 116                         compatible = "sifive,u74-mc", "riscv";
 117                         reg = <4>;
 118                         d-cache-block-size = <64>;
 119                         d-cache-sets = <64>;
 120                         d-cache-size = <32768>;
 121                         d-tlb-sets = <1>;
 122                         d-tlb-size = <40>;
 123                         device_type = "cpu";
 124                         i-cache-block-size = <64>;
 125                         i-cache-sets = <64>;
 126                         i-cache-size = <32768>;
 127                         i-tlb-sets = <1>;
 128                         i-tlb-size = <40>;
 129                         mmu-type = "riscv,sv39";
 130                         next-level-cache = <&ccache>;
 131                         riscv,isa = "rv64imafdc_zba_zbb";
 132                         tlb-split;
 133
 134                         cpu4_intc: interrupt-controller {
 135                                 compatible = "riscv,cpu-intc";
 136                                 interrupt-controller;
 137                                 #interrupt-cells = <1>;
 138                         };
 139                 };
 140
 141                 cpu-map {
 142                         cluster0 {
 143                                 core0 {
 144                                         cpu = <&S7_0>;
 145                                 };
 146
 147                                 core1 {
 148                                         cpu = <&U74_1>;
 149                                 };
 150
 151                                 core2 {
 152                                         cpu = <&U74_2>;
 153                                 };
 154
 155                                 core3 {
 156                                         cpu = <&U74_3>;
 157                                 };
 158
 159                                 core4 {
 160                                         cpu = <&U74_4>;
 161                                 };
 162                         };
 163                 };
 164         };
 165
 166         osc: oscillator {
 167                 compatible = "fixed-clock";
 168                 clock-output-names = "osc";
 169                 #clock-cells = <0>;
 170         };
 171
 172         rtc_osc: rtc-oscillator {
 173                 compatible = "fixed-clock";
 174                 clock-output-names = "rtc_osc";
 175                 #clock-cells = <0>;
 176         };
 177
 178         gmac0_rmii_refin: gmac0-rmii-refin-clock {
 179                 compatible = "fixed-clock";
 180                 clock-output-names = "gmac0_rmii_refin";
 181                 #clock-cells = <0>;
 182         };
 183
 184         gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
 185                 compatible = "fixed-clock";
 186                 clock-output-names = "gmac0_rgmii_rxin";
 187                 #clock-cells = <0>;
 188         };
 189
 190         gmac1_rmii_refin: gmac1-rmii-refin-clock {
 191                 compatible = "fixed-clock";
 192                 clock-output-names = "gmac1_rmii_refin";
 193                 #clock-cells = <0>;
 194         };
 195
 196         gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
 197                 compatible = "fixed-clock";
 198                 clock-output-names = "gmac1_rgmii_rxin";
 199                 #clock-cells = <0>;
 200         };
 201
 202         i2stx_bclk_ext: i2stx-bclk-ext-clock {
 203                 compatible = "fixed-clock";
 204                 clock-output-names = "i2stx_bclk_ext";
 205                 #clock-cells = <0>;
 206         };
 207
 208         i2stx_lrck_ext: i2stx-lrck-ext-clock {
 209                 compatible = "fixed-clock";
 210                 clock-output-names = "i2stx_lrck_ext";
 211                 #clock-cells = <0>;
 212         };
 213
 214         i2srx_bclk_ext: i2srx-bclk-ext-clock {
 215                 compatible = "fixed-clock";
 216                 clock-output-names = "i2srx_bclk_ext";
 217                 #clock-cells = <0>;
 218         };
 219
 220         i2srx_lrck_ext: i2srx-lrck-ext-clock {
 221                 compatible = "fixed-clock";
 222                 clock-output-names = "i2srx_lrck_ext";
 223                 #clock-cells = <0>;
 224         };
 225
 226         tdm_ext: tdm-ext-clock {
 227                 compatible = "fixed-clock";
 228                 clock-output-names = "tdm_ext";
 229                 #clock-cells = <0>;
 230         };
 231
 232         mclk_ext: mclk-ext-clock {
 233                 compatible = "fixed-clock";
 234                 clock-output-names = "mclk_ext";
 235                 #clock-cells = <0>;
 236         };
 237
 238         soc {
 239                 compatible = "simple-bus";
 240                 interrupt-parent = <&plic>;
 241                 #address-cells = <2>;
 242                 #size-cells = <2>;
 243                 ranges;
 244
 245                 clint: timer@2000000 {
 246                         compatible = "starfive,jh7110-clint", "sifive,clint0";
 247                         reg = <0x0 0x2000000 0x0 0x10000>;
 248                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 249                                               <&cpu1_intc 3>, <&cpu1_intc 7>,
 250                                               <&cpu2_intc 3>, <&cpu2_intc 7>,
 251                                               <&cpu3_intc 3>, <&cpu3_intc 7>,
 252                                               <&cpu4_intc 3>, <&cpu4_intc 7>;
 253                 };
 254
 255                 plic: interrupt-controller@c000000 {
 256                         compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 257                         reg = <0x0 0xc000000 0x0 0x4000000>;
 258                         interrupts-extended = <&cpu0_intc 11>,
 259                                               <&cpu1_intc 11>, <&cpu1_intc 9>,
 260                                               <&cpu2_intc 11>, <&cpu2_intc 9>,
 261                                               <&cpu3_intc 11>, <&cpu3_intc 9>,
 262                                               <&cpu4_intc 11>, <&cpu4_intc 9>;
 263                         interrupt-controller;
 264                         #interrupt-cells = <1>;
 265                         #address-cells = <0>;
 266                         riscv,ndev = <136>;
 267                 };
 268
 269                 ccache: cache-controller@2010000 {
 270                         compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
 271                         reg = <0x0 0x2010000 0x0 0x4000>;
 272                         interrupts = <1>, <3>, <4>, <2>;
 273                         cache-block-size = <64>;
 274                         cache-level = <2>;
 275                         cache-sets = <2048>;
 276                         cache-size = <2097152>;
 277                         cache-unified;
 278                 };
 279
 280                 uart0: serial@10000000 {
 281                         compatible = "snps,dw-apb-uart";
 282                         reg = <0x0 0x10000000 0x0 0x10000>;
 283                         clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
 284                                  <&syscrg JH7110_SYSCLK_UART0_APB>;
 285                         clock-names = "baudclk", "apb_pclk";
 286                         resets = <&syscrg JH7110_SYSRST_UART0_APB>,
 287                                  <&syscrg JH7110_SYSRST_UART0_CORE>;
 288                         interrupts = <32>;
 289                         reg-io-width = <4>;
 290                         reg-shift = <2>;
 291                         status = "disabled";
 292                 };
 293
 294                 uart1: serial@10010000 {
 295                         compatible = "snps,dw-apb-uart";
 296                         reg = <0x0 0x10010000 0x0 0x10000>;
 297                         clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
 298                                  <&syscrg JH7110_SYSCLK_UART1_APB>;
 299                         clock-names = "baudclk", "apb_pclk";
 300                         resets = <&syscrg JH7110_SYSRST_UART1_APB>,
 301                                  <&syscrg JH7110_SYSRST_UART1_CORE>;
 302                         interrupts = <33>;
 303                         reg-io-width = <4>;
 304                         reg-shift = <2>;
 305                         status = "disabled";
 306                 };
 307
 308                 uart2: serial@10020000 {
 309                         compatible = "snps,dw-apb-uart";
 310                         reg = <0x0 0x10020000 0x0 0x10000>;
 311                         clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
 312                                  <&syscrg JH7110_SYSCLK_UART2_APB>;
 313                         clock-names = "baudclk", "apb_pclk";
 314                         resets = <&syscrg JH7110_SYSRST_UART2_APB>,
 315                                  <&syscrg JH7110_SYSRST_UART2_CORE>;
 316                         interrupts = <34>;
 317                         reg-io-width = <4>;
 318                         reg-shift = <2>;
 319                         status = "disabled";
 320                 };
 321
 322                 i2c0: i2c@10030000 {
 323                         compatible = "snps,designware-i2c";
 324                         reg = <0x0 0x10030000 0x0 0x10000>;
 325                         clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
 326                         clock-names = "ref";
 327                         resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
 328                         interrupts = <35>;
 329                         #address-cells = <1>;
 330                         #size-cells = <0>;
 331                         status = "disabled";
 332                 };
 333
 334                 i2c1: i2c@10040000 {
 335                         compatible = "snps,designware-i2c";
 336                         reg = <0x0 0x10040000 0x0 0x10000>;
 337                         clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
 338                         clock-names = "ref";
 339                         resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
 340                         interrupts = <36>;
 341                         #address-cells = <1>;
 342                         #size-cells = <0>;
 343                         status = "disabled";
 344                 };
 345
 346                 i2c2: i2c@10050000 {
 347                         compatible = "snps,designware-i2c";
 348                         reg = <0x0 0x10050000 0x0 0x10000>;
 349                         clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
 350                         clock-names = "ref";
 351                         resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
 352                         interrupts = <37>;
 353                         #address-cells = <1>;
 354                         #size-cells = <0>;
 355                         status = "disabled";
 356                 };
 357
 358                 stgcrg: clock-controller@10230000 {
 359                         compatible = "starfive,jh7110-stgcrg";
 360                         reg = <0x0 0x10230000 0x0 0x10000>;
 361                         #clock-cells = <1>;
 362                         #reset-cells = <1>;
 363                 };
 364
 365                 stg_syscon: stg_syscon@10240000 {
 366                         compatible = "starfive,jh7110-stg-syscon","syscon";
 367                         reg = <0x0 0x10240000 0x0 0x1000>;
 368                 };
 369
 370                 uart3: serial@12000000 {
 371                         compatible = "snps,dw-apb-uart";
 372                         reg = <0x0 0x12000000 0x0 0x10000>;
 373                         clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
 374                                  <&syscrg JH7110_SYSCLK_UART3_APB>;
 375                         clock-names = "baudclk", "apb_pclk";
 376                         resets = <&syscrg JH7110_SYSRST_UART3_APB>,
 377                                  <&syscrg JH7110_SYSRST_UART3_CORE>;
 378                         interrupts = <45>;
 379                         reg-io-width = <4>;
 380                         reg-shift = <2>;
 381                         status = "disabled";
 382                 };
 383
 384                 uart4: serial@12010000 {
 385                         compatible = "snps,dw-apb-uart";
 386                         reg = <0x0 0x12010000 0x0 0x10000>;
 387                         clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
 388                                  <&syscrg JH7110_SYSCLK_UART4_APB>;
 389                         clock-names = "baudclk", "apb_pclk";
 390                         resets = <&syscrg JH7110_SYSRST_UART4_APB>,
 391                                  <&syscrg JH7110_SYSRST_UART4_CORE>;
 392                         interrupts = <46>;
 393                         reg-io-width = <4>;
 394                         reg-shift = <2>;
 395                         status = "disabled";
 396                 };
 397
 398                 uart5: serial@12020000 {
 399                         compatible = "snps,dw-apb-uart";
 400                         reg = <0x0 0x12020000 0x0 0x10000>;
 401                         clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
 402                                  <&syscrg JH7110_SYSCLK_UART5_APB>;
 403                         clock-names = "baudclk", "apb_pclk";
 404                         resets = <&syscrg JH7110_SYSRST_UART5_APB>,
 405                                  <&syscrg JH7110_SYSRST_UART5_CORE>;
 406                         interrupts = <47>;
 407                         reg-io-width = <4>;
 408                         reg-shift = <2>;
 409                         status = "disabled";
 410                 };
 411
 412                 i2c3: i2c@12030000 {
 413                         compatible = "snps,designware-i2c";
 414                         reg = <0x0 0x12030000 0x0 0x10000>;
 415                         clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
 416                         clock-names = "ref";
 417                         resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
 418                         interrupts = <48>;
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                         status = "disabled";
 422                 };
 423
 424                 i2c4: i2c@12040000 {
 425                         compatible = "snps,designware-i2c";
 426                         reg = <0x0 0x12040000 0x0 0x10000>;
 427                         clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
 428                         clock-names = "ref";
 429                         resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
 430                         interrupts = <49>;
 431                         #address-cells = <1>;
 432                         #size-cells = <0>;
 433                         status = "disabled";
 434                 };
 435
 436                 i2c5: i2c@12050000 {
 437                         compatible = "snps,designware-i2c";
 438                         reg = <0x0 0x12050000 0x0 0x10000>;
 439                         clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
 440                         clock-names = "ref";
 441                         resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
 442                         interrupts = <50>;
 443                         #address-cells = <1>;
 444                         #size-cells = <0>;
 445                         status = "disabled";
 446                 };
 447
 448                 i2c6: i2c@12060000 {
 449                         compatible = "snps,designware-i2c";
 450                         reg = <0x0 0x12060000 0x0 0x10000>;
 451                         clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
 452                         clock-names = "ref";
 453                         resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
 454                         interrupts = <51>;
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         status = "disabled";
 458                 };
 459
 460                 qspi: spi@13010000 {
 461                         compatible = "cdns,qspi-nor";
 462                         reg = <0x0 0x13010000 0x0 0x10000
 463                                 0x0 0x21000000 0x0 0x400000>;
 464                         clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
 465                         clock-names = "clk_ref";
 466                         resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
 467                                  <&syscrg JH7110_SYSRST_QSPI_AHB>,
 468                                  <&syscrg JH7110_SYSRST_QSPI_REF>;
 469                         reset-names = "rst_apb", "rst_ahb", "rst_ref";
 470                         cdns,fifo-depth = <256>;
 471                         cdns,fifo-width = <4>;
 472                         #address-cells = <1>;
 473                         #size-cells = <0>;
 474                 };
 475
 476                 syscrg: clock-controller@13020000 {
 477                         compatible = "starfive,jh7110-syscrg";
 478                         reg = <0x0 0x13020000 0x0 0x10000>;
 479                         clocks = <&osc>, <&gmac1_rmii_refin>,
 480                                  <&gmac1_rgmii_rxin>,
 481                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 482                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 483                                  <&tdm_ext>, <&mclk_ext>;
 484                         clock-names = "osc", "gmac1_rmii_refin",
 485                                       "gmac1_rgmii_rxin",
 486                                       "i2stx_bclk_ext", "i2stx_lrck_ext",
 487                                       "i2srx_bclk_ext", "i2srx_lrck_ext",
 488                                       "tdm_ext", "mclk_ext";
 489                         #clock-cells = <1>;
 490                         #reset-cells = <1>;
 491                 };
 492
 493                 sys_syscon: sys_syscon@13030000 {
 494                         compatible = "starfive,jh7110-sys-syscon","syscon";
 495                         reg = <0x0 0x13030000 0x0 0x1000>;
 496                 };
 497
 498                 sysgpio: pinctrl@13040000 {
 499                         compatible = "starfive,jh7110-sys-pinctrl";
 500                         reg = <0x0 0x13040000 0x0 0x10000>;
 501                         clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
 502                         resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
 503                         interrupts = <86>;
 504                         interrupt-controller;
 505                         #interrupt-cells = <2>;
 506                         gpio-controller;
 507                         #gpio-cells = <2>;
 508                 };
 509
 510                 mmc0: mmc@16010000 {
 511                         compatible = "starfive,jh7110-mmc";
 512                         reg = <0x0 0x16010000 0x0 0x10000>;
 513                         clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
 514                                  <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
 515                         clock-names = "biu", "ciu";
 516                         resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
 517                         reset-names = "reset";
 518                         interrupts = <74>;
 519                         fifo-depth = <32>;
 520                         fifo-watermark-aligned;
 521                         data-addr = <0>;
 522                         starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
 523                         status = "disabled";
 524                 };
 525
 526                 mmc1: mmc@16020000 {
 527                         compatible = "starfive,jh7110-mmc";
 528                         reg = <0x0 0x16020000 0x0 0x10000>;
 529                         clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
 530                                  <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
 531                         clock-names = "biu", "ciu";
 532                         resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
 533                         reset-names = "reset";
 534                         interrupts = <75>;
 535                         fifo-depth = <32>;
 536                         fifo-watermark-aligned;
 537                         data-addr = <0>;
 538                         starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
 539                         status = "disabled";
 540                 };
 541
 542                 aoncrg: clock-controller@17000000 {
 543                         compatible = "starfive,jh7110-aoncrg";
 544                         reg = <0x0 0x17000000 0x0 0x10000>;
 545                         clocks = <&osc>, <&rtc_osc>,
 546                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
 547                                  <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 548                                  <&syscrg JH7110_SYSCLK_APB_BUS>,
 549                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
 550                         clock-names = "osc", "rtc_osc", "gmac0_rmii_refin",
 551                                       "gmac0_rgmii_rxin", "stg_axiahb",
 552                                       "apb_bus", "gmac0_gtxclk";
 553                         #clock-cells = <1>;
 554                         #reset-cells = <1>;
 555                 };
 556
 557                 aon_syscon: aon_syscon@17010000 {
 558                         compatible = "starfive,jh7110-aon-syscon","syscon";
 559                         reg = <0x0 0x17010000 0x0 0x1000>;
 560                 };
 561
 562                 aongpio: pinctrl@17020000 {
 563                         compatible = "starfive,jh7110-aon-pinctrl";
 564                         reg = <0x0 0x17020000 0x0 0x10000>;
 565                         resets = <&aoncrg JH7110_AONRST_IOMUX>;
 566                         interrupts = <85>;
 567                         interrupt-controller;
 568                         #interrupt-cells = <2>;
 569                         gpio-controller;
 570                         #gpio-cells = <2>;
 571                 };
 572         };
 573 };