arch/riscv/dts/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  */
   5
   6 /dts-v1/;
   7 #include <dt-bindings/clock/starfive,jh7110-crg.h>
   8 #include <dt-bindings/reset/starfive,jh7110-crg.h>
   9
  10 / {
  11         compatible = "starfive,jh7110";
  12         #address-cells = <2>;
  13         #size-cells = <2>;
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 S7_0: cpu@0 {
  20                         compatible = "sifive,s7", "riscv";
  21                         reg = <0>;
  22                         device_type = "cpu";
  23                         i-cache-block-size = <64>;
  24                         i-cache-sets = <64>;
  25                         i-cache-size = <16384>;
  26                         next-level-cache = <&ccache>;
  27                         riscv,isa = "rv64imac_zba_zbb";
  28                         status = "disabled";
  29
  30                         cpu0_intc: interrupt-controller {
  31                                 compatible = "riscv,cpu-intc";
  32                                 interrupt-controller;
  33                                 #interrupt-cells = <1>;
  34                         };
  35                 };
  36
  37                 U74_1: cpu@1 {
  38                         compatible = "sifive,u74-mc", "riscv";
  39                         reg = <1>;
  40                         d-cache-block-size = <64>;
  41                         d-cache-sets = <64>;
  42                         d-cache-size = <32768>;
  43                         d-tlb-sets = <1>;
  44                         d-tlb-size = <40>;
  45                         device_type = "cpu";
  46                         i-cache-block-size = <64>;
  47                         i-cache-sets = <64>;
  48                         i-cache-size = <32768>;
  49                         i-tlb-sets = <1>;
  50                         i-tlb-size = <40>;
  51                         mmu-type = "riscv,sv39";
  52                         next-level-cache = <&ccache>;
  53                         riscv,isa = "rv64imafdc_zba_zbb";
  54                         tlb-split;
  55
  56                         cpu1_intc: interrupt-controller {
  57                                 compatible = "riscv,cpu-intc";
  58                                 interrupt-controller;
  59                                 #interrupt-cells = <1>;
  60                         };
  61                 };
  62
  63                 U74_2: cpu@2 {
  64                         compatible = "sifive,u74-mc", "riscv";
  65                         reg = <2>;
  66                         d-cache-block-size = <64>;
  67                         d-cache-sets = <64>;
  68                         d-cache-size = <32768>;
  69                         d-tlb-sets = <1>;
  70                         d-tlb-size = <40>;
  71                         device_type = "cpu";
  72                         i-cache-block-size = <64>;
  73                         i-cache-sets = <64>;
  74                         i-cache-size = <32768>;
  75                         i-tlb-sets = <1>;
  76                         i-tlb-size = <40>;
  77                         mmu-type = "riscv,sv39";
  78                         next-level-cache = <&ccache>;
  79                         riscv,isa = "rv64imafdc_zba_zbb";
  80                         tlb-split;
  81
  82                         cpu2_intc: interrupt-controller {
  83                                 compatible = "riscv,cpu-intc";
  84                                 interrupt-controller;
  85                                 #interrupt-cells = <1>;
  86                         };
  87                 };
  88
  89                 U74_3: cpu@3 {
  90                         compatible = "sifive,u74-mc", "riscv";
  91                         reg = <3>;
  92                         d-cache-block-size = <64>;
  93                         d-cache-sets = <64>;
  94                         d-cache-size = <32768>;
  95                         d-tlb-sets = <1>;
  96                         d-tlb-size = <40>;
  97                         device_type = "cpu";
  98                         i-cache-block-size = <64>;
  99                         i-cache-sets = <64>;
 100                         i-cache-size = <32768>;
 101                         i-tlb-sets = <1>;
 102                         i-tlb-size = <40>;
 103                         mmu-type = "riscv,sv39";
 104                         next-level-cache = <&ccache>;
 105                         riscv,isa = "rv64imafdc_zba_zbb";
 106                         tlb-split;
 107
 108                         cpu3_intc: interrupt-controller {
 109                                 compatible = "riscv,cpu-intc";
 110                                 interrupt-controller;
 111                                 #interrupt-cells = <1>;
 112                         };
 113                 };
 114
 115                 U74_4: cpu@4 {
 116                         compatible = "sifive,u74-mc", "riscv";
 117                         reg = <4>;
 118                         d-cache-block-size = <64>;
 119                         d-cache-sets = <64>;
 120                         d-cache-size = <32768>;
 121                         d-tlb-sets = <1>;
 122                         d-tlb-size = <40>;
 123                         device_type = "cpu";
 124                         i-cache-block-size = <64>;
 125                         i-cache-sets = <64>;
 126                         i-cache-size = <32768>;
 127                         i-tlb-sets = <1>;
 128                         i-tlb-size = <40>;
 129                         mmu-type = "riscv,sv39";
 130                         next-level-cache = <&ccache>;
 131                         riscv,isa = "rv64imafdc_zba_zbb";
 132                         tlb-split;
 133
 134                         cpu4_intc: interrupt-controller {
 135                                 compatible = "riscv,cpu-intc";
 136                                 interrupt-controller;
 137                                 #interrupt-cells = <1>;
 138                         };
 139                 };
 140
 141                 cpu-map {
 142                         cluster0 {
 143                                 core0 {
 144                                         cpu = <&S7_0>;
 145                                 };
 146
 147                                 core1 {
 148                                         cpu = <&U74_1>;
 149                                 };
 150
 151                                 core2 {
 152                                         cpu = <&U74_2>;
 153                                 };
 154
 155                                 core3 {
 156                                         cpu = <&U74_3>;
 157                                 };
 158
 159                                 core4 {
 160                                         cpu = <&U74_4>;
 161                                 };
 162                         };
 163                 };
 164         };
 165
 166         timer {
 167                 compatible = "riscv,timer";
 168                 interrupts-extended = <&cpu0_intc 5>,
 169                                       <&cpu1_intc 5>,
 170                                       <&cpu2_intc 5>,
 171                                       <&cpu3_intc 5>,
 172                                       <&cpu4_intc 5>;
 173         };
 174
 175         osc: oscillator {
 176                 compatible = "fixed-clock";
 177                 clock-output-names = "osc";
 178                 #clock-cells = <0>;
 179         };
 180
 181         rtc_osc: rtc-oscillator {
 182                 compatible = "fixed-clock";
 183                 clock-output-names = "rtc_osc";
 184                 #clock-cells = <0>;
 185         };
 186
 187         gmac0_rmii_refin: gmac0-rmii-refin-clock {
 188                 compatible = "fixed-clock";
 189                 clock-output-names = "gmac0_rmii_refin";
 190                 #clock-cells = <0>;
 191         };
 192
 193         gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
 194                 compatible = "fixed-clock";
 195                 clock-output-names = "gmac0_rgmii_rxin";
 196                 #clock-cells = <0>;
 197         };
 198
 199         gmac1_rmii_refin: gmac1-rmii-refin-clock {
 200                 compatible = "fixed-clock";
 201                 clock-output-names = "gmac1_rmii_refin";
 202                 #clock-cells = <0>;
 203         };
 204
 205         gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
 206                 compatible = "fixed-clock";
 207                 clock-output-names = "gmac1_rgmii_rxin";
 208                 #clock-cells = <0>;
 209         };
 210
 211         i2stx_bclk_ext: i2stx-bclk-ext-clock {
 212                 compatible = "fixed-clock";
 213                 clock-output-names = "i2stx_bclk_ext";
 214                 #clock-cells = <0>;
 215         };
 216
 217         i2stx_lrck_ext: i2stx-lrck-ext-clock {
 218                 compatible = "fixed-clock";
 219                 clock-output-names = "i2stx_lrck_ext";
 220                 #clock-cells = <0>;
 221         };
 222
 223         i2srx_bclk_ext: i2srx-bclk-ext-clock {
 224                 compatible = "fixed-clock";
 225                 clock-output-names = "i2srx_bclk_ext";
 226                 #clock-cells = <0>;
 227         };
 228
 229         i2srx_lrck_ext: i2srx-lrck-ext-clock {
 230                 compatible = "fixed-clock";
 231                 clock-output-names = "i2srx_lrck_ext";
 232                 #clock-cells = <0>;
 233         };
 234
 235         tdm_ext: tdm-ext-clock {
 236                 compatible = "fixed-clock";
 237                 clock-output-names = "tdm_ext";
 238                 #clock-cells = <0>;
 239         };
 240
 241         mclk_ext: mclk-ext-clock {
 242                 compatible = "fixed-clock";
 243                 clock-output-names = "mclk_ext";
 244                 #clock-cells = <0>;
 245         };
 246
 247         stmmac_axi_setup: stmmac-axi-config {
 248                 snps,lpi_en;
 249                 snps,wr_osr_lmt = <4>;
 250                 snps,rd_osr_lmt = <4>;
 251                 snps,blen = <256 128 64 32 0 0 0>;
 252         };
 253
 254         soc {
 255                 compatible = "simple-bus";
 256                 interrupt-parent = <&plic>;
 257                 #address-cells = <2>;
 258                 #size-cells = <2>;
 259                 ranges;
 260
 261                 clint: timer@2000000 {
 262                         compatible = "starfive,jh7110-clint", "sifive,clint0";
 263                         reg = <0x0 0x2000000 0x0 0x10000>;
 264                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 265                                               <&cpu1_intc 3>, <&cpu1_intc 7>,
 266                                               <&cpu2_intc 3>, <&cpu2_intc 7>,
 267                                               <&cpu3_intc 3>, <&cpu3_intc 7>,
 268                                               <&cpu4_intc 3>, <&cpu4_intc 7>;
 269                 };
 270
 271                 plic: interrupt-controller@c000000 {
 272                         compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 273                         reg = <0x0 0xc000000 0x0 0x4000000>;
 274                         interrupts-extended = <&cpu0_intc 11>,
 275                                               <&cpu1_intc 11>, <&cpu1_intc 9>,
 276                                               <&cpu2_intc 11>, <&cpu2_intc 9>,
 277                                               <&cpu3_intc 11>, <&cpu3_intc 9>,
 278                                               <&cpu4_intc 11>, <&cpu4_intc 9>;
 279                         interrupt-controller;
 280                         #interrupt-cells = <1>;
 281                         #address-cells = <0>;
 282                         riscv,ndev = <136>;
 283                 };
 284
 285                 ccache: cache-controller@2010000 {
 286                         compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
 287                         reg = <0x0 0x2010000 0x0 0x4000>;
 288                         interrupts = <1>, <3>, <4>, <2>;
 289                         cache-block-size = <64>;
 290                         cache-level = <2>;
 291                         cache-sets = <2048>;
 292                         cache-size = <2097152>;
 293                         cache-unified;
 294                 };
 295
 296                 pmu: pmu@17030000 {
 297                         compatible = "starfive,jh7110-pmu";
 298                         reg = <0x0 0x17030000 0x0 0x10000>;
 299                         interrupts = <111>;
 300                         status = "okay";
 301                 };
 302
 303                 uart0: serial@10000000 {
 304                         compatible = "snps,dw-apb-uart";
 305                         reg = <0x0 0x10000000 0x0 0x10000>;
 306                         clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
 307                                  <&syscrg JH7110_SYSCLK_UART0_APB>;
 308                         clock-names = "baudclk", "apb_pclk";
 309                         resets = <&syscrg JH7110_SYSRST_UART0_APB>,
 310                                  <&syscrg JH7110_SYSRST_UART0_CORE>;
 311                         interrupts = <32>;
 312                         reg-io-width = <4>;
 313                         reg-shift = <2>;
 314                         status = "disabled";
 315                 };
 316
 317                 uart1: serial@10010000 {
 318                         compatible = "snps,dw-apb-uart";
 319                         reg = <0x0 0x10010000 0x0 0x10000>;
 320                         clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
 321                                  <&syscrg JH7110_SYSCLK_UART1_APB>;
 322                         clock-names = "baudclk", "apb_pclk";
 323                         resets = <&syscrg JH7110_SYSRST_UART1_APB>,
 324                                  <&syscrg JH7110_SYSRST_UART1_CORE>;
 325                         interrupts = <33>;
 326                         reg-io-width = <4>;
 327                         reg-shift = <2>;
 328                         status = "disabled";
 329                 };
 330
 331                 uart2: serial@10020000 {
 332                         compatible = "snps,dw-apb-uart";
 333                         reg = <0x0 0x10020000 0x0 0x10000>;
 334                         clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
 335                                  <&syscrg JH7110_SYSCLK_UART2_APB>;
 336                         clock-names = "baudclk", "apb_pclk";
 337                         resets = <&syscrg JH7110_SYSRST_UART2_APB>,
 338                                  <&syscrg JH7110_SYSRST_UART2_CORE>;
 339                         interrupts = <34>;
 340                         reg-io-width = <4>;
 341                         reg-shift = <2>;
 342                         status = "disabled";
 343                 };
 344
 345                 i2c0: i2c@10030000 {
 346                         compatible = "snps,designware-i2c";
 347                         reg = <0x0 0x10030000 0x0 0x10000>;
 348                         clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
 349                         clock-names = "ref";
 350                         resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
 351                         interrupts = <35>;
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                         status = "disabled";
 355                 };
 356
 357                 i2c1: i2c@10040000 {
 358                         compatible = "snps,designware-i2c";
 359                         reg = <0x0 0x10040000 0x0 0x10000>;
 360                         clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
 361                         clock-names = "ref";
 362                         resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
 363                         interrupts = <36>;
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         status = "disabled";
 367                 };
 368
 369                 i2c2: i2c@10050000 {
 370                         compatible = "snps,designware-i2c";
 371                         reg = <0x0 0x10050000 0x0 0x10000>;
 372                         clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
 373                         clock-names = "ref";
 374                         resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
 375                         interrupts = <37>;
 376                         #address-cells = <1>;
 377                         #size-cells = <0>;
 378                         status = "disabled";
 379                 };
 380
 381                 stgcrg: clock-controller@10230000 {
 382                         compatible = "starfive,jh7110-stgcrg";
 383                         reg = <0x0 0x10230000 0x0 0x10000>;
 384                         #clock-cells = <1>;
 385                         #reset-cells = <1>;
 386                 };
 387
 388                 stg_syscon: stg_syscon@10240000 {
 389                         compatible = "starfive,jh7110-stg-syscon","syscon";
 390                         reg = <0x0 0x10240000 0x0 0x1000>;
 391                 };
 392
 393                 uart3: serial@12000000 {
 394                         compatible = "snps,dw-apb-uart";
 395                         reg = <0x0 0x12000000 0x0 0x10000>;
 396                         clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
 397                                  <&syscrg JH7110_SYSCLK_UART3_APB>;
 398                         clock-names = "baudclk", "apb_pclk";
 399                         resets = <&syscrg JH7110_SYSRST_UART3_APB>,
 400                                  <&syscrg JH7110_SYSRST_UART3_CORE>;
 401                         interrupts = <45>;
 402                         reg-io-width = <4>;
 403                         reg-shift = <2>;
 404                         status = "disabled";
 405                 };
 406
 407                 uart4: serial@12010000 {
 408                         compatible = "snps,dw-apb-uart";
 409                         reg = <0x0 0x12010000 0x0 0x10000>;
 410                         clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
 411                                  <&syscrg JH7110_SYSCLK_UART4_APB>;
 412                         clock-names = "baudclk", "apb_pclk";
 413                         resets = <&syscrg JH7110_SYSRST_UART4_APB>,
 414                                  <&syscrg JH7110_SYSRST_UART4_CORE>;
 415                         interrupts = <46>;
 416                         reg-io-width = <4>;
 417                         reg-shift = <2>;
 418                         status = "disabled";
 419                 };
 420
 421                 uart5: serial@12020000 {
 422                         compatible = "snps,dw-apb-uart";
 423                         reg = <0x0 0x12020000 0x0 0x10000>;
 424                         clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
 425                                  <&syscrg JH7110_SYSCLK_UART5_APB>;
 426                         clock-names = "baudclk", "apb_pclk";
 427                         resets = <&syscrg JH7110_SYSRST_UART5_APB>,
 428                                  <&syscrg JH7110_SYSRST_UART5_CORE>;
 429                         interrupts = <47>;
 430                         reg-io-width = <4>;
 431                         reg-shift = <2>;
 432                         status = "disabled";
 433                 };
 434
 435                 i2c3: i2c@12030000 {
 436                         compatible = "snps,designware-i2c";
 437                         reg = <0x0 0x12030000 0x0 0x10000>;
 438                         clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
 439                         clock-names = "ref";
 440                         resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
 441                         interrupts = <48>;
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         status = "disabled";
 445                 };
 446
 447                 i2c4: i2c@12040000 {
 448                         compatible = "snps,designware-i2c";
 449                         reg = <0x0 0x12040000 0x0 0x10000>;
 450                         clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
 451                         clock-names = "ref";
 452                         resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
 453                         interrupts = <49>;
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                         status = "disabled";
 457                 };
 458
 459                 i2c5: i2c@12050000 {
 460                         compatible = "snps,designware-i2c";
 461                         reg = <0x0 0x12050000 0x0 0x10000>;
 462                         clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
 463                         clock-names = "ref";
 464                         resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
 465                         interrupts = <50>;
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         status = "disabled";
 469                 };
 470
 471                 i2c6: i2c@12060000 {
 472                         compatible = "snps,designware-i2c";
 473                         reg = <0x0 0x12060000 0x0 0x10000>;
 474                         clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
 475                         clock-names = "ref";
 476                         resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
 477                         interrupts = <51>;
 478                         #address-cells = <1>;
 479                         #size-cells = <0>;
 480                         status = "disabled";
 481                 };
 482
 483                 qspi: spi@13010000 {
 484                         compatible = "cdns,qspi-nor";
 485                         reg = <0x0 0x13010000 0x0 0x10000
 486                                 0x0 0x21000000 0x0 0x400000>;
 487                         clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
 488                         clock-names = "clk_ref";
 489                         resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
 490                                  <&syscrg JH7110_SYSRST_QSPI_AHB>,
 491                                  <&syscrg JH7110_SYSRST_QSPI_REF>;
 492                         reset-names = "rst_apb", "rst_ahb", "rst_ref";
 493                         cdns,fifo-depth = <256>;
 494                         cdns,fifo-width = <4>;
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497                 };
 498
 499                 syscrg: clock-controller@13020000 {
 500                         compatible = "starfive,jh7110-syscrg";
 501                         reg = <0x0 0x13020000 0x0 0x10000>;
 502                         clocks = <&osc>, <&gmac1_rmii_refin>,
 503                                  <&gmac1_rgmii_rxin>,
 504                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 505                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 506                                  <&tdm_ext>, <&mclk_ext>,
 507                                  <&pllclk JH7110_SYSCLK_PLL0_OUT>,
 508                                  <&pllclk JH7110_SYSCLK_PLL1_OUT>,
 509                                  <&pllclk JH7110_SYSCLK_PLL2_OUT>;
 510                         clock-names = "osc", "gmac1_rmii_refin",
 511                                       "gmac1_rgmii_rxin",
 512                                       "i2stx_bclk_ext", "i2stx_lrck_ext",
 513                                       "i2srx_bclk_ext", "i2srx_lrck_ext",
 514                                       "tdm_ext", "mclk_ext",
 515                                       "pll0_out", "pll1_out", "pll2_out";
 516                         #clock-cells = <1>;
 517                         #reset-cells = <1>;
 518                 };
 519
 520                 sys_syscon: sys_syscon@13030000 {
 521                         compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd";
 522                         reg = <0x0 0x13030000 0x0 0x1000>;
 523
 524                         pllclk: clock-controller {
 525                                 compatible = "starfive,jh7110-pll";
 526                                 clocks = <&osc>;
 527                                 #clock-cells = <1>;
 528                         };
 529                 };
 530
 531                 sysgpio: pinctrl@13040000 {
 532                         compatible = "starfive,jh7110-sys-pinctrl";
 533                         reg = <0x0 0x13040000 0x0 0x10000>;
 534                         clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
 535                         resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
 536                         interrupts = <86>;
 537                         interrupt-controller;
 538                         #interrupt-cells = <2>;
 539                         gpio-controller;
 540                         #gpio-cells = <2>;
 541                 };
 542
 543                 mmc0: mmc@16010000 {
 544                         compatible = "starfive,jh7110-mmc";
 545                         reg = <0x0 0x16010000 0x0 0x10000>;
 546                         clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
 547                                  <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
 548                         clock-names = "biu", "ciu";
 549                         resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
 550                         reset-names = "reset";
 551                         interrupts = <74>;
 552                         fifo-depth = <32>;
 553                         fifo-watermark-aligned;
 554                         data-addr = <0>;
 555                         starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
 556                         status = "disabled";
 557                 };
 558
 559                 mmc1: mmc@16020000 {
 560                         compatible = "starfive,jh7110-mmc";
 561                         reg = <0x0 0x16020000 0x0 0x10000>;
 562                         clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
 563                                  <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
 564                         clock-names = "biu", "ciu";
 565                         resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
 566                         reset-names = "reset";
 567                         interrupts = <75>;
 568                         fifo-depth = <32>;
 569                         fifo-watermark-aligned;
 570                         data-addr = <0>;
 571                         starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
 572                         status = "disabled";
 573                 };
 574
 575                 gmac0: ethernet@16030000 {
 576                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
 577                         reg = <0x0 0x16030000 0x0 0x10000>;
 578                         clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
 579                                  <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
 580                                  <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
 581                                  <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
 582                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
 583                         clock-names = "stmmaceth", "pclk", "ptp_ref",
 584                                       "tx", "gtx";
 585                         resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
 586                                  <&aoncrg JH7110_AONRST_GMAC0_AHB>;
 587                         reset-names = "stmmaceth", "ahb";
 588                         interrupts = <7>, <6>, <5>;
 589                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 590                         snps,multicast-filter-bins = <64>;
 591                         snps,perfect-filter-entries = <8>;
 592                         rx-fifo-depth = <2048>;
 593                         tx-fifo-depth = <2048>;
 594                         snps,fixed-burst;
 595                         snps,no-pbl-x8;
 596                         snps,force_thresh_dma_mode;
 597                         snps,axi-config = <&stmmac_axi_setup>;
 598                         snps,tso;
 599                         snps,en-tx-lpi-clockgating;
 600                         snps,txpbl = <16>;
 601                         snps,rxpbl = <16>;
 602                         starfive,syscon = <&aon_syscon 0xc 0x12>;
 603                         status = "disabled";
 604                 };
 605
 606                 gmac1: ethernet@16040000 {
 607                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
 608                         reg = <0x0 0x16040000 0x0 0x10000>;
 609                         clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
 610                                  <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
 611                                  <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
 612                                  <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
 613                                  <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
 614                         clock-names = "stmmaceth", "pclk", "ptp_ref",
 615                                       "tx", "gtx";
 616                         resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
 617                                  <&syscrg JH7110_SYSRST_GMAC1_AHB>;
 618                         reset-names = "stmmaceth", "ahb";
 619                         interrupts = <78>, <77>, <76>;
 620                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 621                         snps,multicast-filter-bins = <64>;
 622                         snps,perfect-filter-entries = <8>;
 623                         rx-fifo-depth = <2048>;
 624                         tx-fifo-depth = <2048>;
 625                         snps,fixed-burst;
 626                         snps,no-pbl-x8;
 627                         snps,force_thresh_dma_mode;
 628                         snps,axi-config = <&stmmac_axi_setup>;
 629                         snps,tso;
 630                         snps,en-tx-lpi-clockgating;
 631                         snps,txpbl = <16>;
 632                         snps,rxpbl = <16>;
 633                         starfive,syscon = <&sys_syscon 0x90 0x2>;
 634                         status = "disabled";
 635                 };
 636
 637                 aoncrg: clock-controller@17000000 {
 638                         compatible = "starfive,jh7110-aoncrg";
 639                         reg = <0x0 0x17000000 0x0 0x10000>;
 640                         clocks = <&osc>, <&rtc_osc>,
 641                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
 642                                  <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 643                                  <&syscrg JH7110_SYSCLK_APB_BUS>,
 644                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
 645                         clock-names = "osc", "rtc_osc", "gmac0_rmii_refin",
 646                                       "gmac0_rgmii_rxin", "stg_axiahb",
 647                                       "apb_bus", "gmac0_gtxclk";
 648                         #clock-cells = <1>;
 649                         #reset-cells = <1>;
 650                 };
 651
 652                 aon_syscon: aon_syscon@17010000 {
 653                         compatible = "starfive,jh7110-aon-syscon","syscon";
 654                         reg = <0x0 0x17010000 0x0 0x1000>;
 655                 };
 656
 657                 aongpio: pinctrl@17020000 {
 658                         compatible = "starfive,jh7110-aon-pinctrl";
 659                         reg = <0x0 0x17020000 0x0 0x10000>;
 660                         resets = <&aoncrg JH7110_AONRST_IOMUX>;
 661                         interrupts = <85>;
 662                         interrupt-controller;
 663                         #interrupt-cells = <2>;
 664                         gpio-controller;
 665                         #gpio-cells = <2>;
 666                 };
 667
 668                 pcie0: pcie@2b000000 {
 669                         compatible = "starfive,jh7110-pcie";
 670                         reg = <0x0 0x2b000000 0x0 0x1000000
 671                                0x9 0x40000000 0x0 0x10000000>;
 672                         reg-names = "reg", "config";
 673                         #address-cells = <3>;
 674                         #size-cells = <2>;
 675                         #interrupt-cells = <1>;
 676                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
 677                                  <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
 678                         interrupts = <56>;
 679                         interrupt-parent = <&plic>;
 680                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 681                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
 682                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
 683                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
 684                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
 685                         msi-parent = <&plic>;
 686                         device_type = "pci";
 687                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
 688                         bus-range = <0x0 0xff>;
 689                         clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
 690                                  <&stgcrg JH7110_STGCLK_PCIE0_TL>,
 691                                  <&stgcrg JH7110_STGCLK_PCIE0_AXI>,
 692                                  <&stgcrg JH7110_STGCLK_PCIE0_APB>;
 693                         clock-names = "noc", "tl", "axi", "apb";
 694                         resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
 695                                  <&stgcrg JH7110_STGRST_PCIE0_SLV0>,
 696                                  <&stgcrg JH7110_STGRST_PCIE0_SLV>,
 697                                  <&stgcrg JH7110_STGRST_PCIE0_BRG>,
 698                                  <&stgcrg JH7110_STGRST_PCIE0_CORE>,
 699                                  <&stgcrg JH7110_STGRST_PCIE0_APB>;
 700                         reset-names = "mst0", "slv0", "slv", "brg",
 701                                       "core", "apb";
 702                         status = "disabled";
 703                 };
 704
 705                 pcie1: pcie@2c000000 {
 706                         compatible = "starfive,jh7110-pcie";
 707                         reg = <0x0 0x2c000000 0x0 0x1000000
 708                                0x9 0xc0000000 0x0 0x10000000>;
 709                         reg-names = "reg", "config";
 710                         #address-cells = <3>;
 711                         #size-cells = <2>;
 712                         #interrupt-cells = <1>;
 713                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
 714                                  <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
 715                         interrupts = <57>;
 716                         interrupt-parent = <&plic>;
 717                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 718                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
 719                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
 720                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
 721                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
 722                         msi-parent = <&plic>;
 723                         device_type = "pci";
 724                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
 725                         bus-range = <0x0 0xff>;
 726                         clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
 727                                  <&stgcrg JH7110_STGCLK_PCIE1_TL>,
 728                                  <&stgcrg JH7110_STGCLK_PCIE1_AXI>,
 729                                  <&stgcrg JH7110_STGCLK_PCIE1_APB>;
 730                         clock-names = "noc", "tl", "axi", "apb";
 731                         resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
 732                                  <&stgcrg JH7110_STGRST_PCIE1_SLV0>,
 733                                  <&stgcrg JH7110_STGRST_PCIE1_SLV>,
 734                                  <&stgcrg JH7110_STGRST_PCIE1_BRG>,
 735                                  <&stgcrg JH7110_STGRST_PCIE1_CORE>,
 736                                  <&stgcrg JH7110_STGRST_PCIE1_APB>;
 737                         reset-names = "mst0", "slv0", "slv", "brg",
 738                                       "core", "apb";
 739                         status = "disabled";
 740                 };
 741         };
 742 };