arch/riscv/dts/jh7110-u-boot.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  */
   5
   6 #include <dt-bindings/reset/starfive,jh7110-crg.h>
   7
   8 / {
   9         cpus: cpus {
  10                 u-boot,dm-spl;
  11
  12                 S7_0: cpu@0 {
  13                         u-boot,dm-spl;
  14                         status = "okay";
  15                         cpu0_intc: interrupt-controller {
  16                                 u-boot,dm-spl;
  17                         };
  18                 };
  19
  20                 U74_1: cpu@1 {
  21                         u-boot,dm-spl;
  22                         cpu1_intc: interrupt-controller {
  23                                 u-boot,dm-spl;
  24                         };
  25                 };
  26
  27                 U74_2: cpu@2 {
  28                         u-boot,dm-spl;
  29                         cpu2_intc: interrupt-controller {
  30                                 u-boot,dm-spl;
  31                         };
  32                 };
  33
  34                 U74_3: cpu@3 {
  35                         u-boot,dm-spl;
  36                         cpu3_intc: interrupt-controller {
  37                                 u-boot,dm-spl;
  38                         };
  39                 };
  40
  41                 U74_4: cpu@4 {
  42                         u-boot,dm-spl;
  43                         cpu4_intc: interrupt-controller {
  44                                 u-boot,dm-spl;
  45                         };
  46                 };
  47         };
  48
  49         soc {
  50                 u-boot,dm-spl;
  51
  52                 clint: timer@2000000 {
  53                         u-boot,dm-spl;
  54                 };
  55
  56                 dmc: dmc@15700000 {
  57                         u-boot,dm-spl;
  58                         compatible = "starfive,jh7110-dmc";
  59                         reg = <0x0 0x15700000 0x0 0x10000>,
  60                                 <0x0 0x13000000 0x0 0x10000>;
  61                         resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
  62                                 <&syscrg JH7110_SYSRST_DDR_OSC>,
  63                                 <&syscrg JH7110_SYSRST_DDR_APB>;
  64                         reset-names = "axi", "osc", "apb";
  65                         clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>;
  66                         clock-names = "pll1_out";
  67                         clock-frequency = <2133>;
  68                 };
  69         };
  70 };
  71
  72 &osc {
  73         u-boot,dm-spl;
  74 };
  75
  76 &gmac0_rmii_refin {
  77         u-boot,dm-spl;
  78 };
  79
  80 &aoncrg {
  81         u-boot,dm-spl;
  82 };
  83
  84 &syscrg {
  85         u-boot,dm-spl;
  86         starfive,sys-syscon = <&sys_syscon>;
  87 };
  88
  89 &stgcrg {
  90         u-boot,dm-spl;
  91 };
  92
  93 &sys_syscon {
  94         u-boot,dm-spl;
  95 };
  96
  97 &S7_0 {
  98         status = "okay";
  99 };