1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
6 #ifndef _ASM_MPC85xx_CONFIG_H_
7 #define _ASM_MPC85xx_CONFIG_H_
9 /* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
12 * This macro should be removed when we no longer care about backwards
13 * compatibility with older operating systems.
15 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
17 #include <fsl_ddrc_version.h>
19 #if defined(CONFIG_ARCH_MPC8548)
20 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
21 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
22 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
23 #define CONFIG_SYS_FSL_RMU
24 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
26 #elif defined(CONFIG_ARCH_P1010)
27 #define CONFIG_FSL_SDHC_V2_3
29 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
30 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
31 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
32 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
34 /* P1011 is single core version of P1020 */
35 #elif defined(CONFIG_ARCH_P1011)
38 #elif defined(CONFIG_ARCH_P1020)
41 #elif defined(CONFIG_ARCH_P1021)
43 #define QE_MURAM_SIZE 0x6000UL
45 #define QE_NUM_OF_SNUM 28
47 #elif defined(CONFIG_ARCH_P1023)
48 #define CONFIG_SYS_NUM_FMAN 1
49 #define CONFIG_SYS_NUM_FM1_DTSEC 2
50 #define CONFIG_SYS_QMAN_NUM_PORTALS 3
51 #define CONFIG_SYS_BMAN_NUM_PORTALS 3
52 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000
53 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
55 /* P1024 is lower end variant of P1020 */
56 #elif defined(CONFIG_ARCH_P1024)
59 /* P1025 is lower end variant of P1021 */
60 #elif defined(CONFIG_ARCH_P1025)
62 #define QE_MURAM_SIZE 0x6000UL
64 #define QE_NUM_OF_SNUM 28
66 #elif defined(CONFIG_ARCH_P2020)
67 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
68 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
69 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
70 #define CONFIG_SYS_FSL_RMU
71 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
73 #elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
74 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
75 #define CONFIG_SYS_NUM_FMAN 1
76 #define CONFIG_SYS_NUM_FM1_DTSEC 5
77 #define CONFIG_SYS_NUM_FM1_10GEC 1
78 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
79 #define CONFIG_SYS_FSL_TBCLK_DIV 32
80 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
81 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
82 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
83 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
84 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
85 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
86 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
87 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
89 #elif defined(CONFIG_ARCH_P3041)
90 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
91 #define CONFIG_SYS_NUM_FMAN 1
92 #define CONFIG_SYS_NUM_FM1_DTSEC 5
93 #define CONFIG_SYS_NUM_FM1_10GEC 1
94 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
95 #define CONFIG_SYS_FSL_TBCLK_DIV 32
96 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
97 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
98 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
99 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
100 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
101 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
102 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
103 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
105 #elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
106 #define CONFIG_SYS_FSL_NUM_CC_PLLS 4
107 #define CONFIG_SYS_NUM_FMAN 2
108 #define CONFIG_SYS_NUM_FM1_DTSEC 4
109 #define CONFIG_SYS_NUM_FM2_DTSEC 4
110 #define CONFIG_SYS_NUM_FM1_10GEC 1
111 #define CONFIG_SYS_NUM_FM2_10GEC 1
112 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
113 #define CONFIG_SYS_FSL_TBCLK_DIV 16
114 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
115 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
116 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
117 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
118 #define CONFIG_SYS_FSL_RMU
119 #define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
120 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
122 #elif defined(CONFIG_ARCH_P5040)
123 #define CONFIG_SYS_FSL_NUM_CC_PLLS 3
124 #define CONFIG_SYS_NUM_FMAN 2
125 #define CONFIG_SYS_NUM_FM1_DTSEC 5
126 #define CONFIG_SYS_NUM_FM1_10GEC 1
127 #define CONFIG_SYS_NUM_FM2_DTSEC 5
128 #define CONFIG_SYS_NUM_FM2_10GEC 1
129 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
130 #define CONFIG_SYS_FSL_TBCLK_DIV 16
131 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
132 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
133 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
134 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
135 #define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
137 #elif defined(CONFIG_ARCH_BSC9131)
138 #define CONFIG_FSL_SDHC_V2_3
139 #define CONFIG_TSECV2
140 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
141 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
142 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
144 #elif defined(CONFIG_ARCH_BSC9132)
145 #define CONFIG_FSL_SDHC_V2_3
146 #define CONFIG_TSECV2
147 #define CONFIG_SYS_FSL_DSP_DDR_ADDR 0x40000000
148 #define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
149 #define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
150 #define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
151 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
152 #define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
153 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
155 #elif defined(CONFIG_ARCH_T4240)
156 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
157 #ifdef CONFIG_ARCH_T4240
158 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
159 #define CONFIG_SYS_NUM_FM1_DTSEC 8
160 #define CONFIG_SYS_NUM_FM1_10GEC 2
161 #define CONFIG_SYS_NUM_FM2_DTSEC 8
162 #define CONFIG_SYS_NUM_FM2_10GEC 2
164 #define CONFIG_SYS_NUM_FM1_DTSEC 6
165 #define CONFIG_SYS_NUM_FM1_10GEC 1
166 #define CONFIG_SYS_NUM_FM2_DTSEC 8
167 #define CONFIG_SYS_NUM_FM2_10GEC 1
169 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
170 #define CONFIG_SYS_FSL_SRDS_1
171 #define CONFIG_SYS_FSL_SRDS_2
172 #define CONFIG_SYS_FSL_SRDS_3
173 #define CONFIG_SYS_FSL_SRDS_4
174 #define CONFIG_SYS_NUM_FMAN 2
175 #define CONFIG_SYS_PME_CLK 0
176 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
177 #define CONFIG_SYS_FM1_CLK 3
178 #define CONFIG_SYS_FM2_CLK 3
179 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
180 #define CONFIG_SYS_FSL_TBCLK_DIV 16
181 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
182 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
183 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
184 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
185 #define CONFIG_SYS_FSL_SRIO_LIODN
186 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
187 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
189 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
190 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
191 #define CONFIG_SYS_FSL_SRDS_1
192 #define CONFIG_SYS_FSL_SRDS_2
193 #define CONFIG_SYS_FSL_NUM_CC_PLLS 5
194 #define CONFIG_SYS_NUM_FMAN 1
195 #define CONFIG_SYS_FM1_CLK 0
196 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
197 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
198 #define CONFIG_SYS_FSL_TBCLK_DIV 16
199 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
200 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE
202 #ifdef CONFIG_ARCH_B4860
203 #define CONFIG_MAX_DSP_CPUS 12
204 #define CONFIG_NUM_DSP_CPUS 6
205 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
206 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
207 #define CONFIG_SYS_NUM_FM1_DTSEC 6
208 #define CONFIG_SYS_NUM_FM1_10GEC 2
209 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
210 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
211 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
212 #define CONFIG_SYS_FSL_SRIO_LIODN
214 #define CONFIG_MAX_DSP_CPUS 2
215 #define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
216 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
217 #define CONFIG_SYS_NUM_FM1_DTSEC 4
218 #define CONFIG_SYS_NUM_FM1_10GEC 0
221 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
222 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
223 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
224 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
225 #define CONFIG_SYS_FSL_SRDS_1
226 #define CONFIG_SYS_NUM_FMAN 1
227 #define CONFIG_SYS_NUM_FM1_DTSEC 5
228 #define CONFIG_PME_PLAT_CLK_DIV 2
229 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
230 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
231 #define CONFIG_FM_PLAT_CLK_DIV 1
232 #define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
233 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
234 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
235 #define CONFIG_SYS_FSL_TBCLK_DIV 16
236 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
237 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
238 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
239 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
240 #define QE_MURAM_SIZE 0x6000UL
241 #define MAX_QE_RISC 1
242 #define QE_NUM_OF_SNUM 28
244 #elif defined(CONFIG_ARCH_T1024)
245 #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
246 #define CONFIG_SYS_FSL_NUM_CC_PLL 2
247 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
248 #define CONFIG_SYS_FSL_SRDS_1
249 #define CONFIG_SYS_NUM_FMAN 1
250 #define CONFIG_SYS_NUM_FM1_DTSEC 4
251 #define CONFIG_SYS_NUM_FM1_10GEC 1
252 #define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
253 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
254 #define CONFIG_SYS_FM1_CLK 0
255 #define CONFIG_QBMAN_CLK_DIV 1
256 #define CONFIG_SYS_FM_MURAM_SIZE 0x30000
257 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
258 #define CONFIG_SYS_FSL_TBCLK_DIV 16
259 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
260 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
261 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
262 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
263 #define QE_MURAM_SIZE 0x6000UL
264 #define MAX_QE_RISC 1
265 #define QE_NUM_OF_SNUM 28
267 #elif defined(CONFIG_ARCH_T2080)
268 #define CONFIG_SYS_FSL_NUM_CC_PLLS 2
269 #define CONFIG_SYS_FSL_QMAN_V3
270 #define CONFIG_SYS_NUM_FMAN 1
271 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
272 #define CONFIG_SYS_FSL_SRDS_1
273 #if defined(CONFIG_ARCH_T2080)
274 #define CONFIG_SYS_NUM_FM1_DTSEC 8
275 #define CONFIG_SYS_NUM_FM1_10GEC 4
276 #define CONFIG_SYS_FSL_SRDS_2
277 #define CONFIG_SYS_FSL_SRIO_LIODN
278 #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
279 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
280 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
282 #define CONFIG_PME_PLAT_CLK_DIV 1
283 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
284 #define CONFIG_SYS_FM1_CLK 0
285 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
286 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000
287 #define CONFIG_SYS_FSL_TBCLK_DIV 16
288 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
289 #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
290 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
291 #define CONFIG_SYS_FSL_ISBC_VER 2
292 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
295 #elif defined(CONFIG_ARCH_C29X)
296 #define CONFIG_FSL_SDHC_V2_3
297 #define CONFIG_TSECV2_1
298 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
299 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
300 #define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
304 #if !defined(CONFIG_ARCH_C29X)
305 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
308 #endif /* _ASM_MPC85xx_CONFIG_H_ */