arch/powerpc/dts/qoriq-sec5.0-0.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
   4  *
   5  * Copyright 2012 Freescale Semiconductor Inc.
   6  */
   7
   8 crypto: crypto@300000 {
   9         compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
  10         fsl,sec-era = <5>;
  11         #address-cells = <1>;
  12         #size-cells = <1>;
  13         reg              = <0x300000 0x10000>;
  14         ranges           = <0 0x300000 0x10000>;
  15         interrupts       = <92 2 0 0>;
  16
  17         sec_jr0: jr@1000 {
  18                 compatible = "fsl,sec-v5.0-job-ring",
  19                              "fsl,sec-v4.0-job-ring";
  20                 reg = <0x1000 0x1000>;
  21                 interrupts = <88 2 0 0>;
  22         };
  23
  24         sec_jr1: jr@2000 {
  25                 compatible = "fsl,sec-v5.0-job-ring",
  26                              "fsl,sec-v4.0-job-ring";
  27                 reg = <0x2000 0x1000>;
  28                 interrupts = <89 2 0 0>;
  29         };
  30
  31         sec_jr2: jr@3000 {
  32                 compatible = "fsl,sec-v5.0-job-ring",
  33                              "fsl,sec-v4.0-job-ring";
  34                 reg = <0x3000 0x1000>;
  35                 interrupts = <90 2 0 0>;
  36         };
  37
  38         sec_jr3: jr@4000 {
  39                 compatible = "fsl,sec-v5.0-job-ring",
  40                              "fsl,sec-v4.0-job-ring";
  41                 reg = <0x4000 0x1000>;
  42                 interrupts = <91 2 0 0>;
  43         };
  44
  45         rtic@6000 {
  46                 compatible = "fsl,sec-v5.0-rtic",
  47                              "fsl,sec-v4.0-rtic";
  48                 #address-cells = <1>;
  49                 #size-cells = <1>;
  50                 reg = <0x6000 0x100>;
  51                 ranges = <0x0 0x6100 0xe00>;
  52
  53                 rtic_a: rtic-a@0 {
  54                         compatible = "fsl,sec-v5.0-rtic-memory",
  55                                      "fsl,sec-v4.0-rtic-memory";
  56                         reg = <0x00 0x20 0x100 0x80>;
  57                 };
  58
  59                 rtic_b: rtic-b@20 {
  60                         compatible = "fsl,sec-v5.0-rtic-memory",
  61                                      "fsl,sec-v4.0-rtic-memory";
  62                         reg = <0x20 0x20 0x200 0x80>;
  63                 };
  64
  65                 rtic_c: rtic-c@40 {
  66                         compatible = "fsl,sec-v5.0-rtic-memory",
  67                                      "fsl,sec-v4.0-rtic-memory";
  68                         reg = <0x40 0x20 0x300 0x80>;
  69                 };
  70
  71                 rtic_d: rtic-d@60 {
  72                         compatible = "fsl,sec-v5.0-rtic-memory",
  73                                      "fsl,sec-v4.0-rtic-memory";
  74                         reg = <0x60 0x20 0x500 0x80>;
  75                 };
  76         };
  77 };
  78
  79 sec_mon: sec_mon@314000 {
  80         compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
  81         reg = <0x314000 0x1000>;
  82         interrupts = <93 2 0 0>;
  83 };