1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Marvell International Ltd.
5 * https://spdx.org/licenses
9 #include <asm/armv8/mmu.h>
11 #include <asm/arch/board.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 #define OTX2_MEM_MAP_USED 4
17 /* +1 is end of list which needs to be empty */
18 #define OTX2_MEM_MAP_MAX (OTX2_MEM_MAP_USED + CONFIG_NR_DRAM_BANKS + 1)
20 static struct mm_region otx2_mem_map[OTX2_MEM_MAP_MAX] = {
22 .virt = 0x800000000000UL,
23 .phys = 0x800000000000UL,
24 .size = 0x40000000000UL,
25 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
28 .virt = 0x840000000000UL,
29 .phys = 0x840000000000UL,
30 .size = 0x40000000000UL,
31 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
34 .virt = 0x880000000000UL,
35 .phys = 0x880000000000UL,
36 .size = 0x40000000000UL,
37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
40 .virt = 0x8c0000000000UL,
41 .phys = 0x8c0000000000UL,
42 .size = 0x40000000000UL,
43 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
48 struct mm_region *mem_map = otx2_mem_map;
50 void mem_map_fill(void)
52 int banks = OTX2_MEM_MAP_USED;
53 u32 dram_start = CONFIG_SYS_TEXT_BASE;
55 for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
56 otx2_mem_map[banks].virt = dram_start;
57 otx2_mem_map[banks].phys = dram_start;
58 otx2_mem_map[banks].size = gd->ram_size;
59 otx2_mem_map[banks].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
65 u64 get_page_table_size(void)
70 void reset_cpu(ulong addr)