1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018 Marvell International Ltd.
5 * https://spdx.org/licenses
11 #include <asm/arch/soc.h>
13 #define MAX_LMAC_PER_BGX 4
14 #define LMAC_CNT MAX_LMAC_PER_BGX
16 #if defined(CONFIG_TARGET_OCTEONTX_81XX)
18 /** Maximum number of BGX interfaces per CPU node */
19 #define MAX_BGX_PER_NODE 3
20 #define OCTEONTX_XCV /* RGMII Interface */
22 #elif defined(CONFIG_TARGET_OCTEONTX_83XX)
24 /** Maximum number of BGX interfaces per CPU node */
25 #define MAX_BGX_PER_NODE 4
30 #define RST_BOOT 0x87E006001600ULL
32 /** Structure definitions */
35 * Register (RSL) rst_boot
37 * RST Boot Register This register is not accessible through ROM scripts;
38 * see SCR_WRITE32_S[ADDR].
45 u64 reserved_2_32 : 31;
49 u64 reserved_47_52 : 6;
58 u64 reserved_61_62 : 2;
61 struct rst_boot_cn81xx {
69 u64 reserved_26_29 : 4;
74 u64 reserved_47_54 : 8;
85 struct rst_boot_cn83xx {
98 u64 reserved_47_54 : 8;
104 u64 trusted_mode : 1;
111 extern unsigned long fdt_base_addr;
113 /** Function definitions */
114 void mem_map_fill(void);
115 int octeontx_board_has_pmp(void);
116 const char *fdt_get_board_model(void);
117 const char *fdt_get_board_serial(void);
118 const char *fdt_get_board_revision(void);
119 void fdt_parse_phy_info(void);
120 void fdt_board_get_ethaddr(int bgx, int lmac, unsigned char *eth);
121 void bgx_set_board_info(int bgx_id, int *mdio_bus, int *phy_addr,
122 bool *autoneg_dis, bool *lmac_reg, bool *lmac_enable);
123 #endif /* __BOARD_H__ */