arch/arm/cpu/armv7/omap3/sys_info.c

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *      Manikandan Pillai <mani.pillai@ti.com>
   7  *
   8  * Derived from Beagle Board and 3430 SDP code by
   9  *      Richard Woodruff <r-woodruff2@ti.com>
  10  *      Syed Mohammed Khasim <khasim@ti.com>
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 #include <common.h>
  16 #include <asm/io.h>
  17 #include <asm/arch/mem.h>       /* get mem tables */
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/bootm.h>
  20
  21 #include <i2c.h>
  22 #include <linux/compiler.h>
  23
  24 extern omap3_sysinfo sysinfo;
  25 static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  26
  27 #ifdef CONFIG_DISPLAY_CPUINFO
  28 static char *rev_s[CPU_3XX_MAX_REV] = {
  29                                 "1.0",
  30                                 "2.0",
  31                                 "2.1",
  32                                 "3.0",
  33                                 "3.1",
  34                                 "UNKNOWN",
  35                                 "UNKNOWN",
  36                                 "3.1.2"};
  37
  38 /* this is the revision table for 37xx CPUs */
  39 static char *rev_s_37xx[CPU_37XX_MAX_REV] = {
  40                                 "1.0",
  41                                 "1.1",
  42                                 "1.2"};
  43 #endif /* CONFIG_DISPLAY_CPUINFO */
  44
  45 /*****************************************************************
  46  * get_dieid(u32 *id) - read die ID
  47  *****************************************************************/
  48 void get_dieid(u32 *id)
  49 {
  50         struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
  51
  52         id[3] = readl(&id_base->die_id_0);
  53         id[2] = readl(&id_base->die_id_1);
  54         id[1] = readl(&id_base->die_id_2);
  55         id[0] = readl(&id_base->die_id_3);
  56 }
  57
  58 /*****************************************************************
  59  * dieid_num_r(void) - read and set die ID
  60  *****************************************************************/
  61 void dieid_num_r(void)
  62 {
  63         char *uid_s, die_id[34];
  64         u32 id[4];
  65
  66         memset(die_id, 0, sizeof(die_id));
  67
  68         uid_s = getenv("dieid#");
  69
  70         if (uid_s == NULL) {
  71                 get_dieid(id);
  72                 sprintf(die_id, "%08x%08x%08x%08x", id[0], id[1], id[2], id[3]);
  73                 setenv("dieid#", die_id);
  74                 uid_s = die_id;
  75         }
  76
  77         printf("Die ID #%s\n", uid_s);
  78 }
  79
  80 /******************************************
  81  * get_cpu_type(void) - extract cpu info
  82  ******************************************/
  83 u32 get_cpu_type(void)
  84 {
  85         return readl(&ctrl_base->ctrl_omap_stat);
  86 }
  87
  88 /******************************************
  89  * get_cpu_id(void) - extract cpu id
  90  * returns 0 for ES1.0, cpuid otherwise
  91  ******************************************/
  92 u32 get_cpu_id(void)
  93 {
  94         struct ctrl_id *id_base;
  95         u32 cpuid = 0;
  96
  97         /*
  98          * On ES1.0 the IDCODE register is not exposed on L4
  99          * so using CPU ID to differentiate between ES1.0 and > ES1.0.
 100          */
 101         __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r"(cpuid));
 102         if ((cpuid & 0xf) == 0x0) {
 103                 return 0;
 104         } else {
 105                 /* Decode the IDs on > ES1.0 */
 106                 id_base = (struct ctrl_id *) OMAP34XX_ID_L4_IO_BASE;
 107
 108                 cpuid = readl(&id_base->idcode);
 109         }
 110
 111         return cpuid;
 112 }
 113
 114 /******************************************
 115  * get_cpu_family(void) - extract cpu info
 116  ******************************************/
 117 u32 get_cpu_family(void)
 118 {
 119         u16 hawkeye;
 120         u32 cpu_family;
 121         u32 cpuid = get_cpu_id();
 122
 123         if (cpuid == 0)
 124                 return CPU_OMAP34XX;
 125
 126         hawkeye = (cpuid >> HAWKEYE_SHIFT) & 0xffff;
 127         switch (hawkeye) {
 128         case HAWKEYE_OMAP34XX:
 129                 cpu_family = CPU_OMAP34XX;
 130                 break;
 131         case HAWKEYE_AM35XX:
 132                 cpu_family = CPU_AM35XX;
 133                 break;
 134         case HAWKEYE_OMAP36XX:
 135                 cpu_family = CPU_OMAP36XX;
 136                 break;
 137         default:
 138                 cpu_family = CPU_OMAP34XX;
 139         }
 140
 141         return cpu_family;
 142 }
 143
 144 /******************************************
 145  * get_cpu_rev(void) - extract version info
 146  ******************************************/
 147 u32 get_cpu_rev(void)
 148 {
 149         u32 cpuid = get_cpu_id();
 150
 151         if (cpuid == 0)
 152                 return CPU_3XX_ES10;
 153         else
 154                 return (cpuid >> CPU_3XX_ID_SHIFT) & 0xf;
 155 }
 156
 157 /*****************************************************************
 158  * get_sku_id(void) - read sku_id to get info on max clock rate
 159  *****************************************************************/
 160 u32 get_sku_id(void)
 161 {
 162         struct ctrl_id *id_base = (struct ctrl_id *)OMAP34XX_ID_L4_IO_BASE;
 163         return readl(&id_base->sku_id) & SKUID_CLK_MASK;
 164 }
 165
 166 /***************************************************************************
 167  *  get_gpmc0_base() - Return current address hardware will be
 168  *     fetching from. The below effectively gives what is correct, its a bit
 169  *   mis-leading compared to the TRM.  For the most general case the mask
 170  *   needs to be also taken into account this does work in practice.
 171  *   - for u-boot we currently map:
 172  *       -- 0 to nothing,
 173  *       -- 4 to flash
 174  *       -- 8 to enent
 175  *       -- c to wifi
 176  ****************************************************************************/
 177 u32 get_gpmc0_base(void)
 178 {
 179         u32 b;
 180
 181         b = readl(&gpmc_cfg->cs[0].config7);
 182         b &= 0x1F;              /* keep base [5:0] */
 183         b = b << 24;            /* ret 0x0b000000 */
 184         return b;
 185 }
 186
 187 /*******************************************************************
 188  * get_gpmc0_width() - See if bus is in x8 or x16 (mainly for nand)
 189  *******************************************************************/
 190 u32 get_gpmc0_width(void)
 191 {
 192         return WIDTH_16BIT;
 193 }
 194
 195 /*************************************************************************
 196  * get_board_rev() - setup to pass kernel board revision information
 197  * returns:(bit[0-3] sub version, higher bit[7-4] is higher version)
 198  *************************************************************************/
 199 #ifdef CONFIG_REVISION_TAG
 200 u32 __weak get_board_rev(void)
 201 {
 202         return 0x20;
 203 }
 204 #endif
 205
 206 /********************************************************
 207  *  get_base(); get upper addr of current execution
 208  *******************************************************/
 209 static u32 get_base(void)
 210 {
 211         u32 val;
 212
 213         __asm__ __volatile__("mov %0, pc \n":"=r"(val)::"memory");
 214         val &= 0xF0000000;
 215         val >>= 28;
 216         return val;
 217 }
 218
 219 /********************************************************
 220  *  is_running_in_flash() - tell if currently running in
 221  *  FLASH.
 222  *******************************************************/
 223 u32 is_running_in_flash(void)
 224 {
 225         if (get_base() < 4)
 226                 return 1;       /* in FLASH */
 227
 228         return 0;               /* running in SRAM or SDRAM */
 229 }
 230
 231 /********************************************************
 232  *  is_running_in_sram() - tell if currently running in
 233  *  SRAM.
 234  *******************************************************/
 235 u32 is_running_in_sram(void)
 236 {
 237         if (get_base() == 4)
 238                 return 1;       /* in SRAM */
 239
 240         return 0;               /* running in FLASH or SDRAM */
 241 }
 242
 243 /********************************************************
 244  *  is_running_in_sdram() - tell if currently running in
 245  *  SDRAM.
 246  *******************************************************/
 247 u32 is_running_in_sdram(void)
 248 {
 249         if (get_base() > 4)
 250                 return 1;       /* in SDRAM */
 251
 252         return 0;               /* running in SRAM or FLASH */
 253 }
 254
 255 /***************************************************************
 256  *  get_boot_type() - Is this an XIP type device or a stream one
 257  *  bits 4-0 specify type. Bit 5 says mem/perif
 258  ***************************************************************/
 259 u32 get_boot_type(void)
 260 {
 261         return (readl(&ctrl_base->status) & SYSBOOT_MASK);
 262 }
 263
 264 /*************************************************************
 265  *  get_device_type(): tell if GP/HS/EMU/TST
 266  *************************************************************/
 267 u32 get_device_type(void)
 268 {
 269         return ((readl(&ctrl_base->status) & (DEVICE_MASK)) >> 8);
 270 }
 271
 272 #ifdef CONFIG_DISPLAY_CPUINFO
 273 /**
 274  * Print CPU information
 275  */
 276 int print_cpuinfo (void)
 277 {
 278         char *cpu_family_s, *cpu_s, *sec_s, *max_clk;
 279
 280         switch (get_cpu_family()) {
 281         case CPU_OMAP34XX:
 282                 cpu_family_s = "OMAP";
 283                 switch (get_cpu_type()) {
 284                 case OMAP3503:
 285                         cpu_s = "3503";
 286                         break;
 287                 case OMAP3515:
 288                         cpu_s = "3515";
 289                         break;
 290                 case OMAP3525:
 291                         cpu_s = "3525";
 292                         break;
 293                 case OMAP3530:
 294                         cpu_s = "3530";
 295                         break;
 296                 default:
 297                         cpu_s = "35XX";
 298                         break;
 299                 }
 300                 if ((get_cpu_rev() >= CPU_3XX_ES31) &&
 301                     (get_sku_id() == SKUID_CLK_720MHZ))
 302                         max_clk = "720 MHz";
 303                 else
 304                         max_clk = "600 MHz";
 305
 306                 break;
 307         case CPU_AM35XX:
 308                 cpu_family_s = "AM";
 309                 switch (get_cpu_type()) {
 310                 case AM3505:
 311                         cpu_s = "3505";
 312                         break;
 313                 case AM3517:
 314                         cpu_s = "3517";
 315                         break;
 316                 default:
 317                         cpu_s = "35XX";
 318                         break;
 319                 }
 320                 max_clk = "600 Mhz";
 321                 break;
 322         case CPU_OMAP36XX:
 323                 cpu_family_s = "OMAP";
 324                 switch (get_cpu_type()) {
 325                 case OMAP3730:
 326                         cpu_s = "3630/3730";
 327                         break;
 328                 default:
 329                         cpu_s = "36XX/37XX";
 330                         break;
 331                 }
 332                 max_clk = "1 Ghz";
 333                 break;
 334         default:
 335                 cpu_family_s = "OMAP";
 336                 cpu_s = "35XX";
 337                 max_clk = "600 Mhz";
 338         }
 339
 340         switch (get_device_type()) {
 341         case TST_DEVICE:
 342                 sec_s = "TST";
 343                 break;
 344         case EMU_DEVICE:
 345                 sec_s = "EMU";
 346                 break;
 347         case HS_DEVICE:
 348                 sec_s = "HS";
 349                 break;
 350         case GP_DEVICE:
 351                 sec_s = "GP";
 352                 break;
 353         default:
 354                 sec_s = "?";
 355         }
 356
 357         if (CPU_OMAP36XX == get_cpu_family())
 358                 printf("%s%s-%s ES%s, CPU-OPP2, L3-200MHz, Max CPU Clock %s\n",
 359                        cpu_family_s, cpu_s, sec_s,
 360                        rev_s_37xx[get_cpu_rev()], max_clk);
 361         else
 362                 printf("%s%s-%s ES%s, CPU-OPP2, L3-165MHz, Max CPU Clock %s\n",
 363                         cpu_family_s, cpu_s, sec_s,
 364                         rev_s[get_cpu_rev()], max_clk);
 365
 366         return 0;
 367 }
 368 #endif  /* CONFIG_DISPLAY_CPUINFO */