*/
#include "hw.h"
#include "omap.h"
+#include "sysbus.h"
/* Interrupt Handlers */
struct omap_intr_handler_bank_s {
};
struct omap_intr_handler_s {
+ SysBusDevice busdev;
qemu_irq *pins;
qemu_irq parent_intr[2];
+ MemoryRegion mmio;
+ void *iclk;
+ void *fclk;
unsigned char nbanks;
int level_only;
+ uint32_t size;
+
+ uint8_t revision;
/* state */
uint32_t new_agr[2];
int sir_intr[2];
int autoidle;
uint32_t mask;
- struct omap_intr_handler_bank_s bank[];
+ struct omap_intr_handler_bank_s bank[3];
};
-inline qemu_irq omap_inth_get_pin(struct omap_intr_handler_s *s, int n)
-{
- return s->pins[n];
-}
-
static void omap_inth_sir_update(struct omap_intr_handler_s *s, int is_fiq)
{
int i, j, sir_intr, p_intr, p, f;
bank->irqs = (bank->inputs &= ~(1 << n)) | bank->swi;
}
-static uint32_t omap_inth_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_inth_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int i, offset = addr;
}
static void omap_inth_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int i, offset = addr;
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc * const omap_inth_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_inth_read,
+static const MemoryRegionOps omap_inth_mem_ops = {
+ .read = omap_inth_read,
+ .write = omap_inth_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static CPUWriteMemoryFunc * const omap_inth_writefn[] = {
- omap_inth_write,
- omap_inth_write,
- omap_inth_write,
-};
-
-void omap_inth_reset(struct omap_intr_handler_s *s)
+static void omap_inth_reset(DeviceState *dev)
{
+ struct omap_intr_handler_s *s = FROM_SYSBUS(struct omap_intr_handler_s,
+ sysbus_from_qdev(dev));
int i;
for (i = 0; i < s->nbanks; ++i){
qemu_set_irq(s->parent_intr[1], 0);
}
-struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
- unsigned long size, unsigned char nbanks, qemu_irq **pins,
- qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk)
+static int omap_intc_init(SysBusDevice *dev)
{
- int iomemtype;
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
- qemu_mallocz(sizeof(struct omap_intr_handler_s) +
- sizeof(struct omap_intr_handler_bank_s) * nbanks);
-
- s->parent_intr[0] = parent_irq;
- s->parent_intr[1] = parent_fiq;
- s->nbanks = nbanks;
- s->pins = qemu_allocate_irqs(omap_set_intr, s, nbanks * 32);
- if (pins)
- *pins = s->pins;
+ struct omap_intr_handler_s *s;
+ s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
+ if (!s->iclk) {
+ hw_error("omap-intc: clk not connected\n");
+ }
+ s->nbanks = 1;
+ sysbus_init_irq(dev, &s->parent_intr[0]);
+ sysbus_init_irq(dev, &s->parent_intr[1]);
+ qdev_init_gpio_in(&dev->qdev, omap_set_intr, s->nbanks * 32);
+ memory_region_init_io(&s->mmio, &omap_inth_mem_ops, s,
+ "omap-intc", s->size);
+ sysbus_init_mmio(dev, &s->mmio);
+ return 0;
+}
- omap_inth_reset(s);
+static Property omap_intc_properties[] = {
+ DEFINE_PROP_UINT32("size", struct omap_intr_handler_s, size, 0x100),
+ DEFINE_PROP_PTR("clk", struct omap_intr_handler_s, iclk),
+ DEFINE_PROP_END_OF_LIST(),
+};
- iomemtype = cpu_register_io_memory(omap_inth_readfn,
- omap_inth_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, size, iomemtype);
+static void omap_intc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- return s;
+ k->init = omap_intc_init;
+ dc->reset = omap_inth_reset;
+ dc->props = omap_intc_properties;
}
-static uint32_t omap2_inth_read(void *opaque, target_phys_addr_t addr)
+static TypeInfo omap_intc_info = {
+ .name = "omap-intc",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(struct omap_intr_handler_s),
+ .class_init = omap_intc_class_init,
+};
+
+static uint64_t omap2_inth_read(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int offset = addr;
if (bank_no < s->nbanks) {
offset &= ~0x60;
bank = &s->bank[bank_no];
+ } else {
+ OMAP_BAD_REG(addr);
+ return 0;
}
}
switch (offset) {
case 0x00: /* INTC_REVISION */
- return 0x21;
+ return s->revision;
case 0x10: /* INTC_SYSCONFIG */
return (s->autoidle >> 2) & 1;
}
static void omap2_inth_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+ uint64_t value, unsigned size)
{
struct omap_intr_handler_s *s = (struct omap_intr_handler_s *) opaque;
int offset = addr;
if (bank_no < s->nbanks) {
offset &= ~0x60;
bank = &s->bank[bank_no];
+ } else {
+ OMAP_BAD_REG(addr);
+ return;
}
}
s->autoidle &= 4;
s->autoidle |= (value & 1) << 2;
if (value & 2) /* SOFTRESET */
- omap_inth_reset(s);
+ omap_inth_reset(&s->busdev.qdev);
return;
case 0x48: /* INTC_CONTROL */
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc * const omap2_inth_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap2_inth_read,
+static const MemoryRegionOps omap2_inth_mem_ops = {
+ .read = omap2_inth_read,
+ .write = omap2_inth_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
-static CPUWriteMemoryFunc * const omap2_inth_writefn[] = {
- omap2_inth_write,
- omap2_inth_write,
- omap2_inth_write,
+static int omap2_intc_init(SysBusDevice *dev)
+{
+ struct omap_intr_handler_s *s;
+ s = FROM_SYSBUS(struct omap_intr_handler_s, dev);
+ if (!s->iclk) {
+ hw_error("omap2-intc: iclk not connected\n");
+ }
+ if (!s->fclk) {
+ hw_error("omap2-intc: fclk not connected\n");
+ }
+ s->level_only = 1;
+ s->nbanks = 3;
+ sysbus_init_irq(dev, &s->parent_intr[0]);
+ sysbus_init_irq(dev, &s->parent_intr[1]);
+ qdev_init_gpio_in(&dev->qdev, omap_set_intr_noedge, s->nbanks * 32);
+ memory_region_init_io(&s->mmio, &omap2_inth_mem_ops, s,
+ "omap2-intc", 0x1000);
+ sysbus_init_mmio(dev, &s->mmio);
+ return 0;
+}
+
+static Property omap2_intc_properties[] = {
+ DEFINE_PROP_UINT8("revision", struct omap_intr_handler_s,
+ revision, 0x21),
+ DEFINE_PROP_PTR("iclk", struct omap_intr_handler_s, iclk),
+ DEFINE_PROP_PTR("fclk", struct omap_intr_handler_s, fclk),
+ DEFINE_PROP_END_OF_LIST(),
};
-struct omap_intr_handler_s *omap2_inth_init(target_phys_addr_t base,
- int size, int nbanks, qemu_irq **pins,
- qemu_irq parent_irq, qemu_irq parent_fiq,
- omap_clk fclk, omap_clk iclk)
+static void omap2_intc_class_init(ObjectClass *klass, void *data)
{
- int iomemtype;
- struct omap_intr_handler_s *s = (struct omap_intr_handler_s *)
- qemu_mallocz(sizeof(struct omap_intr_handler_s) +
- sizeof(struct omap_intr_handler_bank_s) * nbanks);
-
- s->parent_intr[0] = parent_irq;
- s->parent_intr[1] = parent_fiq;
- s->nbanks = nbanks;
- s->level_only = 1;
- s->pins = qemu_allocate_irqs(omap_set_intr_noedge, s, nbanks * 32);
- if (pins)
- *pins = s->pins;
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
- omap_inth_reset(s);
+ k->init = omap2_intc_init;
+ dc->reset = omap_inth_reset;
+ dc->props = omap2_intc_properties;
+}
- iomemtype = cpu_register_io_memory(omap2_inth_readfn,
- omap2_inth_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, size, iomemtype);
+static TypeInfo omap2_intc_info = {
+ .name = "omap2-intc",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(struct omap_intr_handler_s),
+ .class_init = omap2_intc_class_init,
+};
- return s;
+static void omap_intc_register_types(void)
+{
+ type_register_static(&omap_intc_info);
+ type_register_static(&omap2_intc_info);
}
+
+type_init(omap_intc_register_types)
projects / sdk / emulator / qemu.git / blobdiff