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(parent: e4f243b) | patch
Issue memory fence message to assure memory ordering on Ivb/Hsw
authorZhao Yakui <yakui.zhao@intel.com>
Wed, 13 Mar 2013 01:29:23 +0000 (09:29 +0800)
committerYakui Zhao <yakui.zhao@intel.com>
Wed, 13 Mar 2013 01:29:23 +0000 (09:29 +0800)
commit9178a2893eb45724fdcdbc7adfe11aa7dbde39cf
tree4f06ed50f103722e021ad86168346077918dfbf9tree | snapshot
parente4f243b6ed58d832f1ca6ecf1ec15f72dd3e6ef6commit | diff
Issue memory fence message to assure memory ordering on Ivb/Hsw

Otherwise the data inconsistency between different GPU threads
is observed although the GPU threads are spawned by using hardware
scoreboard. Then it causes that avcenc encoding gets the different
results.

Reported-by: Xiang Haihao <haihao.xiang@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
src/shaders/vme/inter_bframe_haswell.asm diff | blob | history
src/shaders/vme/inter_bframe_haswell.g75b diff | blob | history
src/shaders/vme/inter_bframe_ivb.asm diff | blob | history
src/shaders/vme/inter_bframe_ivb.g7b diff | blob | history
src/shaders/vme/inter_frame_haswell.asm diff | blob | history
src/shaders/vme/inter_frame_haswell.g75b diff | blob | history
src/shaders/vme/inter_frame_ivb.asm diff | blob | history
src/shaders/vme/inter_frame_ivb.g7b diff | blob | history
src/shaders/vme/mpeg2_inter_frame_haswell.g75b diff | blob | history
src/shaders/vme/vme7.inc diff | blob | history
src/shaders/vme/vme75.inc diff | blob | history
Domain: Multimedia / Uncategorized;