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(parent: d02343e) | patch
i965: Add chipset limits for Haswell GT1/GT2.
authorKenneth Graunke <kenneth@whitecape.org>
Sat, 13 Aug 2011 01:27:16 +0000 (18:27 -0700)
committerKenneth Graunke <kenneth@whitecape.org>
Wed, 30 Jan 2013 17:46:00 +0000 (09:46 -0800)
commit871da78263673cf123e28b3c0aa88b48745ac93d
tree1ea78bb2134b271c26167064de8b4b797fd64253tree | snapshot
parentd02343e5016a5795451af3e0315b658b39463a30commit | diff
i965: Add chipset limits for Haswell GT1/GT2.

The maximum number of URB entries come from the 3DSTATE_URB_VS and
3DSTATE_URB_GS state packet documentation; the thread count information
comes from the 3DSTATE_VS and 3DSTATE_PS state packet documentation.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
(cherry picked from commit 9add4e803877f97ad7f6d479d81d537426f09b6f)
src/mesa/drivers/dri/i965/brw_context.c diff | blob | history
Domain: Graphics System / GL;