radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI
authorMarek Olšák <maraeo@gmail.com>
Sun, 30 Sep 2012 17:20:04 +0000 (19:20 +0200)
committerMarek Olšák <maraeo@gmail.com>
Sat, 6 Oct 2012 03:45:56 +0000 (05:45 +0200)
commit1aebfdc1121ccb6babb3a63dc0b99d68b4860b04
tree3f0fd6c757f1022afbab218cce2d55c97858c0cb
parent77413e77b82a5d800c86b7d3b864d6cc797721c9
radeon: fix stencil miptree allocation of combined ZS buffers on EG and SI

This allows texturing with depth-stencil buffers directly without the copy
to CB. The separate miptree description for stencil is added, because
the stencil mipmap offsets are not really depth offsets/4 (at least
for the texture units).

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
radeon/radeon_surface.c
radeon/radeon_surface.h