riscv64: Add RISC-V target

[platform/upstream/openblas.git] / getarch.c

diff --git a/getarch.c b/getarch.c
index 4af986f..7761551 100644 (file)
--- a/getarch.c
+++ b/getarch.c
@@ -132,9 +132,11 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 /* #define FORCE_PPC440FP2     */
 /* #define FORCE_CELL          */
 /* #define FORCE_SICORTEX      */
-/* #define FORCE_LOONGSON3R3   */
-/* #define FORCE_LOONGSON3R4   */
-/* #define FORCE_LOONGSON3R5   */
+/* #define FORCE_LOONGSON3R3     */
+/* #define FORCE_LOONGSON3R4     */
+/* #define FORCE_LOONGSON3R5     */
+/* #define FORCE_LOONGSON2K1000  */
+/* #define FORCE_LOONGSONGENERIC */
 /* #define FORCE_I6400         */
 /* #define FORCE_P6600         */
 /* #define FORCE_P5600         */
@@ -969,6 +971,34 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #else
 #endif
 
+#ifdef FORCE_LOONGSON2K1000
+#define FORCE
+#define ARCHITECTURE    "LOONGARCH"
+#define SUBARCHITECTURE "LOONGSON2K1000"
+#define SUBDIRNAME      "loongarch64"
+#define ARCHCONFIG   "-DLOONGSON2K1000 " \
+       "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
+       "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
+       "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
+#define LIBNAME   "loongson2k1000"
+#define CORENAME  "LOONGSON2K1000"
+#else
+#endif
+
+#ifdef FORCE_LOONGSONGENERIC
+#define FORCE
+#define ARCHITECTURE    "LOONGARCH"
+#define SUBARCHITECTURE "LOONGSONGENERIC"
+#define SUBDIRNAME      "loongarch64"
+#define ARCHCONFIG   "-DLOONGSONGENERIC " \
+       "-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
+       "-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
+       "-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
+#define LIBNAME   "loongsongeneric"
+#define CORENAME  "LOONGSONGENERIC"
+#else
+#endif
+
 #ifdef FORCE_I6400
 #define FORCE
 #define ARCHITECTURE    "MIPS"
@@ -1574,6 +1604,16 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #ifdef FORCE_C910V
 #define FORCE
 #define ARCHITECTURE    "RISCV64"
+#ifdef NO_RV64GV
+#define SUBARCHITECTURE "RISCV64_GENERIC"
+#define SUBDIRNAME      "riscv64"
+#define ARCHCONFIG   "-DRISCV64_GENERIC " \
+       "-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
+       "-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
+       "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
+#define LIBNAME   "riscv64_generic"
+#define CORENAME  "RISCV64_GENERIC"
+#else
 #define SUBARCHITECTURE "C910V"
 #define SUBDIRNAME      "riscv64"
 #define ARCHCONFIG   "-DC910V " \
@@ -1582,6 +1622,7 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
        "-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
 #define LIBNAME   "c910v"
 #define CORENAME  "C910V"
+#endif
 #else
 #endif
 
@@ -1682,17 +1723,20 @@ USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
 static int get_num_cores(void) {
 
+  int count;
 #ifdef OS_WINDOWS
   SYSTEM_INFO sysinfo;
 #elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
-  int m[2], count;
+  int m[2];
   size_t len;
 #endif
 
 #if defined(linux) || defined(__sun__)
   //returns the number of processors which are currently online
-  return sysconf(_SC_NPROCESSORS_CONF);
-
+  count = sysconf(_SC_NPROCESSORS_CONF);
+  if (count <= 0) count = 2;
+  return count;
+  
 #elif defined(OS_WINDOWS)
 
   GetSystemInfo(&sysinfo);
@@ -1703,13 +1747,15 @@ static int get_num_cores(void) {
   m[1] = HW_NCPU;
   len = sizeof(int);
   sysctl(m, 2, &count, &len, NULL, 0);
-
+  if (count <= 0) count = 2;
+  
   return count;
 
 #elif defined(AIX)
   //returns the number of processors which are currently online
-  return sysconf(_SC_NPROCESSORS_ONLN);
-
+  count = sysconf(_SC_NPROCESSORS_ONLN);
+  if (count <= 0) count = 2;
+  
 #else
   return 2;
 #endif
@@ -1731,7 +1777,7 @@ int main(int argc, char *argv[]){
 #ifdef FORCE
     printf("CORE=%s\n", CORENAME);
 #else
-#if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__)
+#if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__) || defined(__riscv)
     printf("CORE=%s\n", get_corename());
 #endif
 #endif
@@ -1879,7 +1925,7 @@ printf("ELF_VERSION=2\n");
 #ifdef FORCE
     printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
 #else
-#if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__)
+#if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc) || defined(__loongarch__) || defined(__riscv)
     printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
 #endif
 #endif