dri_bo *bo;
};
-#define PCI_CHIP_GM45_GM 0x2A42
-#define PCI_CHIP_IGD_E_G 0x2E02
-#define PCI_CHIP_Q45_G 0x2E12
-#define PCI_CHIP_G45_G 0x2E22
-#define PCI_CHIP_G41_G 0x2E32
-#define PCI_CHIP_B43_G 0x2E42
-#define PCI_CHIP_B43_G1 0x2E92
-
-#define PCI_CHIP_IRONLAKE_D_G 0x0042
-#define PCI_CHIP_IRONLAKE_M_G 0x0046
-
-#ifndef PCI_CHIP_SANDYBRIDGE_GT1
-#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* Desktop */
-#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
-#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
-#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* Mobile */
-#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
-#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
-#define PCI_CHIP_SANDYBRIDGE_S_GT 0x010A /* Server */
-#endif
-
-#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* Desktop */
-#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
-#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* Mobile */
-#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
-#define PCI_CHIP_IVYBRIDGE_S_GT1 0x015a /* Server */
-#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a
-
-#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
-#define PCI_CHIP_HASWELL_GT2 0x0412
-#define PCI_CHIP_HASWELL_GT3 0x0422
-#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
-#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_GT3 0x0426
-#define PCI_CHIP_HASWELL_S_GT1 0x040a /* Server */
-#define PCI_CHIP_HASWELL_S_GT2 0x041a
-#define PCI_CHIP_HASWELL_S_GT3 0x042a
-#define PCI_CHIP_HASWELL_B_GT1 0x040b /* Reserved */
-#define PCI_CHIP_HASWELL_B_GT2 0x041b
-#define PCI_CHIP_HASWELL_B_GT3 0x042b
-#define PCI_CHIP_HASWELL_E_GT1 0x040e /* Reserved */
-#define PCI_CHIP_HASWELL_E_GT2 0x041e
-#define PCI_CHIP_HASWELL_E_GT3 0x042e
-
-#define PCI_CHIP_HASWELL_SDV_GT1 0x0c02 /* Desktop */
-#define PCI_CHIP_HASWELL_SDV_GT2 0x0c12
-#define PCI_CHIP_HASWELL_SDV_GT3 0x0c22
-#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0c06 /* Mobile */
-#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0c16
-#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0c26
-#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0c0a /* Server */
-#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0c1a
-#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0c2a
-#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0c0b /* Reserved */
-#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0c1b
-#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0c2b
-#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0c0e /* Reserved */
-#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0c1e
-#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0c2e
-
-#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
-#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
-#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
-#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
-#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
-#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
-#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
-#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
-#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
-#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
-#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
-#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
-
-#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
-#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
-#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
-#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
-#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
-#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
-#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
-#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
-#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
-#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
-#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
-#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
-#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
-
-#define PCI_CHIP_BAYTRAIL_M_1 0x0F31
-#define PCI_CHIP_BAYTRAIL_M_2 0x0F32
-#define PCI_CHIP_BAYTRAIL_M_3 0x0F33
-#define PCI_CHIP_BAYTRAIL_M_4 0x0157
-#define PCI_CHIP_BAYTRAIL_D 0x0155
-
-#define PCI_CHIP_BROADWELL_MS_GT1 0x1602
-#define PCI_CHIP_BROADWELL_MS_GT2 0x1612
-#define PCI_CHIP_BROADWELL_MS_GT2PLUS 0x1622
-
-#define PCI_CHIP_BROADWELL_M_GT1_1 0x1606
-#define PCI_CHIP_BROADWELL_M_GT2_1 0x1616
-#define PCI_CHIP_BROADWELL_M_GT2PLUS_1 0x1626
-
-#define PCI_CHIP_BROADWELL_M_GT1_2 0x160B
-#define PCI_CHIP_BROADWELL_M_GT2_2 0x161B
-#define PCI_CHIP_BROADWELL_M_GT2PLUS_2 0x162B
-
-#define PCI_CHIP_BROADWELL_M_GT1_3 0x160E
-#define PCI_CHIP_BROADWELL_M_GT2_3 0x161E
-#define PCI_CHIP_BROADWELL_M_GT2PLUS_3 0x162E
-
-#define PCI_CHIP_BROADWELL_D_GT1_1 0x160A
-#define PCI_CHIP_BROADWELL_D_GT2_1 0x161A
-#define PCI_CHIP_BROADWELL_D_GT2PLUS_1 0x162A
-
-#define PCI_CHIP_BROADWELL_D_GT1_2 0x160D
-#define PCI_CHIP_BROADWELL_D_GT2_2 0x161D
-#define PCI_CHIP_BROADWELL_D_GT2PLUS_2 0x162D
-
-#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
- devid == PCI_CHIP_Q45_G || \
- devid == PCI_CHIP_G45_G || \
- devid == PCI_CHIP_G41_G || \
- devid == PCI_CHIP_B43_G || \
- devid == PCI_CHIP_B43_G1)
-
-#define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
-#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
-
-#define IS_IRONLAKE_D(devid) (devid == PCI_CHIP_IRONLAKE_D_G)
-#define IS_IRONLAKE_M(devid) (devid == PCI_CHIP_IRONLAKE_M_G)
-#define IS_IRONLAKE(devid) (IS_IRONLAKE_D(devid) || IS_IRONLAKE_M(devid))
-
-#define IS_SNB_GT1(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT1 || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
- devid == PCI_CHIP_SANDYBRIDGE_S_GT)
-
-#define IS_SNB_GT2(devid) (devid == PCI_CHIP_SANDYBRIDGE_GT2 || \
- devid == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
- devid == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS)
-
-#define IS_GEN6(devid) (IS_SNB_GT1(devid) || \
- IS_SNB_GT2(devid))
-
-#define IS_BAYTRAIL_M1(devid) (devid == PCI_CHIP_BAYTRAIL_M_1)
-#define IS_BAYTRAIL_M2(devid) (devid == PCI_CHIP_BAYTRAIL_M_2)
-#define IS_BAYTRAIL_M3(devid) (devid == PCI_CHIP_BAYTRAIL_M_3)
-#define IS_BAYTRAIL_D(devid) (devid == PCI_CHIP_BAYTRAIL_D)
-#define IS_BAYTRAIL(devid) (IS_BAYTRAIL_M1(devid) || \
- IS_BAYTRAIL_M2(devid) || \
- IS_BAYTRAIL_M3(devid) || \
- IS_BAYTRAIL_D(devid) )
-
-#define IS_IVB_GT1(devid) (devid == PCI_CHIP_IVYBRIDGE_GT1 || \
- devid == PCI_CHIP_IVYBRIDGE_M_GT1 || \
- devid == PCI_CHIP_IVYBRIDGE_S_GT1)
-
-#define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \
- devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \
- devid == PCI_CHIP_IVYBRIDGE_S_GT2)
-
-#define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || \
- IS_IVB_GT2(devid) || \
- IS_BAYTRAIL(devid) )
-
-#define IS_HSW_GT1(devid) (devid == PCI_CHIP_HASWELL_GT1 || \
- devid == PCI_CHIP_HASWELL_M_GT1 || \
- devid == PCI_CHIP_HASWELL_S_GT1 || \
- devid == PCI_CHIP_HASWELL_B_GT1 || \
- devid == PCI_CHIP_HASWELL_E_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_M_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_S_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_B_GT1 || \
- devid == PCI_CHIP_HASWELL_SDV_E_GT1 || \
- devid == PCI_CHIP_HASWELL_CRW_GT1 || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT1 || \
- devid == PCI_CHIP_HASWELL_CRW_S_GT1 || \
- devid == PCI_CHIP_HASWELL_CRW_B_GT1 || \
- devid == PCI_CHIP_HASWELL_CRW_E_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_M_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_S_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_B_GT1 || \
- devid == PCI_CHIP_HASWELL_ULT_E_GT1)
-
-
-#define IS_HSW_GT2(devid) (devid == PCI_CHIP_HASWELL_GT2|| \
- devid == PCI_CHIP_HASWELL_M_GT2|| \
- devid == PCI_CHIP_HASWELL_S_GT2|| \
- devid == PCI_CHIP_HASWELL_B_GT2 || \
- devid == PCI_CHIP_HASWELL_E_GT2 || \
- devid == PCI_CHIP_HASWELL_SDV_GT2|| \
- devid == PCI_CHIP_HASWELL_SDV_M_GT2|| \
- devid == PCI_CHIP_HASWELL_SDV_S_GT2|| \
- devid == PCI_CHIP_HASWELL_SDV_B_GT2 || \
- devid == PCI_CHIP_HASWELL_SDV_E_GT2 || \
- devid == PCI_CHIP_HASWELL_CRW_GT2|| \
- devid == PCI_CHIP_HASWELL_CRW_M_GT2|| \
- devid == PCI_CHIP_HASWELL_CRW_S_GT2|| \
- devid == PCI_CHIP_HASWELL_CRW_B_GT2|| \
- devid == PCI_CHIP_HASWELL_CRW_E_GT2|| \
- devid == PCI_CHIP_HASWELL_ULT_GT2|| \
- devid == PCI_CHIP_HASWELL_ULT_M_GT2|| \
- devid == PCI_CHIP_HASWELL_ULT_S_GT2|| \
- devid == PCI_CHIP_HASWELL_ULT_B_GT2 || \
- devid == PCI_CHIP_HASWELL_ULT_E_GT2)
-
-
-#define IS_HSW_GT3(devid) (devid == PCI_CHIP_HASWELL_GT3 || \
- devid == PCI_CHIP_HASWELL_M_GT3 || \
- devid == PCI_CHIP_HASWELL_S_GT3 || \
- devid == PCI_CHIP_HASWELL_B_GT3 || \
- devid == PCI_CHIP_HASWELL_E_GT3 || \
- devid == PCI_CHIP_HASWELL_SDV_GT3 || \
- devid == PCI_CHIP_HASWELL_SDV_M_GT3 || \
- devid == PCI_CHIP_HASWELL_SDV_S_GT3 || \
- devid == PCI_CHIP_HASWELL_SDV_B_GT3 || \
- devid == PCI_CHIP_HASWELL_SDV_E_GT3 || \
- devid == PCI_CHIP_HASWELL_CRW_GT3 || \
- devid == PCI_CHIP_HASWELL_CRW_M_GT3 || \
- devid == PCI_CHIP_HASWELL_CRW_S_GT3 || \
- devid == PCI_CHIP_HASWELL_CRW_B_GT3 || \
- devid == PCI_CHIP_HASWELL_CRW_E_GT3 || \
- devid == PCI_CHIP_HASWELL_ULT_GT3 || \
- devid == PCI_CHIP_HASWELL_ULT_M_GT3 || \
- devid == PCI_CHIP_HASWELL_ULT_S_GT3 || \
- devid == PCI_CHIP_HASWELL_ULT_B_GT3 || \
- devid == PCI_CHIP_HASWELL_ULT_E_GT3)
-
-#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
- IS_HSW_GT2(devid) || \
- IS_HSW_GT3(devid))
-
-#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
- IS_HASWELL(devid))
-
-
-#define IS_BDW_GT1(devid) (devid == PCI_CHIP_BROADWELL_M_GT1_1 || \
- devid == PCI_CHIP_BROADWELL_M_GT1_2 || \
- devid == PCI_CHIP_BROADWELL_M_GT1_3 || \
- devid == PCI_CHIP_BROADWELL_D_GT1_1 || \
- devid == PCI_CHIP_BROADWELL_D_GT1_2 || \
- devid == PCI_CHIP_BROADWELL_MS_GT1)
-
-#define IS_BDW_GT2(devid) (devid == PCI_CHIP_BROADWELL_M_GT2_1 || \
- devid == PCI_CHIP_BROADWELL_M_GT2_2 || \
- devid == PCI_CHIP_BROADWELL_M_GT2_3 || \
- devid == PCI_CHIP_BROADWELL_D_GT2_1 || \
- devid == PCI_CHIP_BROADWELL_D_GT2_2 || \
- devid == PCI_CHIP_BROADWELL_MS_GT2)
-
-#define IS_BDW_GT2PLUS(devid) (devid == PCI_CHIP_BROADWELL_M_GT2PLUS_1 || \
- devid == PCI_CHIP_BROADWELL_M_GT2PLUS_2 || \
- devid == PCI_CHIP_BROADWELL_M_GT2PLUS_3 || \
- devid == PCI_CHIP_BROADWELL_D_GT2PLUS_1 || \
- devid == PCI_CHIP_BROADWELL_D_GT2PLUS_2 || \
- devid == PCI_CHIP_BROADWELL_MS_GT2PLUS)
-
-#define IS_GEN8(devid) (IS_BDW_GT1(devid) || \
- IS_BDW_GT2(devid) || \
- IS_BDW_GT2PLUS(devid))
+#define IS_G4X(device_info) (device_info->is_g4x)
+
+#define IS_IRONLAKE(device_info) (device_info->gen == 5)
+
+#define IS_GEN6(device_info) (device_info->gen == 6)
+
+#define IS_HASWELL(device_info) (device_info->is_haswell)
+#define IS_GEN7(device_info) (device_info->gen == 7)
+
+#define IS_GEN8(device_info) (device_info->gen == 8)
#endif /* _INTEL_DRIVER_H_ */
projects / platform / upstream / libva-intel-driver.git / blobdiff