#define _I965_DRV_VIDEO_H_
#include <va/va.h>
+#include <va/va_enc_h264.h>
+#include <va/va_enc_mpeg2.h>
+#include <va/va_vpp.h>
#include <va/va_backend.h>
+#include <va/va_backend_vpp.h>
#include "i965_mutext.h"
#include "object_heap.h"
#include "intel_driver.h"
+#include "i965_fourcc.h"
-#define I965_MAX_PROFILES 11
+#define I965_MAX_PROFILES 20
#define I965_MAX_ENTRYPOINTS 5
#define I965_MAX_CONFIG_ATTRIBUTES 10
-#define I965_MAX_IMAGE_FORMATS 3
+#define I965_MAX_IMAGE_FORMATS 10
#define I965_MAX_SUBPIC_FORMATS 6
+#define I965_MAX_SUBPIC_SUM 4
+#define I965_MAX_SURFACE_ATTRIBUTES 16
#define INTEL_STR_DRIVER_VENDOR "Intel"
#define INTEL_STR_DRIVER_NAME "i965"
-#define I965_SURFACE_TYPE_IMAGE 0
-#define I965_SURFACE_TYPE_SURFACE 1
+#define I965_SURFACE_TYPE_IMAGE 0
+#define I965_SURFACE_TYPE_SURFACE 1
-#define I965_SURFACE_FLAG_FRAME 0x00000000
-#define I965_SURFACE_FLAG_TOP_FIELD_FIRST 0x00000001
-#define I965_SURFACE_FLAG_BOTTOM_FIELD_FIRST 0x00000002
+#define I965_SURFACE_FLAG_FRAME 0x00000000
+#define I965_SURFACE_FLAG_TOP_FIELD_FIRST 0x00000001
+#define I965_SURFACE_FLAG_BOTTOME_FIELD_FIRST 0x00000002
+
+#define DEFAULT_BRIGHTNESS 0
+#define DEFAULT_CONTRAST 50
+#define DEFAULT_HUE 0
+#define DEFAULT_SATURATION 50
struct i965_surface
{
- VAGenericID id;
+ struct object_base *base;
int type;
int flags;
};
const uint32_t (*bin)[4];
int size;
dri_bo *bo;
+ unsigned int kernel_offset;
};
struct buffer_store
#define NUM_SLICES 10
+struct codec_state_base {
+ uint32_t chroma_formats;
+};
+
struct decode_state
{
+ struct codec_state_base base;
struct buffer_store *pic_param;
struct buffer_store **slice_params;
struct buffer_store *iq_matrix;
struct buffer_store *bit_plane;
struct buffer_store *huffman_table;
struct buffer_store **slice_datas;
+ struct buffer_store *probability_data;
VASurfaceID current_render_target;
int max_slice_params;
int max_slice_datas;
int num_slice_params;
int num_slice_datas;
+
+ struct object_surface *render_object;
+ struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
};
+#define SLICE_PACKED_DATA_INDEX_TYPE 0x80000000
+#define SLICE_PACKED_DATA_INDEX_MASK 0x00FFFFFF
+
struct encode_state
{
+ struct codec_state_base base;
struct buffer_store *seq_param;
struct buffer_store *pic_param;
struct buffer_store *pic_control;
struct buffer_store *iq_matrix;
struct buffer_store *q_matrix;
struct buffer_store **slice_params;
- VASurfaceID current_render_target;
int max_slice_params;
int num_slice_params;
+
+ /* for ext */
+ struct buffer_store *seq_param_ext;
+ struct buffer_store *pic_param_ext;
+ struct buffer_store *packed_header_param[4];
+ struct buffer_store *packed_header_data[4];
+ struct buffer_store **slice_params_ext;
+ int max_slice_params_ext;
+ int num_slice_params_ext;
+
+ /* For the packed data that needs to be inserted into video clip */
+ /* currently it is mainly to track packed raw data and packed slice_header data. */
+ struct buffer_store **packed_header_params_ext;
+ int max_packed_header_params_ext;
+ int num_packed_header_params_ext;
+ struct buffer_store **packed_header_data_ext;
+ int max_packed_header_data_ext;
+ int num_packed_header_data_ext;
+
+ /* the array is determined by max_slice_params_ext */
+ int slice_num;
+ /* This is to store the first index of packed data for one slice */
+ int *slice_rawdata_index;
+ /* This is to store the number of packed data for one slice.
+ * Both packed rawdata and slice_header data are tracked by this
+ * this variable. That is to say: When one packed slice_header is parsed,
+ * this variable will also be increased.
+ */
+ int *slice_rawdata_count;
+
+ /* This is to store the index of packed slice header for one slice */
+ int *slice_header_index;
+
+ int last_packed_header_type;
+
+ struct buffer_store *misc_param[16];
+
+ VASurfaceID current_render_target;
+ struct object_surface *input_yuv_object;
+ struct object_surface *reconstructed_object;
+ struct object_buffer *coded_buf_object;
+ struct object_surface *reference_objects[16]; /* Up to 2 reference surfaces are valid for MPEG-2,*/
+};
+
+struct proc_state
+{
+ struct codec_state_base base;
+ struct buffer_store *pipeline_param;
+
+ VASurfaceID current_render_target;
};
#define CODEC_DEC 0
#define CODEC_ENC 1
+#define CODEC_PROC 2
union codec_state
{
+ struct codec_state_base base;
struct decode_state decode;
struct encode_state encode;
+ struct proc_state proc;
};
struct hw_context
{
- void (*run)(VADriverContextP ctx,
- VAProfile profile,
- union codec_state *codec_state,
- struct hw_context *hw_context);
+ VAStatus (*run)(VADriverContextP ctx,
+ VAProfile profile,
+ union codec_state *codec_state,
+ struct hw_context *hw_context);
void (*destroy)(void *);
struct intel_batchbuffer *batch;
};
{
struct object_base base;
VAContextID context_id;
- VAConfigID config_id;
+ struct object_config *obj_config;
VASurfaceID *render_targets; //input->encode, output->decode
int num_render_targets;
int picture_width;
};
#define SURFACE_REFERENCED (1 << 0)
-#define SURFACE_DISPLAYED (1 << 1)
#define SURFACE_DERIVED (1 << 2)
-#define SURFACE_REF_DIS_MASK ((SURFACE_REFERENCED) | \
- (SURFACE_DISPLAYED))
#define SURFACE_ALL_MASK ((SURFACE_REFERENCED) | \
- (SURFACE_DISPLAYED) | \
(SURFACE_DERIVED))
struct object_surface
{
struct object_base base;
VASurfaceStatus status;
- VASubpictureID subpic;
- int width;
- int height;
+ VASubpictureID subpic[I965_MAX_SUBPIC_SUM];
+ struct object_subpic *obj_subpic[I965_MAX_SUBPIC_SUM];
+ unsigned int subpic_render_idx;
+
+ int width; /* the pitch of plane 0 in bytes in horizontal direction */
+ int height; /* the pitch of plane 0 in bytes in vertical direction */
int size;
- int orig_width;
- int orig_height;
+ int orig_width; /* the width of plane 0 in pixels */
+ int orig_height; /* the height of plane 0 in pixels */
int flags;
unsigned int fourcc;
dri_bo *bo;
int cb_cr_width;
int cb_cr_height;
int cb_cr_pitch;
+ /* user specified attributes see: VASurfaceAttribExternalBuffers/VA_SURFACE_ATTRIB_MEM_TYPE_VA */
+ uint32_t user_disable_tiling : 1;
+ uint32_t user_h_stride_set : 1;
+ uint32_t user_v_stride_set : 1;
};
struct object_buffer
{
struct object_base base;
VAImageID image;
+ struct object_image *obj_image;
VARectangle src_rect;
VARectangle dst_rect;
unsigned int format;
unsigned int flags;
};
+#define I965_RING_NULL 0
+#define I965_RING_BSD 1
+#define I965_RING_BLT 2
+#define I965_RING_VEBOX 3
+
+struct i965_filter
+{
+ VAProcFilterType type;
+ int ring;
+};
+
struct hw_codec_info
{
- struct hw_context *(*dec_hw_context_init)(VADriverContextP, VAProfile);
- struct hw_context *(*enc_hw_context_init)(VADriverContextP, VAProfile);
+ struct hw_context *(*dec_hw_context_init)(VADriverContextP, struct object_config *);
+ struct hw_context *(*enc_hw_context_init)(VADriverContextP, struct object_config *);
+ struct hw_context *(*proc_hw_context_init)(VADriverContextP, struct object_config *);
+ bool (*render_init)(VADriverContextP);
+ void (*post_processing_context_init)(VADriverContextP, void *, struct intel_batchbuffer *);
+
int max_width;
int max_height;
+ int min_linear_wpitch;
+ int min_linear_hpitch;
+
+ unsigned int h264_mvc_dec_profiles;
+ unsigned int h264_dec_chroma_formats;
+ unsigned int jpeg_dec_chroma_formats;
+
+ unsigned int has_mpeg2_decoding:1;
+ unsigned int has_mpeg2_encoding:1;
+ unsigned int has_h264_decoding:1;
+ unsigned int has_h264_encoding:1;
+ unsigned int has_vc1_decoding:1;
+ unsigned int has_vc1_encoding:1;
+ unsigned int has_jpeg_decoding:1;
+ unsigned int has_jpeg_encoding:1;
+ unsigned int has_vpp:1;
+ unsigned int has_accelerated_getimage:1;
+ unsigned int has_accelerated_putimage:1;
+ unsigned int has_tiled_surface:1;
+ unsigned int has_di_motion_adptive:1;
+ unsigned int has_di_motion_compensated:1;
+ unsigned int has_vp8_decoding:1;
+ unsigned int has_vp8_encoding:1;
+ unsigned int has_h264_mvc_encoding:1;
+
+ unsigned int num_filters;
+ struct i965_filter filters[VAProcFilterCount];
};
struct object_heap buffer_heap;
struct object_heap image_heap;
struct object_heap subpic_heap;
- struct hw_codec_info *codec_info;
+ const struct hw_codec_info *codec_info;
_I965Mutex render_mutex;
+ _I965Mutex pp_mutex;
struct intel_batchbuffer *batch;
+ struct intel_batchbuffer *pp_batch;
struct i965_render_state render_state;
void *pp_context;
char va_vendor[256];
VADisplayAttribute *display_attributes;
unsigned int num_display_attributes;
VADisplayAttribute *rotation_attrib;
+ VADisplayAttribute *brightness_attrib;
+ VADisplayAttribute *contrast_attrib;
+ VADisplayAttribute *hue_attrib;
+ VADisplayAttribute *saturation_attrib;
+ VAContextID current_context_id;
/* VA/DRI (X11) specific data */
struct va_dri_output *dri_output;
return (struct i965_driver_data *)(ctx->pDriverData);
}
-void
+VAStatus
i965_check_alloc_surface_bo(VADriverContextP ctx,
struct object_surface *obj_surface,
int tiled,
unsigned int fourcc,
unsigned int subsampling);
+int
+va_enc_packed_type_to_idx(int packed_type);
+
+/* reserve 2 byte for internal using */
+#define CODEC_H264 0
+#define CODEC_MPEG2 1
+#define CODEC_H264_MVC 2
+
+#define H264_DELIMITER0 0x00
+#define H264_DELIMITER1 0x00
+#define H264_DELIMITER2 0x00
+#define H264_DELIMITER3 0x00
+#define H264_DELIMITER4 0x00
+
+#define MPEG2_DELIMITER0 0x00
+#define MPEG2_DELIMITER1 0x00
+#define MPEG2_DELIMITER2 0x00
+#define MPEG2_DELIMITER3 0x00
+#define MPEG2_DELIMITER4 0xb0
+
+struct i965_coded_buffer_segment
+{
+ VACodedBufferSegment base;
+ unsigned char mapped;
+ unsigned char codec;
+};
+
+#define I965_CODEDBUFFER_HEADER_SIZE ALIGN(sizeof(struct i965_coded_buffer_segment), 64)
extern VAStatus i965_MapBuffer(VADriverContextP ctx,
VABufferID buf_id, /* in */
extern VAStatus i965_UnmapBuffer(VADriverContextP ctx, VABufferID buf_id);
+extern VAStatus i965_DestroySurfaces(VADriverContextP ctx,
+ VASurfaceID *surface_list,
+ int num_surfaces);
+
+extern VAStatus i965_CreateSurfaces(VADriverContextP ctx,
+ int width,
+ int height,
+ int format,
+ int num_surfaces,
+ VASurfaceID *surfaces);
+
+#define I965_SURFACE_MEM_NATIVE 0
+#define I965_SURFACE_MEM_GEM_FLINK 1
+#define I965_SURFACE_MEM_DRM_PRIME 2
+
+void
+i965_destroy_surface_storage(struct object_surface *obj_surface);
+
#endif /* _I965_DRV_VIDEO_H_ */