Prepare for 64bit relocation addresses

[platform/upstream/intel-gpu-tools.git] / tests / gem_unfence_active_buffers.c

diff --git a/tests/gem_unfence_active_buffers.c b/tests/gem_unfence_active_buffers.c
index aa0e01e..2c221a2 100644 (file)
--- a/tests/gem_unfence_active_buffers.c
+++ b/tests/gem_unfence_active_buffers.c
@@ -93,11 +93,9 @@ igt_simple_main
                OUT_BATCH(0 << 16 | 1024);
                OUT_BATCH((2048) << 16 | (2048));
                OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-               BLIT_RELOC_UDW(devid);
                OUT_BATCH(0 << 16 | 0);
                OUT_BATCH(2*1024*4);
                OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-               BLIT_RELOC_UDW(devid);
                ADVANCE_BATCH();
 
                if (IS_GEN6(devid) || IS_GEN7(devid)) {
@@ -128,11 +126,9 @@ igt_simple_main
                OUT_BATCH(0 << 16 | 0);
                OUT_BATCH((1) << 16 | (1));
                OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-               BLIT_RELOC_UDW(devid);
                OUT_BATCH(0 << 16 | 0);
                OUT_BATCH(TEST_STRIDE);
                OUT_RELOC_FENCED(test_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-               BLIT_RELOC_UDW(devid);
                ADVANCE_BATCH();
                intel_batchbuffer_flush(batch);
                igt_info("test bo offset: %#lx\n", test_bo->offset);
@@ -149,11 +145,9 @@ igt_simple_main
                OUT_BATCH(0 << 16 | 1024);
                OUT_BATCH((1) << 16 | (1));
                OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
-               BLIT_RELOC_UDW(devid);
                OUT_BATCH(0 << 16 | 0);
                OUT_BATCH(2*1024*4);
                OUT_RELOC_FENCED(busy_bo, I915_GEM_DOMAIN_RENDER, 0, 0);
-               BLIT_RELOC_UDW(devid);
                ADVANCE_BATCH();
 
                if (IS_GEN6(devid) || IS_GEN7(devid)) {