Imported Upstream version 7.9
[platform/upstream/gdb.git] / opcodes / mips-opc.c
index e2c258c..0472b5b 100644 (file)
@@ -1,5 +1,5 @@
 /* mips-opc.c -- MIPS opcode list.
-   Copyright (C) 1993-2014 Free Software Foundation, Inc.
+   Copyright (C) 1993-2015 Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
@@ -40,6 +40,24 @@ decode_mips_operand (const char *p)
 {
   switch (p[0])
     {
+    case '-':
+      switch (p[1])
+       {
+       case 'a': INT_ADJ (19, 0, 262143, 2, FALSE);
+       case 'b': INT_ADJ (18, 0, 131071, 3, FALSE);
+       case 'd': SPECIAL (0, 0, REPEAT_DEST_REG);
+       case 's': SPECIAL (5, 21, NON_ZERO_REG);
+       case 't': SPECIAL (5, 16, NON_ZERO_REG);
+       case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, TRUE);
+       case 'v': PREV_CHECK (5, 16, TRUE, TRUE, FALSE, FALSE);
+       case 'w': PREV_CHECK (5, 16, FALSE, TRUE, TRUE, TRUE);
+       case 'x': PREV_CHECK (5, 21, TRUE, FALSE, FALSE, TRUE);
+       case 'y': PREV_CHECK (5, 21, FALSE, TRUE, TRUE, FALSE);
+       case 'A': PCREL (19, 0, TRUE, 2, 2, FALSE, FALSE);
+       case 'B': PCREL (18, 0, TRUE, 3, 3, FALSE, FALSE);
+       }
+      break;
+
     case '+':
       switch (p[1])
        {
@@ -61,13 +79,16 @@ decode_mips_operand (const char *p)
        case 'F': MSB (5, 11, 33, TRUE, 64);    /* (33 .. 64), 64-bit op */
        case 'G': MSB (5, 11, 33, FALSE, 64);   /* (33 .. 64), 64-bit op */
        case 'H': MSB (5, 11, 1, FALSE, 64);    /* (1 .. 32), 64-bit op */
+       case 'I': UINT (2, 6);
        case 'J': HINT (10, 11);
        case 'K': SPECIAL (4, 21, VU0_MATCH_SUFFIX);
        case 'L': SPECIAL (2, 21, VU0_SUFFIX);
        case 'M': SPECIAL (2, 23, VU0_SUFFIX);
        case 'N': SPECIAL (2, 0, VU0_MATCH_SUFFIX);
+       case 'O': UINT (3, 6);
        case 'P': BIT (5, 6, 32);               /* (32 .. 63) */
        case 'Q': SINT (10, 6);
+       case 'R': SPECIAL (0, 0, PC);
        case 'S': MSB (5, 11, 0, FALSE, 63);    /* (0 .. 31), 64-bit op */
        case 'T': INT_ADJ (10, 16, 511, 0, FALSE); /* (-512 .. 511) << 0 */
        case 'U': INT_ADJ (10, 16, 511, 1, FALSE); /* (-512 .. 511) << 1 */
@@ -113,6 +134,10 @@ decode_mips_operand (const char *p)
        case '&': SPECIAL (0, 0, IMM_INDEX);
        case '*': SPECIAL (5, 16, REG_INDEX);
        case '|': BIT (8, 16, 0);               /* (0 .. 255) */
+       case ':': SINT (11, 0);
+       case '\'': BRANCH (26, 0, 2);
+       case '"': BRANCH (21, 0, 2);
+       case ';': SPECIAL (10, 16, SAME_RS_RT);
        }
       break;
 
@@ -190,10 +215,10 @@ decode_mips_operand (const char *p)
 
 /* Short hand so the lines aren't too long.  */
 
-#define LCD    INSN_LOAD_COPROC_DELAY
+#define LC     INSN_LOAD_COPROC
 #define UBD     INSN_UNCOND_BRANCH_DELAY
 #define CBD    INSN_COND_BRANCH_DELAY
-#define COD     INSN_COPROC_MOVE_DELAY
+#define CM     INSN_COPROC_MOVE
 #define CLD    (INSN_LOAD_MEMORY|INSN_COPROC_MEMORY_DELAY)
 #define CBL    INSN_COND_BRANCH_LIKELY
 #define NODS   INSN_NO_DELAY_SLOT
@@ -241,6 +266,9 @@ decode_mips_operand (const char *p)
 #define WR_MACC INSN2_WRITE_MDMX_ACC
 #define RD_MACC INSN2_READ_MDMX_ACC
 
+#define RD_pc   INSN2_READ_PC
+#define FS      INSN2_FORBIDDEN_SLOT
+
 #define I1     INSN_ISA1
 #define I2     INSN_ISA2
 #define I3     INSN_ISA3
@@ -251,9 +279,11 @@ decode_mips_operand (const char *p)
 #define I33    INSN_ISA32R2
 #define I34    INSN_ISA32R3
 #define I36    INSN_ISA32R5
+#define I37    INSN_ISA32R6
 #define I65    INSN_ISA64R2
 #define I66    INSN_ISA64R3
 #define I68    INSN_ISA64R5
+#define I69    INSN_ISA64R6
 #define I3_32   INSN_ISA3_32
 #define I3_33   INSN_ISA3_32R2
 #define I4_32   INSN_ISA4_32
@@ -286,9 +316,10 @@ decode_mips_operand (const char *p)
 #define N5     (INSN_5400 | INSN_5500)
 #define N54    INSN_5400
 #define N55    INSN_5500
-#define IOCT   (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2)
-#define IOCTP  (INSN_OCTEONP | INSN_OCTEON2)
-#define IOCT2  INSN_OCTEON2
+#define IOCT   (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCTP  (INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCT2  (INSN_OCTEON2 | INSN_OCTEON3)
+#define IOCT3  INSN_OCTEON3
 #define XLR     INSN_XLR
 #define IVIRT  ASE_VIRT
 #define IVIRT64        ASE_VIRT64
@@ -383,9 +414,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
 /* name,               args,           match,      mask,       pinfo,                  pinfo2,         membership,     ase,    exclusions */
-{"pref",               "k,o(b)",       0xcc000000, 0xfc000000, RD_3|LM,                0,              I4_32|G3,       0,      0 },
+{"pref",               "k,+j(b)",      0x7c000035, 0xfc00007f, RD_3,                   0,              I37,            0,      0 },
+{"pref",               "k,o(b)",       0xcc000000, 0xfc000000, RD_3|LM,                0,              I4_32|G3,       0,      I37 },
 {"pref",               "k,A(b)",       0,    (int) M_PREF_AB,  INSN_MACRO,             0,              I4_32|G3,       0,      0 },
-{"prefx",              "h,t(b)",       0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S|LM,              0,              I4_33,          0,      0 },
+{"prefx",              "h,t(b)",       0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S|LM,              0,              I4_33,          0,      I37 },
 {"nop",                        "",             0x00000000, 0xffffffff, 0,                      INSN2_ALIAS,    I1,             0,      0 }, /* sll */
 {"ssnop",              "",             0x00000040, 0xffffffff, 0,                      INSN2_ALIAS,    I1,             0,      0 }, /* sll */
 {"ehb",                        "",             0x000000c0, 0xffffffff, 0,                      INSN2_ALIAS,    I1,             0,      0 }, /* sll */
@@ -398,7 +430,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"move",               "d,s",          0x00000025, 0xfc1f07ff, WR_1|RD_2,              INSN2_ALIAS,    I1,             0,      0 },/* or */
 {"b",                  "p",            0x10000000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 },/* beq 0,0 */
 {"b",                  "p",            0x04010000, 0xffff0000, UBD,                    INSN2_ALIAS,    I1,             0,      0 },/* bgez 0 */
+{"nal",                        "",             0x04100000, 0xffffffff, WR_31|CBD,              INSN2_ALIAS,    I1,             0,      0 },/* bltzal 0 */
 {"bal",                        "p",            0x04110000, 0xffff0000, WR_31|UBD,              INSN2_ALIAS,    I1,             0,      0 },/* bgezal 0*/
+{"bc",                 "+'",           0xc8000000, 0xfc000000, NODS,                   0,              I37,            0,      0 },
+{"balc",               "+'",           0xe8000000, 0xfc000000, WR_31|NODS,             0,              I37,            0,      0 },
+{"lapc",               "s,-A",         0xec000000, 0xfc180000, WR_1,                   RD_pc,          I37,            0,      0 },
+{"la",                 "t,A(b)",       0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1,             0,      0 },
 
 /* Loongson specific instructions.  Loongson 3A redefines the Coprocessor 2
    instructions.  Put them here so that disassembler will find them first.
@@ -592,26 +629,28 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"abs",                        "d,v",          0,    (int) M_ABS,      INSN_MACRO,             0,              I1,             0,      0 },
 {"abs.s",              "D,V",          0x46000005, 0xffff003f, WR_1|RD_2|FP_S,         0,              I1,             0,      0 },
 {"abs.d",              "D,V",          0x46200005, 0xffff003f, WR_1|RD_2|FP_D,         0,              I1,             0,      SF },
-{"abs.ps",             "D,V",          0x46c00005, 0xffff003f, WR_1|RD_2|FP_D,         0,              I5_33|IL2F,     0,      0 },
+{"abs.ps",             "D,V",          0x46c00005, 0xffff003f, WR_1|RD_2|FP_D,         0,              I5_33|IL2F,     0,      I37 },
 {"abs.ps",             "D,V",          0x45600005, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2E,           0,      0 },
 {"aclr",               "\\,~(b)",      0x04070000, 0xfc1f8000, RD_3|LM|SM|NODS,        0,              0,              MC,     0 },
 {"aclr",               "\\,A(b)",      0,    (int) M_ACLR_AB,  INSN_MACRO,             0,              0,              MC,     0 },
 {"add",                        "d,v,t",        0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
-{"add",                        "t,r,I",        0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1,             0,      0 },
+{"add",                        "t,r,I",        0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1,             0,      I37 },
 {"add",                        "D,S,T",        0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
 {"add",                        "D,S,T",        0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
 {"add.s",              "D,V,T",        0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"add.d",              "D,V,T",        0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
 {"add.ob",             "X,Y,Q",        0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"add.ob",             "D,S,Q",        0x4800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
-{"add.ps",             "D,V,T",        0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33|IL2F,     0,      0 },
+{"add.ps",             "D,V,T",        0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33|IL2F,     0,      I37 },
 {"add.ps",             "D,V,T",        0x45600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"add.qh",             "X,Y,Q",        0x7820000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"adda.ob",            "Y,Q",          0x78000037, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        SB1,            MX,     0 },
 {"adda.qh",            "Y,Q",          0x78200037, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        0,              MX,     0 },
 {"adda.s",             "S,T",          0x46000018, 0xffe007ff, RD_1|RD_2|FP_S,         0,              EE,             0,      0 },
-{"addi",               "t,r,j",        0x20000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      0 },
+{"addi",               "t,r,j",        0x20000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      I37 },
 {"addiu",              "t,r,j",        0x24000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      0 },
+{"addiu",              "s,+R,-a",      0xec000000, 0xfc180000, WR_1,                   RD_pc,          I37,            0,      0 },
+{"addiupc",            "s,-a",         0xec000000, 0xfc180000, WR_1,                   RD_pc,          I37,            0,      0 },
 {"addl.ob",            "Y,Q",          0x78000437, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        SB1,            MX,     0 },
 {"addl.qh",            "Y,Q",          0x78200437, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        0,              MX,     0 },
 {"addr.ps",            "D,S,T",        0x46c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              M3D,    0 },
@@ -622,7 +661,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"alni.ob",            "X,Y,Z,O",      0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"alni.ob",            "D,S,T,%",      0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"alni.qh",            "X,Y,Z,O",      0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
-{"alnv.ps",            "D,V,T,s",      0x4c00001e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I5_33,          0,      0 },
+{"alnv.ps",            "D,V,T,s",      0x4c00001e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I5_33,          0,      I37 },
 {"alnv.ob",            "X,Y,Z,s",      0x78000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            SB1,            MX,     0 },
 {"alnv.qh",            "X,Y,Z,s",      0x7800001b, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            0,              MX,     0 },
 {"and",                        "d,v,t",        0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
@@ -649,198 +688,200 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bc1any2t",           "N,p",          0x45210000, 0xffe30000, RD_CC|CBD|FP_S,         0,              0,              M3D,    0 },
 {"bc1any4f",           "N,p",          0x45400000, 0xffe30000, RD_CC|CBD|FP_S,         0,              0,              M3D,    0 },
 {"bc1any4t",           "N,p",          0x45410000, 0xffe30000, RD_CC|CBD|FP_S,         0,              0,              M3D,    0 },
-{"bc1f",               "p",            0x45000000, 0xffff0000, RD_CC|CBD|FP_S,         0,              I1,             0,      0 },
-{"bc1f",               "N,p",          0x45000000, 0xffe30000, RD_CC|CBD|FP_S,         0,              I4_32,          0,      0 },
-{"bc1fl",              "p",            0x45020000, 0xffff0000, RD_CC|CBL|FP_S,         0,              I2|T3,          0,      0 },
-{"bc1fl",              "N,p",          0x45020000, 0xffe30000, RD_CC|CBL|FP_S,         0,              I4_32,          0,      0 },
-{"bc1t",               "p",            0x45010000, 0xffff0000, RD_CC|CBD|FP_S,         0,              I1,             0,      0 },
-{"bc1t",               "N,p",          0x45010000, 0xffe30000, RD_CC|CBD|FP_S,         0,              I4_32,          0,      0 },
-{"bc1tl",              "p",            0x45030000, 0xffff0000, RD_CC|CBL|FP_S,         0,              I2|T3,          0,      0 },
-{"bc1tl",              "N,p",          0x45030000, 0xffe30000, RD_CC|CBL|FP_S,         0,              I4_32,          0,      0 },
+{"bc1eqz",             "T,p",          0x45200000, 0xffe00000, RD_1|CBD|FP_S,          0,              I37,            0,      0 },
+{"bc1f",               "p",            0x45000000, 0xffff0000, RD_CC|CBD|FP_S,         0,              I1,             0,      I37 },
+{"bc1f",               "N,p",          0x45000000, 0xffe30000, RD_CC|CBD|FP_S,         0,              I4_32,          0,      I37 },
+{"bc1fl",              "p",            0x45020000, 0xffff0000, RD_CC|CBL|FP_S,         0,              I2|T3,          0,      I37 },
+{"bc1fl",              "N,p",          0x45020000, 0xffe30000, RD_CC|CBL|FP_S,         0,              I4_32,          0,      I37 },
+{"bc1nez",             "T,p",          0x45a00000, 0xffe00000, RD_1|CBD|FP_S,          0,              I37,            0,      0 },
+{"bc1t",               "p",            0x45010000, 0xffff0000, RD_CC|CBD|FP_S,         0,              I1,             0,      I37 },
+{"bc1t",               "N,p",          0x45010000, 0xffe30000, RD_CC|CBD|FP_S,         0,              I4_32,          0,      I37 },
+{"bc1tl",              "p",            0x45030000, 0xffff0000, RD_CC|CBL|FP_S,         0,              I2|T3,          0,      I37 },
+{"bc1tl",              "N,p",          0x45030000, 0xffe30000, RD_CC|CBL|FP_S,         0,              I4_32,          0,      I37 },
 /* bc2* are at the bottom of the table.  */
 /* bc3* are at the bottom of the table.  */
 {"beqz",               "s,p",          0x10000000, 0xfc1f0000, RD_1|CBD,               0,              I1,             0,      0 },
-{"beqzl",              "s,p",          0x50000000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      0 },
+{"beqzl",              "s,p",          0x50000000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      I37 },
 {"beq",                        "s,t,p",        0x10000000, 0xfc000000, RD_1|RD_2|CBD,          0,              I1,             0,      0 },
 {"beq",                        "s,I,p",        0,    (int) M_BEQ_I,    INSN_MACRO,             0,              I1,             0,      0 },
-{"beql",               "s,t,p",        0x50000000, 0xfc000000, RD_1|RD_2|CBL,          0,              I2|T3,          0,      0 },
-{"beql",               "s,I,p",        0,    (int) M_BEQL_I,   INSN_MACRO,             0,              I2|T3,          0,      0 },
+{"beql",               "s,t,p",        0x50000000, 0xfc000000, RD_1|RD_2|CBL,          0,              I2|T3,          0,      I37 },
+{"beql",               "s,I,p",        0,    (int) M_BEQL_I,   INSN_MACRO,             0,              I2|T3,          0,      I37 },
 {"bge",                        "s,t,p",        0,    (int) M_BGE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"bge",                        "s,I,p",        0,    (int) M_BGE_I,    INSN_MACRO,             0,              I1,             0,      0 },
-{"bgel",               "s,t,p",        0,    (int) M_BGEL,     INSN_MACRO,             0,              I2|T3,          0,      0 },
-{"bgel",               "s,I,p",        0,    (int) M_BGEL_I,   INSN_MACRO,             0,              I2|T3,          0,      0 },
+{"bgel",               "s,t,p",        0,    (int) M_BGEL,     INSN_MACRO,             0,              I2|T3,          0,      I37 },
+{"bgel",               "s,I,p",        0,    (int) M_BGEL_I,   INSN_MACRO,             0,              I2|T3,          0,      I37 },
 {"bgeu",               "s,t,p",        0,    (int) M_BGEU,     INSN_MACRO,             0,              I1,             0,      0 },
 {"bgeu",               "s,I,p",        0,    (int) M_BGEU_I,   INSN_MACRO,             0,              I1,             0,      0 },
-{"bgeul",              "s,t,p",        0,    (int) M_BGEUL,    INSN_MACRO,             0,              I2|T3,          0,      0 },
-{"bgeul",              "s,I,p",        0,    (int) M_BGEUL_I,  INSN_MACRO,             0,              I2|T3,          0,      0 },
+{"bgeul",              "s,t,p",        0,    (int) M_BGEUL,    INSN_MACRO,             0,              I2|T3,          0,      I37 },
+{"bgeul",              "s,I,p",        0,    (int) M_BGEUL_I,  INSN_MACRO,             0,              I2|T3,          0,      I37 },
 {"bgez",               "s,p",          0x04010000, 0xfc1f0000, RD_1|CBD,               0,              I1,             0,      0 },
-{"bgezl",              "s,p",          0x04030000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      0 },
-{"bgezal",             "s,p",          0x04110000, 0xfc1f0000, RD_1|WR_31|CBD,         0,              I1,             0,      0 },
-{"bgezall",            "s,p",          0x04130000, 0xfc1f0000, RD_1|WR_31|CBL,         0,              I2|T3,          0,      0 },
+{"bgezl",              "s,p",          0x04030000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      I37 },
+{"bgezal",             "s,p",          0x04110000, 0xfc1f0000, RD_1|WR_31|CBD,         0,              I1,             0,      I37 },
+{"bgezall",            "s,p",          0x04130000, 0xfc1f0000, RD_1|WR_31|CBL,         0,              I2|T3,          0,      I37 },
 {"bgt",                        "s,t,p",        0,    (int) M_BGT,      INSN_MACRO,             0,              I1,             0,      0 },
 {"bgt",                        "s,I,p",        0,    (int) M_BGT_I,    INSN_MACRO,             0,              I1,             0,      0 },
-{"bgtl",               "s,t,p",        0,    (int) M_BGTL,     INSN_MACRO,             0,              I2|T3,          0,      0 },
-{"bgtl",               "s,I,p",        0,    (int) M_BGTL_I,   INSN_MACRO,             0,              I2|T3,          0,      0 },
+{"bgtl",               "s,t,p",        0,    (int) M_BGTL,     INSN_MACRO,             0,              I2|T3,          0,      I37 },
+{"bgtl",               "s,I,p",        0,    (int) M_BGTL_I,   INSN_MACRO,             0,              I2|T3,          0,      I37 },
 {"bgtu",               "s,t,p",        0,    (int) M_BGTU,     INSN_MACRO,             0,              I1,             0,      0 },
 {"bgtu",               "s,I,p",        0,    (int) M_BGTU_I,   INSN_MACRO,             0,              I1,             0,      0 },
-{"bgtul",              "s,t,p",        0,    (int) M_BGTUL,    INSN_MACRO,             0,              I2|T3,          0,      0 },
-{"bgtul",              "s,I,p",        0,    (int) M_BGTUL_I,  INSN_MACRO,             0,              I2|T3,          0,      0 },
+{"bgtul",              "s,t,p",        0,    (int) M_BGTUL,    INSN_MACRO,             0,              I2|T3,          0,      I37 },
+{"bgtul",              "s,I,p",        0,    (int) M_BGTUL_I,  INSN_MACRO,             0,              I2|T3,          0,      I37 },
 {"bgtz",               "s,p",          0x1c000000, 0xfc1f0000, RD_1|CBD,               0,              I1,             0,      0 },
-{"bgtzl",              "s,p",          0x5c000000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      0 },
+{"bgtzl",              "s,p",          0x5c000000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      I37 },
 {"ble",                        "s,t,p",        0,    (int) M_BLE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"ble",                        "s,I,p",        0,    (int) M_BLE_I,    INSN_MACRO,             0,              I1,             0,      0 },
-{"blel",               "s,t,p",        0,    (int) M_BLEL,     INSN_MACRO,             0,              I2|T3,          0,      0 },
-{"blel",               "s,I,p",        0,    (int) M_BLEL_I,   INSN_MACRO,             0,              I2|T3,          0,      0 },
+{"blel",               "s,t,p",        0,    (int) M_BLEL,     INSN_MACRO,             0,              I2|T3,          0,      I37 },
+{"blel",               "s,I,p",        0,    (int) M_BLEL_I,   INSN_MACRO,             0,              I2|T3,          0,      I37 },
 {"bleu",               "s,t,p",        0,    (int) M_BLEU,     INSN_MACRO,             0,              I1,             0,      0 },
 {"bleu",               "s,I,p",        0,    (int) M_BLEU_I,   INSN_MACRO,             0,              I1,             0,      0 },
-{"bleul",              "s,t,p",        0,    (int) M_BLEUL,    INSN_MACRO,             0,              I2|T3,          0,      0 },
-{"bleul",              "s,I,p",        0,    (int) M_BLEUL_I,  INSN_MACRO,             0,              I2|T3,          0,      0 },
+{"bleul",              "s,t,p",        0,    (int) M_BLEUL,    INSN_MACRO,             0,              I2|T3,          0,      I37 },
+{"bleul",              "s,I,p",        0,    (int) M_BLEUL_I,  INSN_MACRO,             0,              I2|T3,          0,      I37 },
 {"blez",               "s,p",          0x18000000, 0xfc1f0000, RD_1|CBD,               0,              I1,             0,      0 },
-{"blezl",              "s,p",          0x58000000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      0 },
+{"blezl",              "s,p",          0x58000000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      I37 },
 {"blt",                        "s,t,p",        0,    (int) M_BLT,      INSN_MACRO,             0,              I1,             0,      0 },
 {"blt",                        "s,I,p",        0,    (int) M_BLT_I,    INSN_MACRO,             0,              I1,             0,      0 },
-{"bltl",               "s,t,p",        0,    (int) M_BLTL,     INSN_MACRO,             0,              I2|T3,          0,      0 },
-{"bltl",               "s,I,p",        0,    (int) M_BLTL_I,   INSN_MACRO,             0,              I2|T3,          0,      0 },
+{"bltl",               "s,t,p",        0,    (int) M_BLTL,     INSN_MACRO,             0,              I2|T3,          0,      I37 },
+{"bltl",               "s,I,p",        0,    (int) M_BLTL_I,   INSN_MACRO,             0,              I2|T3,          0,      I37 },
 {"bltu",               "s,t,p",        0,    (int) M_BLTU,     INSN_MACRO,             0,              I1,             0,      0 },
 {"bltu",               "s,I,p",        0,    (int) M_BLTU_I,   INSN_MACRO,             0,              I1,             0,      0 },
-{"bltul",              "s,t,p",        0,    (int) M_BLTUL,    INSN_MACRO,             0,              I2|T3,          0,      0 },
-{"bltul",              "s,I,p",        0,    (int) M_BLTUL_I,  INSN_MACRO,             0,              I2|T3,          0,      0 },
+{"bltul",              "s,t,p",        0,    (int) M_BLTUL,    INSN_MACRO,             0,              I2|T3,          0,      I37 },
+{"bltul",              "s,I,p",        0,    (int) M_BLTUL_I,  INSN_MACRO,             0,              I2|T3,          0,      I37 },
 {"bltz",               "s,p",          0x04000000, 0xfc1f0000, RD_1|CBD,               0,              I1,             0,      0 },
-{"bltzl",              "s,p",          0x04020000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      0 },
-{"bltzal",             "s,p",          0x04100000, 0xfc1f0000, RD_1|WR_31|CBD,         0,              I1,             0,      0 },
-{"bltzall",            "s,p",          0x04120000, 0xfc1f0000, RD_1|WR_31|CBL,         0,              I2|T3,          0,      0 },
+{"bltzl",              "s,p",          0x04020000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      I37 },
+{"bltzal",             "s,p",          0x04100000, 0xfc1f0000, RD_1|WR_31|CBD,         0,              I1,             0,      I37 },
+{"bltzall",            "s,p",          0x04120000, 0xfc1f0000, RD_1|WR_31|CBL,         0,              I2|T3,          0,      I37 },
 {"bnez",               "s,p",          0x14000000, 0xfc1f0000, RD_1|CBD,               0,              I1,             0,      0 },
-{"bnezl",              "s,p",          0x54000000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      0 },
+{"bnezl",              "s,p",          0x54000000, 0xfc1f0000, RD_1|CBL,               0,              I2|T3,          0,      I37 },
 {"bne",                        "s,t,p",        0x14000000, 0xfc000000, RD_1|RD_2|CBD,          0,              I1,             0,      0 },
 {"bne",                        "s,I,p",        0,    (int) M_BNE_I,    INSN_MACRO,             0,              I1,             0,      0 },
-{"bnel",               "s,t,p",        0x54000000, 0xfc000000, RD_1|RD_2|CBL,          0,              I2|T3,          0,      0 },
-{"bnel",               "s,I,p",        0,    (int) M_BNEL_I,   INSN_MACRO,             0,              I2|T3,          0,      0 },
+{"bnel",               "s,t,p",        0x54000000, 0xfc000000, RD_1|RD_2|CBL,          0,              I2|T3,          0,      I37 },
+{"bnel",               "s,I,p",        0,    (int) M_BNEL_I,   INSN_MACRO,             0,              I2|T3,          0,      I37 },
 {"break",              "",             0x0000000d, 0xffffffff, TRAP,                   0,              I1,             0,      0 },
 {"break",              "c",            0x0000000d, 0xfc00ffff, TRAP,                   0,              I1,             0,      0 },
 {"break",              "c,q",          0x0000000d, 0xfc00003f, TRAP,                   0,              I1,             0,      0 },
-{"c.f.d",              "S,T",          0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.f.d",              "M,S,T",        0x46200030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.f.s",              "S,T",          0x46000030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      0 },
-{"c.f.s",              "M,S,T",        0x46000030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.f.ps",             "S,T",          0x46c00030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.f.d",              "S,T",          0x46200030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.f.d",              "M,S,T",        0x46200030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.f.s",              "S,T",          0x46000030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      I37 },
+{"c.f.s",              "M,S,T",        0x46000030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.f.ps",             "S,T",          0x46c00030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.f.ps",             "S,T",          0x45600030, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.f.ps",             "M,S,T",        0x46c00030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.un.d",             "S,T",          0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.un.d",             "M,S,T",        0x46200031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.un.s",             "S,T",          0x46000031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.un.s",             "M,S,T",        0x46000031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.un.ps",            "S,T",          0x46c00031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.f.ps",             "M,S,T",        0x46c00030, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.un.d",             "S,T",          0x46200031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.un.d",             "M,S,T",        0x46200031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.un.s",             "S,T",          0x46000031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.un.s",             "M,S,T",        0x46000031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.un.ps",            "S,T",          0x46c00031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.un.ps",            "S,T",          0x45600031, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.un.ps",            "M,S,T",        0x46c00031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.eq.d",             "S,T",          0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.eq.d",             "M,S,T",        0x46200032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.eq.s",             "S,T",          0x46000032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      0 },
-{"c.eq.s",             "M,S,T",        0x46000032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
+{"c.un.ps",            "M,S,T",        0x46c00031, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.eq.d",             "S,T",          0x46200032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.eq.d",             "M,S,T",        0x46200032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.eq.s",             "S,T",          0x46000032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      I37 },
+{"c.eq.s",             "M,S,T",        0x46000032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
 {"c.eq.ob",            "Y,Q",          0x78000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D,   0,              SB1,            MX,     0 },
 {"c.eq.ob",            "S,Q",          0x48000001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D,   0,              N54,            0,      0 },
-{"c.eq.ps",            "S,T",          0x46c00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.eq.ps",            "S,T",          0x46c00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.eq.ps",            "S,T",          0x45600032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.eq.ps",            "M,S,T",        0x46c00032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
+{"c.eq.ps",            "M,S,T",        0x46c00032, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
 {"c.eq.qh",            "Y,Q",          0x78200001, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              MX,     0 },
-{"c.ueq.d",            "S,T",          0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.ueq.d",            "M,S,T",        0x46200033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.ueq.s",            "S,T",          0x46000033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.ueq.s",            "M,S,T",        0x46000033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.ueq.ps",           "S,T",          0x46c00033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.ueq.d",            "S,T",          0x46200033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.ueq.d",            "M,S,T",        0x46200033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.ueq.s",            "S,T",          0x46000033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.ueq.s",            "M,S,T",        0x46000033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.ueq.ps",           "S,T",          0x46c00033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.ueq.ps",           "S,T",          0x45600033, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.ueq.ps",           "M,S,T",        0x46c00033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.olt.d",            "S,T",          0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.olt.d",            "M,S,T",        0x46200034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.olt.s",            "S,T",          0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.olt.s",            "M,S,T",        0x46000034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.olt.ps",           "S,T",          0x46c00034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.ueq.ps",           "M,S,T",        0x46c00033, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.olt.d",            "S,T",          0x46200034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.olt.d",            "M,S,T",        0x46200034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.olt.s",            "S,T",          0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.olt.s",            "M,S,T",        0x46000034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.olt.ps",           "S,T",          0x46c00034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.olt.ps",           "S,T",          0x45600034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.olt.ps",           "M,S,T",        0x46c00034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.ult.d",            "S,T",          0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.ult.d",            "M,S,T",        0x46200035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.ult.s",            "S,T",          0x46000035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.ult.s",            "M,S,T",        0x46000035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.ult.ps",           "S,T",          0x46c00035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.olt.ps",           "M,S,T",        0x46c00034, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.ult.d",            "S,T",          0x46200035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.ult.d",            "M,S,T",        0x46200035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.ult.s",            "S,T",          0x46000035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.ult.s",            "M,S,T",        0x46000035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.ult.ps",           "S,T",          0x46c00035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.ult.ps",           "S,T",          0x45600035, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.ult.ps",           "M,S,T",        0x46c00035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.ole.d",            "S,T",          0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.ole.d",            "M,S,T",        0x46200036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.ole.s",            "S,T",          0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.ole.s",            "M,S,T",        0x46000036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.ole.ps",           "S,T",          0x46c00036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.ult.ps",           "M,S,T",        0x46c00035, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.ole.d",            "S,T",          0x46200036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.ole.d",            "M,S,T",        0x46200036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.ole.s",            "S,T",          0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.ole.s",            "M,S,T",        0x46000036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.ole.ps",           "S,T",          0x46c00036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.ole.ps",           "S,T",          0x45600036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.ole.ps",           "M,S,T",        0x46c00036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.ule.d",            "S,T",          0x46200037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.ule.d",            "M,S,T",        0x46200037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.ule.s",            "S,T",          0x46000037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.ule.s",            "M,S,T",        0x46000037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.ule.ps",           "S,T",          0x46c00037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.ole.ps",           "M,S,T",        0x46c00036, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.ule.d",            "S,T",          0x46200037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.ule.d",            "M,S,T",        0x46200037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.ule.s",            "S,T",          0x46000037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.ule.s",            "M,S,T",        0x46000037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.ule.ps",           "S,T",          0x46c00037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.ule.ps",           "S,T",          0x45600037, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.ule.ps",           "M,S,T",        0x46c00037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.sf.d",             "S,T",          0x46200038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.sf.d",             "M,S,T",        0x46200038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.sf.s",             "S,T",          0x46000038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.sf.s",             "M,S,T",        0x46000038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.sf.ps",            "S,T",          0x46c00038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.ule.ps",           "M,S,T",        0x46c00037, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.sf.d",             "S,T",          0x46200038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.sf.d",             "M,S,T",        0x46200038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.sf.s",             "S,T",          0x46000038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.sf.s",             "M,S,T",        0x46000038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.sf.ps",            "S,T",          0x46c00038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.sf.ps",            "S,T",          0x45600038, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.sf.ps",            "M,S,T",        0x46c00038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.ngle.d",           "S,T",          0x46200039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.ngle.d",           "M,S,T",        0x46200039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.ngle.s",           "S,T",          0x46000039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.ngle.s",           "M,S,T",        0x46000039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.ngle.ps",          "S,T",          0x46c00039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.sf.ps",            "M,S,T",        0x46c00038, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.ngle.d",           "S,T",          0x46200039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.ngle.d",           "M,S,T",        0x46200039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.ngle.s",           "S,T",          0x46000039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.ngle.s",           "M,S,T",        0x46000039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.ngle.ps",          "S,T",          0x46c00039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.ngle.ps",          "S,T",          0x45600039, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.ngle.ps",          "M,S,T",        0x46c00039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.seq.d",            "S,T",          0x4620003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.seq.d",            "M,S,T",        0x4620003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.seq.s",            "S,T",          0x4600003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.seq.s",            "M,S,T",        0x4600003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.seq.ps",           "S,T",          0x46c0003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.ngle.ps",          "M,S,T",        0x46c00039, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.seq.d",            "S,T",          0x4620003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.seq.d",            "M,S,T",        0x4620003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.seq.s",            "S,T",          0x4600003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.seq.s",            "M,S,T",        0x4600003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.seq.ps",           "S,T",          0x46c0003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.seq.ps",           "S,T",          0x4560003a, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.seq.ps",           "M,S,T",        0x46c0003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.ngl.d",            "S,T",          0x4620003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.ngl.d",            "M,S,T",        0x4620003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.ngl.s",            "S,T",          0x4600003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.ngl.s",            "M,S,T",        0x4600003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.ngl.ps",           "S,T",          0x46c0003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.seq.ps",           "M,S,T",        0x46c0003a, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.ngl.d",            "S,T",          0x4620003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.ngl.d",            "M,S,T",        0x4620003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.ngl.s",            "S,T",          0x4600003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.ngl.s",            "M,S,T",        0x4600003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.ngl.ps",           "S,T",          0x46c0003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.ngl.ps",           "S,T",          0x4560003b, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.ngl.ps",           "M,S,T",        0x46c0003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.lt.d",             "S,T",          0x4620003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.lt.d",             "M,S,T",        0x4620003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
+{"c.ngl.ps",           "M,S,T",        0x46c0003b, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.lt.d",             "S,T",          0x4620003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.lt.d",             "M,S,T",        0x4620003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
 {"c.lt.s",             "S,T",          0x46000034, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              EE,             0,      0 },
-{"c.lt.s",             "S,T",          0x4600003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.lt.s",             "M,S,T",        0x4600003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
+{"c.lt.s",             "S,T",          0x4600003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.lt.s",             "M,S,T",        0x4600003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
 {"c.lt.ob",            "Y,Q",          0x78000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D,   0,              SB1,            MX,     0 },
 {"c.lt.ob",            "S,Q",          0x48000004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D,   0,              N54,            0,      0 },
-{"c.lt.ps",            "S,T",          0x46c0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.lt.ps",            "S,T",          0x46c0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.lt.ps",            "S,T",          0x4560003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.lt.ps",            "M,S,T",        0x46c0003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
+{"c.lt.ps",            "M,S,T",        0x46c0003c, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
 {"c.lt.qh",            "Y,Q",          0x78200004, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              MX,     0 },
-{"c.nge.d",            "S,T",          0x4620003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.nge.d",            "M,S,T",        0x4620003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.nge.s",            "S,T",          0x4600003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.nge.s",            "M,S,T",        0x4600003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.nge.ps",           "S,T",          0x46c0003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.nge.d",            "S,T",          0x4620003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.nge.d",            "M,S,T",        0x4620003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.nge.s",            "S,T",          0x4600003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.nge.s",            "M,S,T",        0x4600003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.nge.ps",           "S,T",          0x46c0003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.nge.ps",           "S,T",          0x4560003d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.nge.ps",           "M,S,T",        0x46c0003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
-{"c.le.d",             "S,T",          0x4620003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.le.d",             "M,S,T",        0x4620003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
+{"c.nge.ps",           "M,S,T",        0x46c0003d, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"c.le.d",             "S,T",          0x4620003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.le.d",             "M,S,T",        0x4620003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
 {"c.le.s",             "S,T",          0x46000036, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              EE,             0,      0 },
-{"c.le.s",             "S,T",          0x4600003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.le.s",             "M,S,T",        0x4600003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
+{"c.le.s",             "S,T",          0x4600003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.le.s",             "M,S,T",        0x4600003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
 {"c.le.ob",            "Y,Q",          0x78000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D,   0,              SB1,            MX,     0 },
 {"c.le.ob",            "S,Q",          0x48000005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D,   0,              N54,            0,      0 },
-{"c.le.ps",            "S,T",          0x46c0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.le.ps",            "S,T",          0x46c0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.le.ps",            "S,T",          0x4560003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.le.ps",            "M,S,T",        0x46c0003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
+{"c.le.ps",            "M,S,T",        0x46c0003e, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
 {"c.le.qh",            "Y,Q",          0x78200005, 0xfc2007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              MX,     0 },
-{"c.ngt.d",            "S,T",          0x4620003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF },
-{"c.ngt.d",            "M,S,T",        0x4620003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      0 },
-{"c.ngt.s",            "S,T",          0x4600003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE },
-{"c.ngt.s",            "M,S,T",        0x4600003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      0 },
-{"c.ngt.ps",           "S,T",          0x46c0003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      0 },
+{"c.ngt.d",            "S,T",          0x4620003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I1,             0,      SF|I37 },
+{"c.ngt.d",            "M,S,T",        0x4620003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I4_32,          0,      I37 },
+{"c.ngt.s",            "S,T",          0x4600003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_S,   0,              I1,             0,      EE|I37 },
+{"c.ngt.s",            "M,S,T",        0x4600003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"c.ngt.ps",           "S,T",          0x46c0003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              I5_33|IL2F,     0,      I37 },
 {"c.ngt.ps",           "S,T",          0x4560003f, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"c.ngt.ps",           "M,S,T",        0x46c0003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      0 },
+{"c.ngt.ps",           "M,S,T",        0x46c0003f, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              I5_33,          0,      I37 },
 {"cabs.eq.d",          "M,S,T",        0x46200072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              0,              M3D,    0 },
 {"cabs.eq.ps",         "M,S,T",        0x46c00072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_D,   0,              0,              M3D,    0 },
 {"cabs.eq.s",          "M,S,T",        0x46000072, 0xffe000ff, RD_2|RD_3|WR_CC|FP_S,   0,              0,              M3D,    0 },
@@ -894,33 +935,36 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"flushd",             "",             0xbc020000, 0xffffffff, 0,                      0,              L1,             0,      0 },
 {"flushid",            "",             0xbc030000, 0xffffffff, 0,                      0,              L1,             0,      0 },
 {"wb",                 "o(b)",         0xbc040000, 0xfc1f0000, RD_2|SM,                0,              L1,             0,      0 },
-{"cache",              "k,o(b)",       0xbc000000, 0xfc000000, RD_3,                   0,              I3_32|T3,       0,      0},
-{"cache",              "k,A(b)",       0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3_32|T3,       0,      0},
+{"cache",              "k,+j(b)",      0x7c000025, 0xfc00007f, RD_3,                   0,              I37,            0,      0 },
+{"cache",              "k,o(b)",       0xbc000000, 0xfc000000, RD_3,                   0,              I3_32|T3,       0,      I37 },
+{"cache",              "k,A(b)",       0,    (int) M_CACHE_AB, INSN_MACRO,             0,              I3_32|T3,       0,      0 },
 {"ceil.l.d",           "D,S",          0x4620000a, 0xffff003f, WR_1|RD_2|FP_D,         0,              I3_33,          0,      0 },
 {"ceil.l.s",           "D,S",          0x4600000a, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I3_33,          0,      0 },
 {"ceil.w.d",           "D,S",          0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I2,             0,      SF },
 {"ceil.w.s",           "D,S",          0x4600000e, 0xffff003f, WR_1|RD_2|FP_S,         0,              I2,             0,      EE },
 /* cfc0 is at the bottom of the table.  */
-{"cfc1",               "t,G",          0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S,    0,              I1,             0,      0 },
-{"cfc1",               "t,S",          0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S,    0,              I1,             0,      0 },
+{"cfc1",               "t,G",          0x44400000, 0xffe007ff, WR_1|RD_C1|LC,          0,              I1,             0,      0 },
+{"cfc1",               "t,S",          0x44400000, 0xffe007ff, WR_1|RD_C1|LC,          0,              I1,             0,      0 },
 /* cfc2 is at the bottom of the table.  */
 /* cfc3 is at the bottom of the table.  */
-{"cftc1",              "d,E",          0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD|FP_S, 0,            0,              MT32,   0 },
-{"cftc1",              "d,T",          0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD|FP_S, 0,            0,              MT32,   0 },
-{"cftc2",              "d,E",          0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LCD,    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"cftc1",              "d,E",          0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC,     0,              0,              MT32,   0 },
+{"cftc1",              "d,T",          0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LC,     0,              0,              MT32,   0 },
+{"cftc2",              "d,E",          0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LC    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"cins32",             "t,r,+p,+s",    0x70000033, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"cins",               "t,r,+P,+S",    0x70000033, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 }, /* cins32 */
 {"cins",               "t,r,+p,+S",    0x70000032, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
-{"clo",                        "U,s",          0x70000021, 0xfc0007ff, WR_1|RD_2,      0,              I32|N55,        0,      0 },
-{"clz",                        "U,s",          0x70000020, 0xfc0007ff, WR_1|RD_2,      0,              I32|N55,        0,      0 },
+{"clo",                        "d,s",          0x00000051, 0xfc1f07ff, WR_1|RD_2,              0,              I37,            0,      0 },
+{"clo",                        "U,s",          0x70000021, 0xfc0007ff, WR_1|RD_2,              0,              I32|N55,        0,      I37 },
+{"clz",                        "d,s",          0x00000050, 0xfc1f07ff, WR_1|RD_2,              0,              I37,            0,      0 },
+{"clz",                        "U,s",          0x70000020, 0xfc0007ff, WR_1|RD_2,              0,              I32|N55,        0,      I37 },
 /* ctc0 is at the bottom of the table.  */
-{"ctc1",               "t,G",          0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S,    0,              I1,             0,      0 },
-{"ctc1",               "t,S",          0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S,    0,              I1,             0,      0 },
+{"ctc1",               "t,G",          0x44c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      0 },
+{"ctc1",               "t,S",          0x44c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      0 },
 /* ctc2 is at the bottom of the table.  */
 /* ctc3 is at the bottom of the table.  */
-{"cttc1",              "t,g",          0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD|FP_S, 0,            0,              MT32,   0 },
-{"cttc1",              "t,S",          0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD|FP_S, 0,            0,              MT32,   0 },
-{"cttc2",              "t,g",          0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|COD,    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"cttc1",              "t,G",          0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   0 },
+{"cttc1",              "t,S",          0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   0 },
+{"cttc2",              "t,g",          0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|CM,     0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"cvt.d.l",            "D,S",          0x46a00021, 0xffff003f, WR_1|RD_2|FP_D,         0,              I3_33,          0,      0 },
 {"cvt.d.s",            "D,S",          0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      SF },
 {"cvt.d.w",            "D,S",          0x46800021, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      SF },
@@ -934,21 +978,23 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"cvt.w.d",            "D,S",          0x46200024, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I1,             0,      SF },
 {"cvt.w.s",            "D,S",          0x46000024, 0xffff003f, WR_1|RD_2|FP_S,         0,              I1,             0,      EE },
 {"cvt.ps.pw",          "D,S",          0x46800026, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              0,              M3D,    0 },
-{"cvt.ps.s",           "D,V,T",        0x46000026, 0xffe0003f, WR_1|RD_2|RD_3|FP_S|FP_D, 0,            I5_33,          0,      0 },
+{"cvt.ps.s",           "D,V,T",        0x46000026, 0xffe0003f, WR_1|RD_2|RD_3|FP_S|FP_D, 0,            I5_33,          0,      I37 },
 {"cvt.pw.ps",          "D,S",          0x46c00024, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              0,              M3D,    0 },
 {"dabs",               "d,v",          0,    (int) M_DABS,     INSN_MACRO,             0,              I3,             0,      0 },
 {"dadd",               "d,v,t",        0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
-{"dadd",               "t,r,I",        0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3,             0,      0 },
+{"dadd",               "t,r,I",        0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3,             0,      I69 },
 {"dadd",               "D,S,T",        0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"dadd",               "D,S,T",        0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
-{"daddi",              "t,r,j",        0x60000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      0 },
+{"daddi",              "t,r,j",        0x60000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      I69 },
 {"daddiu",             "t,r,j",        0x64000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      0 },
 {"daddu",              "d,v,t",        0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"daddu",              "t,r,I",        0,    (int) M_DADDU_I,  INSN_MACRO,             0,              I3,             0,      0 },
 {"daddwc",             "d,s,t",        0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0,          XLR,            0,      0 },
 {"dbreak",             "",             0x7000003f, 0xffffffff, 0,                      0,              N5,             0,      0 },
-{"dclo",               "U,s",          0x70000025, 0xfc0007ff, WR_1|RD_2,      0,              I64|N55,        0,      0 },
-{"dclz",               "U,s",          0x70000024, 0xfc0007ff, WR_1|RD_2,      0,              I64|N55,        0,      0 },
+{"dclo",               "d,s",          0x00000053, 0xfc1f07ff, WR_1|RD_2,              0,              I69,            0,      0 },
+{"dclo",               "U,s",          0x70000025, 0xfc0007ff, WR_1|RD_2,      0,              I64|N55,        0,      I69 },
+{"dclz",               "d,s",          0x00000052, 0xfc1f07ff, WR_1|RD_2,              0,              I69,            0,      0 },
+{"dclz",               "U,s",          0x70000024, 0xfc0007ff, WR_1|RD_2,      0,              I64|N55,        0,      I69 },
 /* dctr and dctw are used on the r5000.  */
 {"dctr",               "o(b)",         0xbc050000, 0xfc1f0000, RD_2,                   0,              I3,             0,      0 },
 {"dctw",               "o(b)",         0xbc090000, 0xfc1f0000, RD_2,                   0,              I3,             0,      0 },
@@ -959,13 +1005,17 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dextm",              "t,r,+A,+G",    0x7c000001, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 },
 {"dextu",              "t,r,+E,+H",    0x7c000002, 0xfc00003f, WR_1|RD_2,              0,              I65,            0,      0 },
 /* For ddiv, see the comments about div.  */
-{"ddiv",               "z,s,t",        0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I3,             0,      M32 },
-{"ddiv",               "d,v,t",        0,    (int) M_DDIV_3,   INSN_MACRO,             0,              I3,             0,      M32 },
-{"ddiv",               "d,v,I",        0,    (int) M_DDIV_3I,  INSN_MACRO,             0,              I3,             0,      M32 },
+{"dmod",               "d,s,t",        0x000000de, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
+{"ddiv",               "d,s,t",        0x0000009e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
+{"ddiv",               "z,s,t",        0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I3,             0,      M32|I69 },
+{"ddiv",               "d,v,t",        0,    (int) M_DDIV_3,   INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"ddiv",               "d,v,I",        0,    (int) M_DDIV_3I,  INSN_MACRO,             0,              I3,             0,      M32|I69 },
 /* For ddivu, see the comments about div.  */
-{"ddivu",              "z,s,t",        0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I3,             0,      M32 },
-{"ddivu",              "d,v,t",        0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3,             0,      M32 },
-{"ddivu",              "d,v,I",        0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3,             0,      M32 },
+{"dmodu",              "d,s,t",        0x000000df, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
+{"ddivu",              "d,s,t",        0x0000009f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
+{"ddivu",              "z,s,t",        0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I3,             0,      M32|I69 },
+{"ddivu",              "d,v,t",        0,    (int) M_DDIVU_3,  INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"ddivu",              "d,v,I",        0,    (int) M_DDIVU_3I, INSN_MACRO,             0,              I3,             0,      M32|I69 },
 {"di",                 "",             0x42000039, 0xffffffff, WR_C0,                  0,              EE,             0,      0 },
 {"di",                 "",             0x41606000, 0xffffffff, WR_C0,                  0,              I33,            0,      0 },
 {"di",                 "t",            0x41606000, 0xffe0ffff, WR_1|WR_C0,             0,              I33,            0,      0 },
@@ -978,20 +1028,24 @@ const struct mips_opcode mips_builtin_opcodes[] =
    though the first operand appeared twice (the first operand is both
    a source and a destination).  To get the div machine instruction,
    you must use an explicit destination of $0.  */
-{"div",                        "z,s,t",        0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I1,             0,      0 },
-{"div",                        "z,t",          0x0000001a, 0xffe0ffff, RD_2|WR_HILO,           0,              I1,             0,      0 },
-{"div",                        "d,v,t",        0,    (int) M_DIV_3,    INSN_MACRO,             0,              I1,             0,      0 },
-{"div",                        "d,v,I",        0,    (int) M_DIV_3I,   INSN_MACRO,             0,              I1,             0,      0 },
+{"mod",                        "d,v,t",        0x000000da, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I37,            0,      0},
+{"modu",               "d,v,t",        0x000000db, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I37,            0,      0},
+{"div",                        "d,v,t",        0x0000009a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I37,            0,      0},
+{"div",                        "z,s,t",        0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I1,             0,      I37 },
+{"div",                        "z,t",          0x0000001a, 0xffe0ffff, RD_2|WR_HILO,           0,              I1,             0,      I37 },
+{"div",                        "d,v,t",        0,    (int) M_DIV_3,    INSN_MACRO,             0,              I1,             0,      I37 },
+{"div",                        "d,v,I",        0,    (int) M_DIV_3I,   INSN_MACRO,             0,              I1,             0,      I37 },
 {"div1",               "z,s,t",        0x7000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              EE,             0,      0 },
 {"div1",               "z,t",          0x7000001a, 0xffe0ffff, RD_2|WR_HILO,           0,              EE,             0,      0 },
 {"div.d",              "D,V,T",        0x46200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
 {"div.s",              "D,V,T",        0x46000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"div.ps",             "D,V,T",        0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            0,      0 },
 /* For divu, see the comments about div.  */
-{"divu",               "z,s,t",        0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I1,             0,      0 },
-{"divu",               "z,t",          0x0000001b, 0xffe0ffff, RD_2|WR_HILO,           0,              I1,             0,      0 },
-{"divu",               "d,v,t",        0,    (int) M_DIVU_3,   INSN_MACRO,             0,              I1,             0,      0 },
-{"divu",               "d,v,I",        0,    (int) M_DIVU_3I,  INSN_MACRO,             0,              I1,             0,      0 },
+{"divu",               "d,v,t",        0x0000009b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I37,            0,      0},
+{"divu",               "z,s,t",        0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I1,             0,      I37 },
+{"divu",               "z,t",          0x0000001b, 0xffe0ffff, RD_2|WR_HILO,           0,              I1,             0,      I37 },
+{"divu",               "d,v,t",        0,    (int) M_DIVU_3,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"divu",               "d,v,I",        0,    (int) M_DIVU_3I,  INSN_MACRO,             0,              I1,             0,      I37 },
 {"divu1",              "z,s,t",        0x7000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              EE,             0,      0 },
 {"divu1",              "z,t",          0x7000001b, 0xffe0ffff, RD_2|WR_HILO,           0,              EE,             0,      0 },
 {"dla",                        "t,A(b)",       0,    (int) M_DLA_AB,   INSN_MACRO,             0,              I3,             0,      0 },
@@ -1008,42 +1062,46 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmaccu",             "d,s,t",        0x00000069, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO,   0,              N412,           0,      0 },
 {"dmaccus",            "d,s,t",        0x00000469, 0xfc0007ff, WR_1|RD_2|RD_3|WR_LO,   0,              N412,           0,      0 },
 {"dmadd16",            "s,t",          0x00000029, 0xfc00ffff, RD_1|RD_2|MOD_LO,       0,              N411,           0,      0 },
-{"dmfc0",              "t,G",          0x40200000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I3,             0,      EE },
-{"dmfc0",              "t,G,H",        0x40200000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I64,            0,      0 },
-{"dmfgc0",             "t,G",          0x40600100, 0xffe007ff, WR_1|RD_C0|LCD,         0,              0,              IVIRT64, 0 },
-{"dmfgc0",             "t,G,H",        0x40600100, 0xffe007f8, WR_1|RD_C0|LCD,         0,              0,              IVIRT64, 0 },
+{"dmfc0",              "t,G",          0x40200000, 0xffe007ff, WR_1|RD_C0|LC         0,              I3,             0,      EE },
+{"dmfc0",              "t,G,H",        0x40200000, 0xffe007f8, WR_1|RD_C0|LC         0,              I64,            0,      0 },
+{"dmfgc0",             "t,G",          0x40600100, 0xffe007ff, WR_1|RD_C0|LC         0,              0,              IVIRT64, 0 },
+{"dmfgc0",             "t,G,H",        0x40600100, 0xffe007f8, WR_1|RD_C0|LC         0,              0,              IVIRT64, 0 },
 {"dmt",                        "",             0x41600bc1, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
 {"dmt",                        "t",            0x41600bc1, 0xffe0ffff, WR_1|TRAP,              0,              0,              MT32,   0 },
-{"dmtc0",              "t,G",          0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              I3,             0,      EE },
-{"dmtc0",              "t,G,H",        0x40a00000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I64,            0,      0 },
-{"dmtgc0",             "t,G",          0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              0,              IVIRT64, 0 },
-{"dmtgc0",             "t,G,H",        0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              0,              IVIRT64, 0 },
-{"dmfc1",              "t,S",          0x44200000, 0xffe007ff, WR_1|RD_2|LCD|FP_D,     0,              I3,             0,      SF },
-{"dmfc1",              "t,G",          0x44200000, 0xffe007ff, WR_1|RD_2|LCD|FP_D,     0,              I3,             0,      SF },
-{"dmtc1",              "t,S",          0x44a00000, 0xffe007ff, RD_1|WR_2|COD|FP_D,     0,              I3,             0,      SF },
-{"dmtc1",              "t,G",          0x44a00000, 0xffe007ff, RD_1|WR_2|COD|FP_D,     0,              I3,             0,      SF },
+{"dmtc0",              "t,G",          0x40a00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I3,             0,      EE },
+{"dmtc0",              "t,G,H",        0x40a00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I64,            0,      0 },
+{"dmtgc0",             "t,G",          0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              0,              IVIRT64, 0 },
+{"dmtgc0",             "t,G,H",        0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,   0,               0,              IVIRT64, 0 },
+{"dmfc1",              "t,S",          0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D,      0,              I3,             0,      SF },
+{"dmfc1",              "t,G",          0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D,     0,               I3,             0,      SF },
+{"dmtc1",              "t,S",          0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,      0,              I3,             0,      SF },
+{"dmtc1",              "t,G",          0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,     0,               I3,             0,      SF },
 /* dmfc2 is at the bottom of the table.  */
 /* dmtc2 is at the bottom of the table.  */
 /* dmfc3 is at the bottom of the table.  */
 /* dmtc3 is at the bottom of the table.  */
+{"dmuh",               "d,s,t",        0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
+{"dmul",               "d,s,t",        0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
 {"dmul",               "d,v,t",        0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              IOCT,           0,      0 },
-{"dmul",               "d,v,t",        0,    (int) M_DMUL,     INSN_MACRO,             0,              I3,             0,      M32 },
-{"dmul",               "d,v,I",        0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3,             0,      M32 },
-{"dmulo",              "d,v,t",        0,    (int) M_DMULO,    INSN_MACRO,             0,              I3,             0,      M32 },
-{"dmulo",              "d,v,I",        0,    (int) M_DMULO_I,  INSN_MACRO,             0,              I3,             0,      M32 },
-{"dmulou",             "d,v,t",        0,    (int) M_DMULOU,   INSN_MACRO,             0,              I3,             0,      M32 },
-{"dmulou",             "d,v,I",        0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3,             0,      M32 },
-{"dmult",              "s,t",          0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              I3,             0,      M32 },
-{"dmultu",             "s,t",          0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              I3,             0,      M32 },
+{"dmul",               "d,v,t",        0,    (int) M_DMUL,     INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"dmul",               "d,v,I",        0,    (int) M_DMUL_I,   INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"dmulo",              "d,v,t",        0,    (int) M_DMULO,    INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"dmulo",              "d,v,I",        0,    (int) M_DMULO_I,  INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"dmulou",             "d,v,t",        0,    (int) M_DMULOU,   INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"dmulou",             "d,v,I",        0,    (int) M_DMULOU_I, INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"dmult",              "s,t",          0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              I3,             0,      M32|I69 },
+{"dmulu",              "d,s,t",        0x0000009d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
+{"dmuhu",              "d,s,t",        0x000000dd, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
+{"dmultu",             "s,t",          0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              I3,             0,      M32|I69 },
 {"dneg",               "d,w",          0x0000002e, 0xffe007ff, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsub 0 */
 {"dnegu",              "d,w",          0x0000002f, 0xffe007ff, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsubu 0*/
 {"dpop",               "d,v",          0x7000002d, 0xfc1f07ff, WR_1|RD_2,              0,              IOCT,           0,      0 },
-{"drem",               "z,s,t",        0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I3,             0,      M32 },
-{"drem",               "d,v,t",        0,    (int) M_DREM_3,   INSN_MACRO,             0,              I3,             0,      M32 },
-{"drem",               "d,v,I",        0,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3,             0,      M32 },
-{"dremu",              "z,s,t",        0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I3,             0,      M32 },
-{"dremu",              "d,v,t",        0,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3,             0,      M32 },
-{"dremu",              "d,v,I",        0,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3,             0,      M32 },
+{"drem",               "z,s,t",        0x0000001e, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I3,             0,      M32|I69 },
+{"drem",               "d,v,t",        0,    (int) M_DREM_3,   INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"drem",               "d,v,I",        0,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"dremu",              "z,s,t",        0x0000001f, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I3,             0,      M32|I69 },
+{"dremu",              "d,v,t",        0,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3,             0,      M32|I69 },
+{"dremu",              "d,v,I",        0,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3,             0,      M32|I69 },
 {"dret",               "",             0x7000003e, 0xffffffff, 0,                      0,              N5,             0,      0 },
 {"drol",               "d,v,t",        0,    (int) M_DROL,     INSN_MACRO,             0,              I3,             0,      0 },
 {"drol",               "d,v,I",        0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3,             0,      0 },
@@ -1082,7 +1140,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsrl",               "D,S,T",        0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"dsrl",               "D,S,T",        0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
 {"dsub",               "d,v,t",        0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
-{"dsub",               "d,v,I",        0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3,             0,      0 },
+{"dsub",               "d,v,I",        0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3,             0,      I69 },
 {"dsub",               "D,S,T",        0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"dsub",               "D,S,T",        0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
 {"dsubu",              "d,v,t",        0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
@@ -1111,11 +1169,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"hypcall",            "+J",           0x42000028, 0xffe007ff, TRAP,                   0,              0,              IVIRT,  0 },
 {"ins",                        "t,r,+A,+B",    0x7c000004, 0xfc00003f, WR_1|RD_2,              0,              I33,            0,      0 },
 {"iret",               "",             0x42000038, 0xffffffff, NODS,                   0,              0,              MC,     0 },
-{"jr",                 "s",            0x00000008, 0xfc1fffff, RD_1|UBD,               0,              I1,             0,      0 },
+{"jr",                 "s",            0x00000009, 0xfc1fffff, RD_1|UBD,               INSN2_ALIAS,    I37,            0,      0 }, /* jalr $0 */
+{"jr",                 "s",            0x00000008, 0xfc1fffff, RD_1|UBD,               0,              I1,             0,      I37 },
+/* MIPS R6 jic appears before beqzc and jialc appears before bnezc */
 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
    the same hazard barrier effect.  */
-{"jr.hb",              "s",            0x00000408, 0xfc1fffff, RD_1|UBD,               0,              I32,            0,      0 },
-{"j",                  "s",            0x00000008, 0xfc1fffff, RD_1|UBD,               0,              I1,             0,      0 }, /* jr */
+{"jr.hb",              "s",            0x00000409, 0xfc1fffff, RD_1|UBD,               INSN2_ALIAS,    I37,            0,      0 }, /* jalr.hb $0 */
+{"jr.hb",              "s",            0x00000408, 0xfc1fffff, RD_1|UBD,               0,              I32,            0,      I37 },
+{"j",                  "s",            0x00000009, 0xfc1fffff, RD_1|UBD,               INSN2_ALIAS,    I37,            0,      0 }, /* jalr $0 */
+{"j",                  "s",            0x00000008, 0xfc1fffff, RD_1|UBD,               0,              I1,             0,      I37 }, /* jr */
 /* SVR4 PIC code requires special handling for j, so it must be a
    macro.  */
 {"j",                  "a",            0,     (int) M_J_A,     INSN_MACRO,             0,              I1,             0,      0 },
@@ -1138,8 +1200,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
    assembler, but will never match user input (because the line above
    will match first).  */
 {"jal",                        "a",            0x0c000000, 0xfc000000, WR_31|UBD,              0,              I1,             0,      0 },
-{"jalx",               "+i",           0x74000000, 0xfc000000, WR_31|UBD,              0,              I1,             0,      0 },
-{"la",                 "t,A(b)",       0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1,             0,      0 },
+{"jalx",               "+i",           0x74000000, 0xfc000000, WR_31|UBD,              0,              I1,             0,      I37 },
 {"laa",                        "d,(b),t",      0x7000049f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM,   0,              IOCT2,          0,      0 },
 {"laad",               "d,(b),t",      0x700004df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM,   0,              IOCT2,          0,      0 },
 {"lac",                        "d,(b)",        0x7000039f, 0xfc1f07ff, WR_1|RD_2|LM|SM,        0,              IOCT2,          0,      0 },
@@ -1164,7 +1225,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lwx",                        "d,t(b)",       0x7c00000a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IOCT2,          D32,    0},
 {"lwux",               "d,t(b)",       0x7c00040a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IOCT2,          0,      0 },
 {"lca",                        "t,A(b)",       0,    (int) M_LCA_AB,   INSN_MACRO,             0,              I1,             0,      0 },
+{"ldpc",               "s,-B",         0xec180000, 0xfc1c0000, WR_1,                   RD_pc,          I69,            0,      0 },
 /* The macro has to be first to handle o32 correctly.  */
+{"ld",                 "s,-b(+R)",     0xec180000, 0xfc1c0000, WR_1,                   RD_pc,          I69,            0,      0 },
 {"ld",                 "t,A(b)",       0,    (int) M_LD_AB,    INSN_MACRO,             0,              I1,             0,      0 },
 {"ld",                 "t,o(b)",       0xdc000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      0 },
 {"ldaddw",             "t,b",          0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM,       0,              XLR,            0,      0 },
@@ -1176,15 +1239,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ldc1",               "E,A(b)",       0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,             0,      SF },
 {"l.d",                        "T,o(b)",       0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D,     0,              I2,             0,      SF }, /* ldc1 */
 {"l.d",                        "T,A(b)",       0,    (int) M_L_DAB,    INSN_MACRO,             INSN2_M_FP_D,   I1,             0,      0 },
-{"ldc2",               "E,o(b)",       0xd8000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
+{"ldc2",               "E,+:(d)",      0x49c00000, 0xffe00000, RD_3|WR_C2|CLD,         0,              I37,            0,      0 },
+{"ldc2",               "E,o(b)",       0xd8000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I2,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
 {"ldc2",               "E,A(b)",       0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
 {"ldc3",               "E,o(b)",       0xdc000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
 {"ldc3",               "E,A(b)",       0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
-{"ldl",                        "t,o(b)",       0x68000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      0 },
-{"ldl",                        "t,A(b)",       0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3,             0,      0 },
-{"ldr",                        "t,o(b)",       0x6c000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      0 },
-{"ldr",                        "t,A(b)",       0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3,             0,      0 },
-{"ldxc1",              "D,t(b)",       0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0,              I4_33,          0,      0 },
+{"ldl",                        "t,o(b)",       0x68000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      I69 },
+{"ldl",                        "t,A(b)",       0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3,             0,      I69 },
+{"ldr",                        "t,o(b)",       0x6c000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      I69 },
+{"ldr",                        "t,A(b)",       0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3,             0,      I69 },
+{"ldxc1",              "D,t(b)",       0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0,              I4_33,          0,      I37 },
 {"lh",                 "t,o(b)",       0x84000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
 {"lh",                 "t,A(b)",       0,    (int) M_LH_AB,    INSN_MACRO,             0,              I1,             0,      0 },
 {"lhu",                        "t,o(b)",       0x94000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
@@ -1194,42 +1258,49 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"li.d",               "T,L",          0,    (int) M_LI_DD,    INSN_MACRO,             INSN2_M_FP_D,   I1,             0,      SF },
 {"li.s",               "t,f",          0,    (int) M_LI_S,     INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      0 },
 {"li.s",               "T,l",          0,    (int) M_LI_SS,    INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      0 },
-{"ll",                 "t,o(b)",       0xc0000000, 0xfc000000, WR_1|RD_3|LM,           0,              I2,             0,      EE },
+{"ll",                 "t,+j(b)",      0x7c000036, 0xfc00007f, WR_1|RD_3|LM,           0,              I37,            0,      0 },
+{"ll",                 "t,o(b)",       0xc0000000, 0xfc000000, WR_1|RD_3|LM,           0,              I2,             0,      EE|I37 },
 {"ll",                 "t,A(b)",       0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2,             0,      EE },
-{"lld",                        "t,o(b)",       0xd0000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      EE },
+{"lld",                        "t,+j(b)",      0x7c000037, 0xfc00007f, WR_1|RD_3|LM,           0,              I69,            0,      0 },
+{"lld",                        "t,o(b)",       0xd0000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      EE|I69 },
 {"lld",                        "t,A(b)",       0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3,             0,      EE },
 {"lq",                 "t,o(b)",       0x78000000, 0xfc000000, WR_1|RD_3|LM,           0,              MMI,            0,      0 },
 {"lq",                 "t,A(b)",       0,    (int) M_LQ_AB,    INSN_MACRO,             0,              MMI,            0,      0 },
 {"lqc2",               "+7,o(b)",      0xd8000000, 0xfc000000, RD_3|WR_C2|LM,          0,              EE,             0,      0 },
 {"lqc2",               "+7,A(b)",      0,    (int) M_LQC2_AB,  INSN_MACRO,             0,              EE,             0,      0 },
 {"lui",                        "t,u",          0x3c000000, 0xffe00000, WR_1,                   0,              I1,             0,      0 },
-{"luxc1",              "D,t(b)",       0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0,              I5_33|N55,      0,      0},
+{"luxc1",              "D,t(b)",       0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0,              I5_33|N55,      0,      I37},
+{"lwpc",               "s,-A",         0xec080000, 0xfc180000, WR_1|LM,                RD_pc,          I37,            0,      0 },
 {"lw",                 "t,o(b)",       0x8c000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
+{"lw",                 "s,-a(+R)",     0xec080000, 0xfc180000, WR_1|LM,                RD_pc,          I37,            0,      0 },
 {"lw",                 "t,A(b)",       0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1,             0,      0 },
-{"lwc0",               "E,o(b)",       0xc0000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
-{"lwc0",               "E,A(b)",       0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2 },
+{"lwc0",               "E,o(b)",       0xc0000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|I37 },
+{"lwc0",               "E,A(b)",       0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|I37 },
 {"lwc1",               "T,o(b)",       0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S,     0,              I1,             0,      0 },
 {"lwc1",               "E,o(b)",       0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S,     0,              I1,             0,      0 },
 {"lwc1",               "T,A(b)",       0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      0 },
 {"lwc1",               "E,A(b)",       0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      0 },
 {"l.s",                        "T,o(b)",       0xc4000000, 0xfc000000, WR_1|RD_3|CLD|FP_S,     0,              I1,             0,      0 }, /* lwc1 */
 {"l.s",                        "T,A(b)",       0,    (int) M_LWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      0 },
-{"lwc2",               "E,o(b)",       0xc8000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"lwc2",               "E,+:(d)",      0x49400000, 0xffe00000, RD_3|WR_C2|CLD,         0,              I37,            0,      0 },
+{"lwc2",               "E,o(b)",       0xc8000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
 {"lwc2",               "E,A(b)",       0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"lwc3",               "E,o(b)",       0xcc000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"lwc3",               "E,A(b)",       0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"lwl",                        "t,o(b)",       0x88000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
-{"lwl",                        "t,A(b)",       0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1,             0,      0 },
-{"lcache",             "t,o(b)",       0x88000000, 0xfc000000, WR_1|RD_3|LM,           0,              I2,             0,      0 }, /* same */
-{"lcache",             "t,A(b)",       0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I2,             0,      0 }, /* as lwl */
-{"lwr",                        "t,o(b)",       0x98000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
-{"lwr",                        "t,A(b)",       0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1,             0,      0 },
-{"flush",              "t,o(b)",       0x98000000, 0xfc000000, WR_1|RD_3|LM,           0,              I2,             0,      0 }, /* same */
-{"flush",              "t,A(b)",       0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I2,             0,      0 }, /* as lwr */
+{"lwc3",               "E,o(b)",       0xcc000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"lwc3",               "E,A(b)",       0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"lwl",                        "t,o(b)",       0x88000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      I37 },
+{"lwl",                        "t,A(b)",       0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"lcache",             "t,o(b)",       0x88000000, 0xfc000000, WR_1|RD_3|LM,           0,              I2,             0,      I37 }, /* same */
+{"lcache",             "t,A(b)",       0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I2,             0,      I37 }, /* as lwl */
+{"lwr",                        "t,o(b)",       0x98000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      I37 },
+{"lwr",                        "t,A(b)",       0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"flush",              "t,o(b)",       0x98000000, 0xfc000000, WR_1|RD_3|LM,           0,              I2,             0,      I37 }, /* same */
+{"flush",              "t,A(b)",       0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I2,             0,      I37 }, /* as lwr */
 {"fork",               "d,s,t",        0x7c000008, 0xfc0007ff, WR_1|RD_2|RD_3|TRAP,    0,              0,              MT32,   0 },
+{"lwupc",              "s,-A",         0xec100000, 0xfc180000, WR_1,                   RD_pc,          I69,            0,      0 },
 {"lwu",                        "t,o(b)",       0x9c000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      0 },
+{"lwu" ,               "s,-a(+R)",     0xec100000, 0xfc180000, WR_1,                   RD_pc,          I69,            0,      0 },
 {"lwu",                        "t,A(b)",       0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3,             0,      0 },
-{"lwxc1",              "D,t(b)",       0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_S,     0,          I4_33,          0,      0 },
+{"lwxc1",              "D,t(b)",       0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_S,     0,          I4_33,          0,      I37 },
 {"lwxs",               "d,t(b)",       0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3|LM,           0,         0,              SMT,    0 },
 {"macc",               "d,s,t",        0x00000028, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,      0,         N412,           0,      0 },
 {"macc",               "d,s,t",        0x00000158, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,      0,         N5,             0,      0 },
@@ -1245,18 +1316,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"maccus",             "d,s,t",        0x00000468, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,      0,         N412,           0,      0 },
 {"mad",                        "s,t",          0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,         P3,             0,      0 },
 {"madu",               "s,t",          0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,         P3,             0,      0 },
-{"madd.d",             "D,R,S,T",      0x4c000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,         I4_33,          0,      0 },
+{"madd.d",             "D,R,S,T",      0x4c000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,         I4_33,          0,      I37 },
 {"madd.d",             "D,S,T",        0x46200018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,         0,         IL2E,           0,      0 },
 {"madd.d",             "D,S,T",        0x72200018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,         0,         IL2F,           0,      0 },
-{"madd.s",             "D,R,S,T",      0x4c000020, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S,    0,         I4_33,          0,      0 },
+{"madd.s",             "D,R,S,T",      0x4c000020, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S,    0,         I4_33,          0,      I37 },
 {"madd.s",             "D,S,T",        0x46000018, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,         0,         IL2E,           0,      0 },
 {"madd.s",             "D,S,T",        0x72000018, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,         0,         IL2F,           0,      0 },
 {"madd.s",             "D,S,T",        0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,         0,         EE,             0,      0 },
-{"madd.ps",            "D,R,S,T",      0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,         I5_33,          0,      0 },
+{"madd.ps",            "D,R,S,T",      0x4c000026, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D,    0,         I5_33,          0,      I37 },
 {"madd.ps",            "D,S,T",        0x45600018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,         0,         IL2E,           0,      0 },
 {"madd.ps",            "D,S,T",        0x72c00018, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,         0,         IL2F,           0,      0 },
 {"madd",               "s,t",          0x0000001c, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,         L1,             0,      0 },
-{"madd",               "s,t",          0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,         I32|N55,        0,      0 },
+{"madd",               "s,t",          0x70000000, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,         I32|N55,        0,      I37 },
 {"madd",               "s,t",          0x70000000, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M,      0,         G1,             0,      0 },
 {"madd",               "7,s,t",        0x70000000, 0xfc00e7ff, RD_2|RD_3|MOD_a,             0,         0,              D32,    0 },
 {"madd",               "d,s,t",        0x70000000, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,         G1,             0,      0 },
@@ -1265,7 +1336,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"madda.s",            "S,T",          0x4600001e, 0xffe007ff, RD_1|RD_2|FP_S,              0,         EE,             0,      0 },
 {"maddp",              "s,t",          0x70000441, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,         0,              SMT,    0 },
 {"maddu",              "s,t",          0x0000001d, 0xfc00ffff, RD_1|RD_2|WR_HILO,           0,         L1,             0,      0 },
-{"maddu",              "s,t",          0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,         I32|N55,        0,      0 },
+{"maddu",              "s,t",          0x70000001, 0xfc00ffff, RD_1|RD_2|MOD_HILO,          0,         I32|N55,        0,      I37 },
 {"maddu",              "s,t",          0x70000001, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M,      0,         G1,             0,      0 },
 {"maddu",              "7,s,t",        0x70000001, 0xfc00e7ff, RD_2|RD_3|MOD_a,             0,         0,              D32,    0 },
 {"maddu",              "d,s,t",        0x70000001, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,         G1,             0,      0 },
@@ -1276,52 +1347,53 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"max.ob",             "D,S,Q",        0x48000007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"max.qh",             "X,Y,Q",        0x78200007, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"max.s",              "D,S,T",        0x46000028, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              EE,             0,      0 },
-{"mfbpc",              "t",            0x4000c000, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfdab",              "t",            0x4000c004, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfdabm",             "t",            0x4000c005, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfdvb",              "t",            0x4000c006, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfdvbm",             "t",            0x4000c007, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfiab",              "t",            0x4000c002, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfiabm",             "t",            0x4000c003, 0xffe0ffff, WR_1|RD_C0|LCD,         0,              EE,             0,      0 },
-{"mfpc",               "t,P",          0x4000c801, 0xffe0ffc1, WR_1|RD_C0|LCD,         0,              M1|N5|EE,       0,      0 },
-{"mfps",               "t,P",          0x4000c800, 0xffe0ffc1, WR_1|RD_C0|LCD,         0,              M1|N5|EE,       0,      0 },
+{"max.s",              "D,S,T",        0x4600001e, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"mfbpc",              "t",            0x4000c000, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfdab",              "t",            0x4000c004, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfdabm",             "t",            0x4000c005, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfdvb",              "t",            0x4000c006, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfdvbm",             "t",            0x4000c007, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfiab",              "t",            0x4000c002, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfiabm",             "t",            0x4000c003, 0xffe0ffff, WR_1|RD_C0|LC,          0,              EE,             0,      0 },
+{"mfpc",               "t,P",          0x4000c801, 0xffe0ffc1, WR_1|RD_C0|LC,          0,              M1|N5|EE,       0,      0 },
+{"mfps",               "t,P",          0x4000c800, 0xffe0ffc1, WR_1|RD_C0|LC,          0,              M1|N5|EE,       0,      0 },
 {"mftacx",             "d",            0x41020021, 0xffff07ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mftacx",             "d,*",          0x41020021, 0xfff307ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
-{"mftc0",              "d,+t",         0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LCD,    0,              0,              MT32,   0 },
-{"mftc0",              "d,E,H",        0x41000000, 0xffe007f8, WR_1|RD_C0|TRAP|LCD,    0,              0,              MT32,   0 },
-{"mftc1",              "d,T",          0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_S, 0,             0,              MT32,   0 },
-{"mftc1",              "d,E",          0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_S, 0,             0,              MT32,   0 },
-{"mftc2",              "d,E",          0x41000024, 0xffe007ff, WR_1|RD_C2|TRAP|LCD,    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"mftc0",              "d,+t",         0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LC    0,              0,              MT32,   0 },
+{"mftc0",              "d,E,H",        0x41000000, 0xffe007f8, WR_1|RD_C0|TRAP|LC    0,              0,              MT32,   0 },
+{"mftc1",              "d,T",          0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0,              0,              MT32,   0 },
+{"mftc1",              "d,E",          0x41000022, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_S, 0,              0,              MT32,   0 },
+{"mftc2",              "d,E",          0x41000024, 0xffe007ff, WR_1|RD_C2|TRAP|LC    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"mftdsp",             "d",            0x41100021, 0xffff07ff, WR_1|TRAP,              0,              0,              MT32,   0 },
 {"mftgpr",             "d,t",          0x41000020, 0xffe007ff, WR_1|RD_2|TRAP,         0,              0,              MT32,   0 },
-{"mfthc1",             "d,T",          0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_D, 0,             0,              MT32,   0 },
-{"mfthc1",             "d,E",          0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LCD|FP_D, 0,             0,              MT32,   0 },
-{"mfthc2",             "d,E",          0x41000034, 0xffe007ff, WR_1|RD_C2|TRAP|LCD,    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"mfthc1",             "d,T",          0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, 0,              0,              MT32,   0 },
+{"mfthc1",             "d,E",          0x41000032, 0xffe007ff, WR_1|RD_2|TRAP|LC|FP_D, 0,              0,              MT32,   0 },
+{"mfthc2",             "d,E",          0x41000034, 0xffe007ff, WR_1|RD_C2|TRAP|LC    0,              0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"mfthi",              "d",            0x41010021, 0xffff07ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mfthi",              "d,*",          0x41010021, 0xfff307ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mftlo",              "d",            0x41000021, 0xffff07ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mftlo",              "d,*",          0x41000021, 0xfff307ff, WR_1|RD_a|TRAP,         0,              0,              MT32,   0 },
 {"mftr",               "d,t,!,H,$",    0x41000000, 0xffe007c8, WR_1|TRAP,              0,              0,              MT32,   0 },
-{"mfc0",               "t,G",          0x40000000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I1,             0,      0 },
-{"mfc0",               "t,G,H",        0x40000000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I32,            0,      0 },
-{"mfgc0",              "t,G",          0x40600000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              0,              IVIRT,  0 },
-{"mfgc0",              "t,G,H",        0x40600000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              0,              IVIRT,  0 },
-{"mfhc0",              "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I33,            XPA,    0 },
-{"mfhc0",              "t,G,H",        0x40400000, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I33,            XPA,    0 },
-{"mfhgc0",             "t,G",          0x40600400, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I33,            IVIRT|XPA,      0 },
-{"mfhgc0",             "t,G,H",        0x40600400, 0xffe007f8, WR_1|RD_C0|LCD,         0,              I33,            IVIRT|XPA,      0 },
-{"mfc1",               "t,S",          0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S,     0,              I1,             0,      0 },
-{"mfc1",               "t,G",          0x44000000, 0xffe007ff, WR_1|RD_2|LCD|FP_S,     0,              I1,             0,      0 },
-{"mfhc1",              "t,S",          0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D,     0,              I33,            0,      0 },
-{"mfhc1",              "t,G",          0x44600000, 0xffe007ff, WR_1|RD_2|LCD|FP_D,     0,              I33,            0,      0 },
+{"mfc0",               "t,G",          0x40000000, 0xffe007ff, WR_1|RD_C0|LC         0,              I1,             0,      0 },
+{"mfc0",               "t,G,H",        0x40000000, 0xffe007f8, WR_1|RD_C0|LC         0,              I32,            0,      0 },
+{"mfgc0",              "t,G",          0x40600000, 0xffe007ff, WR_1|RD_C0|LC         0,              0,              IVIRT,  0 },
+{"mfgc0",              "t,G,H",        0x40600000, 0xffe007f8, WR_1|RD_C0|LC         0,              0,              IVIRT,  0 },
+{"mfhc0",              "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LC         0,              I33,            XPA,    0 },
+{"mfhc0",              "t,G,H",        0x40400000, 0xffe007f8, WR_1|RD_C0|LC         0,              I33,            XPA,    0 },
+{"mfhgc0",             "t,G",          0x40600400, 0xffe007ff, WR_1|RD_C0|LC         0,              I33,            IVIRT|XPA,      0 },
+{"mfhgc0",             "t,G,H",        0x40600400, 0xffe007f8, WR_1|RD_C0|LC         0,              I33,            IVIRT|XPA,      0 },
+{"mfc1",               "t,S",          0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S,      0,              I1,             0,      0 },
+{"mfc1",               "t,G",          0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S,      0,              I1,             0,      0 },
+{"mfhc1",              "t,S",          0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D,      0,              I33,            0,      0 },
+{"mfhc1",              "t,G",          0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D,      0,              I33,            0,      0 },
 /* mfc2 is at the bottom of the table.  */
 /* mfhc2 is at the bottom of the table.  */
 /* mfc3 is at the bottom of the table.  */
-{"mfdr",               "t,G",          0x7000003d, 0xffe007ff, WR_1|RD_C0|LCD,         0,              N5,             0,      0 },
-{"mfhi",               "d",            0x00000010, 0xffff07ff, WR_1|RD_HI,             0,              I1,             0,      0 },
+{"mfdr",               "t,G",          0x7000003d, 0xffe007ff, WR_1|RD_C0|LC         0,              N5,             0,      0 },
+{"mfhi",               "d",            0x00000010, 0xffff07ff, WR_1|RD_HI,             0,              I1,             0,      I37 },
 {"mfhi",               "d,9",          0x00000010, 0xff9f07ff, WR_1|RD_HI,             0,              0,              D32,    0 },
 {"mfhi1",              "d",            0x70000010, 0xffff07ff, WR_1|RD_HI,             0,              EE,             0,      0 },
-{"mflo",               "d",            0x00000012, 0xffff07ff, WR_1|RD_LO,             0,              I1,             0,      0 },
+{"mflo",               "d",            0x00000012, 0xffff07ff, WR_1|RD_LO,             0,              I1,             0,      I37 },
 {"mflo",               "d,9",          0x00000012, 0xff9f07ff, WR_1|RD_LO,             0,              0,              D32,    0 },
 {"mflo1",              "d",            0x70000012, 0xffff07ff, WR_1|RD_LO,             0,              EE,             0,      0 },
 {"mflhxu",             "d",            0x00000052, 0xffff07ff, WR_1|MOD_HILO,          0,              0,              SMT,    0 },
@@ -1331,37 +1403,38 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"min.ob",             "D,S,Q",        0x48000006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"min.qh",             "X,Y,Q",        0x78200006, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"min.s",              "D,S,T",        0x46000029, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              EE,             0,      0 },
+{"min.s",              "D,S,T",        0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
 {"mov.d",              "D,S",          0x46200006, 0xffff003f, WR_1|RD_2|FP_D,         0,              I1,             0,      SF },
 {"mov.s",              "D,S",          0x46000006, 0xffff003f, WR_1|RD_2|FP_S,         0,              I1,             0,      0 },
-{"mov.ps",             "D,S",          0x46c00006, 0xffff003f, WR_1|RD_2|FP_D,         0,              I5_33|IL2F,     0,      0 },
+{"mov.ps",             "D,S",          0x46c00006, 0xffff003f, WR_1|RD_2|FP_D,         0,              I5_33|IL2F,     0,      I37 },
 {"mov.ps",             "D,S",          0x45600006, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2E,           0,      0 },
-{"movf",               "d,s,N",        0x00000001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0,           I4_32,          0,      0  },
-{"movf.d",             "D,S,N",        0x46200011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I4_32,          0,      0 },
+{"movf",               "d,s,N",        0x00000001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0,           I4_32,          0,      I37  },
+{"movf.d",             "D,S,N",        0x46200011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I4_32,          0,      I37 },
 {"movf.l",             "D,S,N",        0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              SB1,            MX,     0 },
 {"movf.l",             "X,Y,N",        0x46a00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              SB1,            MX,     0 },
-{"movf.s",             "D,S,N",        0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,              I4_32,          0,      0 },
-{"movf.ps",            "D,S,N",        0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I5_33,          0,      0 },
-{"movn",               "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I4_32|IL2E|IL2F|EE, 0,  0 },
+{"movf.s",             "D,S,N",        0x46000011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"movf.ps",            "D,S,N",        0x46c00011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"movn",               "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I4_32|IL2E|IL2F|EE, 0,  I37 },
 {"movnz",              "d,v,t",        0x0000000b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E|IL2F|IL3A, 0,      0 },
 {"ffc",                        "d,v",          0x0000000b, 0xfc1f07ff, WR_1|RD_2,              0,              L1,             0,      0 },
-{"movn.d",             "D,S,t",        0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I4_32,          0,      0 },
+{"movn.d",             "D,S,t",        0x46200013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I4_32,          0,      I37 },
 {"movn.l",             "D,S,t",        0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"movn.l",             "X,Y,t",        0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
-{"movn.s",             "D,S,t",        0x46000013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I4_32,          0,      0 },
-{"movn.ps",            "D,S,t",        0x46c00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      0 },
-{"movt",               "d,s,N",        0x00010001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0,           I4_32,          0,      0 },
-{"movt.d",             "D,S,N",        0x46210011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I4_32,          0,      0 },
+{"movn.s",             "D,S,t",        0x46000013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I4_32,          0,      I37 },
+{"movn.ps",            "D,S,t",        0x46c00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      I37 },
+{"movt",               "d,s,N",        0x00010001, 0xfc0307ff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0,           I4_32,          0,      I37 },
+{"movt.d",             "D,S,N",        0x46210011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I4_32,          0,      I37 },
 {"movt.l",             "D,S,N",        0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              SB1,            MX,     0 },
 {"movt.l",             "X,Y,N",        0x46a10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              SB1,            MX,     0 },
-{"movt.s",             "D,S,N",        0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,              I4_32,          0,      0 },
-{"movt.ps",            "D,S,N",        0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I5_33,          0,      0 },
-{"movz",               "d,v,t",        0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I4_32|IL2E|IL2F|EE, 0,  0 },
+{"movt.s",             "D,S,N",        0x46010011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_S,   0,              I4_32,          0,      I37 },
+{"movt.ps",            "D,S,N",        0x46c10011, 0xffe3003f, WR_1|RD_2|RD_CC|FP_D,   0,              I5_33,          0,      I37 },
+{"movz",               "d,v,t",        0x0000000a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I4_32|IL2E|IL2F|EE, 0,  I37 },
 {"ffs",                        "d,v",          0x0000000a, 0xfc1f07ff, WR_1|RD_2,              0,              L1,             0,      0 },
-{"movz.d",             "D,S,t",        0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I4_32,          0,      0 },
+{"movz.d",             "D,S,t",        0x46200012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I4_32,          0,      I37 },
 {"movz.l",             "D,S,t",        0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"movz.l",             "X,Y,t",        0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
-{"movz.s",             "D,S,t",        0x46000012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I4_32,          0,      0 },
-{"movz.ps",            "D,S,t",        0x46c00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      0 },
+{"movz.s",             "D,S,t",        0x46000012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I4_32,          0,      I37 },
+{"movz.ps",            "D,S,t",        0x46c00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      I37 },
 {"msac",               "d,s,t",        0x000001d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              N5,             0,      0 },
 {"msacu",              "d,s,t",        0x000001d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              N5,             0,      0 },
 {"msachi",             "d,s,t",        0x000003d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              N5,             0,      0 },
@@ -1373,77 +1446,83 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msgld",              "t",            0,    (int) M_MSGLD_T,  INSN_MACRO,             0,              XLR,            0,      0 },
 {"msgwait",            "",             0,    (int) M_MSGWAIT,  INSN_MACRO,             0,              XLR,            0,      0 },
 {"msgwait",            "t",            0,    (int) M_MSGWAIT_T,INSN_MACRO,             0,              XLR,            0,      0 },
-{"msub.d",             "D,R,S,T",      0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I4_33,          0,      0 },
+{"msub.d",             "D,R,S,T",      0x4c000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I4_33,          0,      I37 },
 {"msub.d",             "D,S,T",        0x46200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"msub.d",             "D,S,T",        0x72200019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F,           0,      0 },
-{"msub.s",             "D,R,S,T",      0x4c000028, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,            I4_33,          0,      0 },
+{"msub.s",             "D,R,S,T",      0x4c000028, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,            I4_33,          0,      I37 },
 {"msub.s",             "D,S,T",        0x46000019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
 {"msub.s",             "D,S,T",        0x72000019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F,           0,      0 },
 {"msub.s",             "D,S,T",        0x4600001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              EE,             0,      0 },
-{"msub.ps",            "D,R,S,T",      0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I5_33,          0,      0 },
+{"msub.ps",            "D,R,S,T",      0x4c00002e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I5_33,          0,      I37 },
 {"msub.ps",            "D,S,T",        0x45600019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"msub.ps",            "D,S,T",        0x72c00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F,           0,      0 },
 {"msub",               "s,t",          0x0000001e, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              L1,             0,      0 },
-{"msub",               "s,t",          0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              I32|N55,        0,      0 },
+{"msub",               "s,t",          0x70000004, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              I32|N55,        0,      I37 },
 {"msub",               "7,s,t",        0x70000004, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,              D32,    0 },
 {"msuba.s",            "S,T",          0x4600001f, 0xffe007ff, RD_1|RD_2|FP_S,         0,              EE,             0,      0 },
 {"msubu",              "s,t",          0x0000001f, 0xfc00ffff, RD_1|RD_2|WR_HILO,      0,              L1,             0,      0 },
-{"msubu",              "s,t",          0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              I32|N55,        0,      0 },
+{"msubu",              "s,t",          0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              I32|N55,        0,      I37 },
 {"msubu",              "7,s,t",        0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,              D32,    0 },
-{"mtbpc",              "t",            0x4080c000, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtdab",              "t",            0x4080c004, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtdabm",             "t",            0x4080c005, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtdvb",              "t",            0x4080c006, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtdvbm",             "t",            0x4080c007, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtiab",              "t",            0x4080c002, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtiabm",             "t",            0x4080c003, 0xffe0ffff, RD_1|WR_C0|COD,         0,              EE,             0,      0 },
-{"mtpc",               "t,P",          0x4080c801, 0xffe0ffc1, RD_1|WR_C0|COD,         0,              M1|N5|EE,       0,      0 },
-{"mtps",               "t,P",          0x4080c800, 0xffe0ffc1, RD_1|WR_C0|COD,         0,              M1|N5|EE,       0,      0 },
-{"mtc0",               "t,G",          0x40800000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              I1,             0,      0 },
-{"mtc0",               "t,G,H",        0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I32,            0,      0 },
-{"mtgc0",              "t,G",          0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              0,              IVIRT,  0 },
-{"mtgc0",              "t,G,H",        0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              0,              IVIRT,  0 },
-{"mthc0",              "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              I33,            XPA,    0 },
-{"mthc0",              "t,G,H",        0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I33,            XPA,    0 },
-{"mthgc0",             "t,G",          0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|COD,   0,              I33,            IVIRT|XPA,      0 },
-{"mthgc0",             "t,G,H",        0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|COD,   0,              I33,            IVIRT|XPA,      0 },
-{"mtc1",               "t,S",          0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S,     0,              I1,             0,      0 },
-{"mtc1",               "t,G",          0x44800000, 0xffe007ff, RD_1|WR_2|COD|FP_S,     0,              I1,             0,      0 },
-{"mthc1",              "t,S",          0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D,     0,              I33,            0,      0 },
-{"mthc1",              "t,G",          0x44e00000, 0xffe007ff, RD_1|WR_2|COD|FP_D,     0,              I33,            0,      0 },
+{"mtbpc",              "t",            0x4080c000, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtdab",              "t",            0x4080c004, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtdabm",             "t",            0x4080c005, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtdvb",              "t",            0x4080c006, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtdvbm",             "t",            0x4080c007, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtiab",              "t",            0x4080c002, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtiabm",             "t",            0x4080c003, 0xffe0ffff, RD_1|WR_C0|CM,          0,              EE,             0,      0 },
+{"mtpc",               "t,P",          0x4080c801, 0xffe0ffc1, RD_1|WR_C0|CM,          0,              M1|N5|EE,       0,      0 },
+{"mtps",               "t,P",          0x4080c800, 0xffe0ffc1, RD_1|WR_C0|CM,          0,              M1|N5|EE,       0,      0 },
+{"mtc0",               "t,G",          0x40800000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I1,             0,      0 },
+{"mtc0",               "t,G,H",        0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I32,            0,      0 },
+{"mtgc0",              "t,G",          0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              0,              IVIRT,  0 },
+{"mtgc0",              "t,G,H",        0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,   0,               0,              IVIRT,  0 },
+{"mthc0",              "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I33,            XPA,    0 },
+{"mthc0",              "t,G,H",        0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I33,            XPA,    0 },
+{"mthgc0",             "t,G",          0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I33,            IVIRT|XPA,      0 },
+{"mthgc0",             "t,G,H",        0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I33,            IVIRT|XPA,      0 },
+{"mtc1",               "t,S",          0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S,      0,              I1,             0,      0 },
+{"mtc1",               "t,G",          0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S,      0,              I1,             0,      0 },
+{"mthc1",              "t,S",          0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,      0,              I33,            0,      0 },
+{"mthc1",              "t,G",          0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,      0,              I33,            0,      0 },
 /* mtc2 is at the bottom of the table.  */
 /* mthc2 is at the bottom of the table.  */
 /* mtc3 is at the bottom of the table.  */
-{"mtdr",               "t,G",          0x7080003d, 0xffe007ff, RD_1|WR_C0|COD,         0,              N5,             0,      0 },
-{"mthi",               "s",            0x00000011, 0xfc1fffff, RD_1|WR_HI,             0,              I1,             0,      0 },
+{"mtdr",               "t,G",          0x7080003d, 0xffe007ff, RD_1|WR_C0|CM,          0,              N5,             0,      0 },
+{"mthi",               "s",            0x00000011, 0xfc1fffff, RD_1|WR_HI,             0,              I1,             0,      I37 },
 {"mthi",               "s,7",          0x00000011, 0xfc1fe7ff, RD_1|WR_HI,             0,              0,              D32,    0 },
 {"mthi1",              "s",            0x70000011, 0xfc1fffff, RD_1|WR_HI,             0,              EE,             0,      0 },
-{"mtlo",               "s",            0x00000013, 0xfc1fffff, RD_1|WR_LO,             0,              I1,             0,      0 },
+{"mtlo",               "s",            0x00000013, 0xfc1fffff, RD_1|WR_LO,             0,              I1,             0,      I37 },
 {"mtlo",               "s,7",          0x00000013, 0xfc1fe7ff, RD_1|WR_LO,             0,              0,              D32,    0 },
 {"mtlo1",              "s",            0x70000013, 0xfc1fffff, RD_1|WR_LO,             0,              EE,             0,      0 },
 {"mtlhx",              "s",            0x00000053, 0xfc1fffff, RD_1|MOD_HILO,          0,              0,              SMT,    0 },
 {"mtcr",               "t,s",          0x70000019, 0xfc00ffff, RD_1|RD_2,              0,              XLR,            0,      0 },
 {"mtm0",               "s",            0x70000008, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtm0",               "s,t",          0x70000008, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtm1",               "s",            0x7000000c, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtm1",               "s,t",          0x7000000c, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtm2",               "s",            0x7000000d, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtm2",               "s,t",          0x7000000d, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtp0",               "s",            0x70000009, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtp0",               "s,t",          0x70000009, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtp1",               "s",            0x7000000a, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtp1",               "s,t",          0x7000000a, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtp2",               "s",            0x7000000b, 0xfc1fffff, RD_1,                   0,              IOCT,           0,      0 },
+{"mtp2",               "s,t",          0x7000000b, 0xfc00ffff, RD_1|RD_2,              0,              IOCT3,          0,      0 },
 {"mtsa",               "s",            0x00000029, 0xfc1fffff, RD_1,                   0,              EE,             0,      0 },
 {"mtsab",              "s,j",          0x04180000, 0xfc1f0000, RD_1,                   0,              EE,             0,      0 },
 {"mtsah",              "s,j",          0x04190000, 0xfc1f0000, RD_1,                   0,              EE,             0,      0 },
-{"mttc0",              "t,G",          0x41800000, 0xffe007ff, RD_1|WR_C0|WR_CC|TRAP|COD, 0,           0,              MT32,   0 },
-{"mttc0",              "t,G,H",        0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|COD, 0,           0,              MT32,   0 },
-{"mttc1",              "t,S",          0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_S, 0,             0,              MT32,   0 },
-{"mttc1",              "t,G",          0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_S, 0,             0,              MT32,   0 },
-{"mttc2",              "t,g",          0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|COD, 0,           0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"mttc0",              "t,G",          0x41800000, 0xffe007ff, RD_1|WR_C0|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
+{"mttc0",              "t,G,H",        0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|CM, 0,            0,              MT32,   0 },
+{"mttc1",              "t,S",          0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0,              0,              MT32,   0 },
+{"mttc1",              "t,G",          0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0,              0,              MT32,   0 },
+{"mttc2",              "t,g",          0x41800024, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"mttacx",             "t",            0x41801021, 0xffe0ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttacx",             "t,&",          0x41801021, 0xffe09fff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttdsp",             "t",            0x41808021, 0xffe0ffff, RD_1|TRAP,              0,              0,              MT32,   0 },
 {"mttgpr",             "t,d",          0x41800020, 0xffe007ff, RD_1|WR_2|TRAP,         0,              0,              MT32,   0 },
-{"mtthc1",             "t,S",          0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_D, 0,             0,              MT32,   0 },
-{"mtthc1",             "t,G",          0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|COD|FP_D, 0,             0,              MT32,   0 },
-{"mtthc2",             "t,g",          0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|COD, 0,           0,              MT32,   IOCT|IOCTP|IOCT2 },
+{"mtthc1",             "t,S",          0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0,              0,              MT32,   0 },
+{"mtthc1",             "t,G",          0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0,              0,              MT32,   0 },
+{"mtthc2",             "t,g",          0x41800034, 0xffe007ff, RD_1|WR_C2|WR_CC|TRAP|CM, 0,            0,              MT32,   IOCT|IOCTP|IOCT2 },
 {"mtthi",              "t",            0x41800821, 0xffe0ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mtthi",              "t,&",          0x41800821, 0xffe09fff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
 {"mttlo",              "t",            0x41800021, 0xffe0ffff, RD_1|WR_a|TRAP,         0,              0,              MT32,   0 },
@@ -1453,13 +1532,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mul.s",              "D,V,T",        0x46000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"mul.ob",             "X,Y,Q",        0x78000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"mul.ob",             "D,S,Q",        0x48000030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
-{"mul.ps",             "D,V,T",        0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33|IL2F,     0,      0 },
+{"mul.ps",             "D,V,T",        0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33|IL2F,     0,      I37 },
 {"mul.ps",             "D,V,T",        0x45600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"mul.qh",             "X,Y,Q",        0x78200030, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
-{"mul",                        "d,v,t",        0x70000002, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              I32|P3|N55,     0,      0},
+{"muh",                        "d,v,t",        0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I37,            0,      0},
+{"muhu",               "d,v,t",        0x000000d9, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I37,            0,      0},
+{"mul",                        "d,v,t",        0x00000098, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I37,            0,      0},
+{"mul",                        "d,v,t",        0x70000002, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              I32|P3|N55,     0,      I37},
 {"mul",                        "d,s,t",        0x00000058, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              N54,            0,      0 },
-{"mul",                        "d,v,t",        0,    (int) M_MUL,      INSN_MACRO,             0,              I1,             0,      0 },
-{"mul",                        "d,v,I",        0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1,             0,      0 },
+{"mul",                        "d,v,t",        0,    (int) M_MUL,      INSN_MACRO,             0,              I1,             0,      I37 },
+{"mul",                        "d,v,I",        0,    (int) M_MUL_I,    INSN_MACRO,             0,              I1,             0,      I37 },
 {"mula.ob",            "Y,Q",          0x78000033, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        SB1,            MX,     0 },
 {"mula.ob",            "S,Q",          0x48000033, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        N54,            0,      0 },
 {"mula.qh",            "Y,Q",          0x78200033, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        0,              MX,     0 },
@@ -1469,10 +1551,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mull.ob",            "Y,Q",          0x78000433, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        SB1,            MX,     0 },
 {"mull.ob",            "S,Q",          0x48000433, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        N54,            0,      0 },
 {"mull.qh",            "Y,Q",          0x78200433, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        0,              MX,     0 },
-{"mulo",               "d,v,t",        0,    (int) M_MULO,     INSN_MACRO,             0,              I1,             0,      0 },
-{"mulo",               "d,v,I",        0,    (int) M_MULO_I,   INSN_MACRO,             0,              I1,             0,      0 },
-{"mulou",              "d,v,t",        0,    (int) M_MULOU,    INSN_MACRO,             0,              I1,             0,      0 },
-{"mulou",              "d,v,I",        0,    (int) M_MULOU_I,  INSN_MACRO,             0,              I1,             0,      0 },
+{"mulo",               "d,v,t",        0,    (int) M_MULO,     INSN_MACRO,             0,              I1,             0,      I37 },
+{"mulo",               "d,v,I",        0,    (int) M_MULO_I,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"mulou",              "d,v,t",        0,    (int) M_MULOU,    INSN_MACRO,             0,              I1,             0,      I37 },
+{"mulou",              "d,v,I",        0,    (int) M_MULOU_I,  INSN_MACRO,             0,              I1,             0,      I37 },
 {"mulr.ps",            "D,S,T",        0x46c0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              M3D,    0 },
 {"muls",               "d,s,t",        0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              N5,             0,      0 },
 {"mulsu",              "d,s,t",        0x000000d9, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              N5,             0,      0 },
@@ -1484,40 +1566,41 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mulsl.ob",           "Y,Q",          0x78000432, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        SB1,            MX,     0 },
 {"mulsl.ob",           "S,Q",          0x48000432, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        N54,            0,      0 },
 {"mulsl.qh",           "Y,Q",          0x78200432, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        0,              MX,     0 },
-{"mult",               "s,t",          0x00000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,              I1,             0,      0 },
+{"mult",               "s,t",          0x00000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,              I1,             0,      I37 },
 {"mult",               "7,s,t",        0x00000018, 0xfc00e7ff, RD_2|RD_3|WR_a,         0,              0,              D32,    0 },
 {"mult",               "d,s,t",        0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,         G1,             0,      0 },
 {"mult1",              "s,t",          0x70000018, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,              EE,             0,      0 },
 {"mult1",              "d,s,t",        0x70000018, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,         EE,             0,      0 },
 {"multp",              "s,t",          0x00000459, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              0,              SMT,    0 },
-{"multu",              "s,t",          0x00000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,              I1,             0,      0 },
+{"multu",              "s,t",          0x00000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,              I1,             0,      I37 },
 {"multu",              "7,s,t",        0x00000019, 0xfc00e7ff, RD_2|RD_3|WR_a,         0,              0,              D32,    0 },
 {"multu",              "d,s,t",        0x00000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,         G1,             0,      0 },
 {"multu1",             "s,t",          0x70000019, 0xfc00ffff, RD_1|RD_2|WR_HILO|IS_M, 0,              EE,             0,      0 },
 {"multu1",             "d,s,t",        0x70000019, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO|IS_M, 0,         EE,             0,      0 },
+{"mulu",               "d,v,t",        0x00000099, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I37,            0,      0},
 {"mulu",               "d,s,t",        0x00000059, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              N5,             0,      0 },
 {"neg",                        "d,w",          0x00000022, 0xffe007ff, WR_1|RD_2,              0,              I1,             0,      0 }, /* sub 0 */
 {"negu",               "d,w",          0x00000023, 0xffe007ff, WR_1|RD_2,              0,              I1,             0,      0 }, /* subu 0 */
 {"neg.d",              "D,V",          0x46200007, 0xffff003f, WR_1|RD_2|FP_D,         0,              I1,             0,      SF },
 {"neg.s",              "D,V",          0x46000007, 0xffff003f, WR_1|RD_2|FP_S,         0,              I1,             0,      0 },
-{"neg.ps",             "D,V",          0x46c00007, 0xffff003f, WR_1|RD_2|FP_D,         0,              I5_33|IL2F,     0,      0 },
+{"neg.ps",             "D,V",          0x46c00007, 0xffff003f, WR_1|RD_2|FP_D,         0,              I5_33|IL2F,     0,      I37 },
 {"neg.ps",             "D,V",          0x45600007, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2E,           0,      0 },
-{"nmadd.d",            "D,R,S,T",      0x4c000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I4_33,          0,      0 },
+{"nmadd.d",            "D,R,S,T",      0x4c000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I4_33,          0,      I37 },
 {"nmadd.d",            "D,S,T",        0x4620001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"nmadd.d",            "D,S,T",        0x7220001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F,           0,      0 },
-{"nmadd.s",            "D,R,S,T",      0x4c000030, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,            I4_33,          0,      0 },
+{"nmadd.s",            "D,R,S,T",      0x4c000030, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,            I4_33,          0,      I37 },
 {"nmadd.s",            "D,S,T",        0x4600001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
 {"nmadd.s",            "D,S,T",        0x7200001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F,           0,      0 },
-{"nmadd.ps",           "D,R,S,T",      0x4c000036, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I5_33,          0,      0 },
+{"nmadd.ps",           "D,R,S,T",      0x4c000036, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I5_33,          0,      I37 },
 {"nmadd.ps",           "D,S,T",        0x4560001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"nmadd.ps",           "D,S,T",        0x72c0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F,           0,      0 },
-{"nmsub.d",            "D,R,S,T",      0x4c000039, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I4_33,          0,      0 },
+{"nmsub.d",            "D,R,S,T",      0x4c000039, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I4_33,          0,      I37 },
 {"nmsub.d",            "D,S,T",        0x4620001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"nmsub.d",            "D,S,T",        0x7220001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F,           0,      0 },
-{"nmsub.s",            "D,R,S,T",      0x4c000038, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,            I4_33,          0,      0 },
+{"nmsub.s",            "D,R,S,T",      0x4c000038, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0,            I4_33,          0,      I37 },
 {"nmsub.s",            "D,S,T",        0x4600001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
 {"nmsub.s",            "D,S,T",        0x7200001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F,           0,      0 },
-{"nmsub.ps",           "D,R,S,T",      0x4c00003e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I5_33,          0,      0 },
+{"nmsub.ps",           "D,R,S,T",      0x4c00003e, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0,            I5_33,          0,      I37 },
 {"nmsub.ps",           "D,S,T",        0x4560001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"nmsub.ps",           "D,S,T",        0x72c0001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F,           0,      0 },
 /* nop is at the start of the table.  */
@@ -1582,8 +1665,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"pickt.qh",           "X,Y,Q",        0x78200003, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"pinteh",             "d,s,t",        0x700002a9, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"pinth",              "d,s,t",        0x70000289, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
-{"pll.ps",             "D,V,T",        0x46c0002c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      0 },
-{"plu.ps",             "D,V,T",        0x46c0002d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      0 },
+{"pll.ps",             "D,V,T",        0x46c0002c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      I37 },
+{"plu.ps",             "D,V,T",        0x46c0002d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      I37 },
 {"plzcw",              "d,s",          0x70000004, 0xfc1f07ff, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"pmaddh",             "d,s,t",        0x70000409, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0,              MMI,            0,      0 },
 {"pmadduw",            "d,s,t",        0x70000029, 0xfc0007ff, WR_1|RD_2|RD_3|MOD_HILO, 0,             MMI,            0,      0 },
@@ -1625,8 +1708,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"psubuw",             "d,s,t",        0x70000468, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"pxor",               "d,s,t",        0x700004c9, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
   /* pref and prefx are at the start of the table.  */
-{"pul.ps",             "D,V,T",        0x46c0002e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      0 },
-{"puu.ps",             "D,V,T",        0x46c0002f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      0 },
+{"pul.ps",             "D,V,T",        0x46c0002e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      I37 },
+{"puu.ps",             "D,V,T",        0x46c0002f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33,          0,      I37 },
 {"pperm",              "s,t",          0x70000481, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              0,              SMT,    0 },
 {"qfsrv",              "d,s,t",        0x700006e8, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"qmac.00",            "s,t",          0x70000412, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,              IOCT2,          0,      0 },
@@ -1655,12 +1738,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"recip2.d",           "D,S,T",        0x4620001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              M3D,    0 },
 {"recip2.ps",          "D,S,T",        0x46c0001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              M3D,    0 },
 {"recip2.s",           "D,S,T",        0x4600001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              M3D,    0 },
-{"rem",                        "z,s,t",        0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I1,             0,      0 },
-{"rem",                        "d,v,t",        0,    (int) M_REM_3,    INSN_MACRO,             0,              I1,             0,      0 },
-{"rem",                        "d,v,I",        0,    (int) M_REM_3I,   INSN_MACRO,             0,              I1,             0,      0 },
-{"remu",               "z,s,t",        0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO,      0,              I1,             0,      0 },
-{"remu",               "d,v,t",        0,    (int) M_REMU_3,   INSN_MACRO,             0,              I1,             0,      0 },
-{"remu",               "d,v,I",        0,    (int) M_REMU_3I,  INSN_MACRO,             0,              I1,             0,      0 },
+{"rem",                        "z,s,t",        0x0000001a, 0xfc00ffff, RD_2|RD_3|WR_HILO,      INSN2_ALIAS,    I1,             0,      I37 },
+{"rem",                        "d,v,t",        0,    (int) M_REM_3,    INSN_MACRO,             0,              I1,             0,      I37 },
+{"rem",                        "d,v,I",        0,    (int) M_REM_3I,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"remu",               "z,s,t",        0x0000001b, 0xfc00ffff, RD_2|RD_3|WR_HILO,      INSN2_ALIAS,    I1,             0,      I37 },
+{"remu",               "d,v,t",        0,    (int) M_REMU_3,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"remu",               "d,v,I",        0,    (int) M_REMU_3I,  INSN_MACRO,             0,              I1,             0,      I37 },
 {"rdhwr",              "t,K",          0x7c00003b, 0xffe007ff, WR_1,                   0,              I33,            0,      0 },
 {"rdpgpr",             "d,w",          0x41400000, 0xffe007ff, WR_1,                   0,              I33,            0,      0 },
 /* rfe is moved below as it now conflicts with tlbgp */
@@ -1705,9 +1788,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"saad",               "t,(b)",        0x70000019, 0xfc00ffff, RD_1|RD_2|SM,           0,              IOCTP,          0,      0 },
 {"sb",                 "t,o(b)",       0xa0000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      0 },
 {"sb",                 "t,A(b)",       0,    (int) M_SB_AB,    INSN_MACRO,             0,              I1,             0,      0 },
-{"sc",                 "t,o(b)",       0xe0000000, 0xfc000000, MOD_1|RD_3|SM,          0,              I2,             0,      EE },
+{"sc",                 "t,+j(b)",      0x7c000026, 0xfc00007f, MOD_1|RD_3|SM,          0,              I37,            0,      0 },
+{"sc",                 "t,o(b)",       0xe0000000, 0xfc000000, MOD_1|RD_3|SM,          0,              I2,             0,      EE|I37 },
 {"sc",                 "t,A(b)",       0,    (int) M_SC_AB,    INSN_MACRO,             0,              I2,             0,      EE },
-{"scd",                        "t,o(b)",       0xf0000000, 0xfc000000, MOD_1|RD_3|SM,          0,              I3,             0,      EE },
+{"scd",                        "t,+j(b)",      0x7c000027, 0xfc00007f, MOD_1|RD_3|SM,          0,              I69,            0,      0 },
+{"scd",                        "t,o(b)",       0xf0000000, 0xfc000000, MOD_1|RD_3|SM,          0,              I3,             0,      EE|I69 },
 {"scd",                        "t,A(b)",       0,    (int) M_SCD_AB,   INSN_MACRO,             0,              I3,             0,      EE },
 /* The macro has to be first to handle o32 correctly.  */
 {"sd",                 "t,A(b)",       0,    (int) M_SD_AB,    INSN_MACRO,             0,              I1,             0,      0 },
@@ -1715,23 +1800,26 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sdbbp",              "",             0x0000000e, 0xffffffff, TRAP,                   0,              G2,             0,      0 },
 {"sdbbp",              "c",            0x0000000e, 0xfc00ffff, TRAP,                   0,              G2,             0,      0 },
 {"sdbbp",              "c,q",          0x0000000e, 0xfc00003f, TRAP,                   0,              G2,             0,      0 },
-{"sdbbp",              "",             0x7000003f, 0xffffffff, TRAP,                   0,              I32,            0,      0 },
-{"sdbbp",              "B",            0x7000003f, 0xfc00003f, TRAP,                   0,              I32,            0,      0 },
+{"sdbbp",              "",             0x0000000e, 0xffffffff, TRAP,                   0,              I37,            0,      0 },
+{"sdbbp",              "",             0x7000003f, 0xffffffff, TRAP,                   0,              I32,            0,      I37 },
+{"sdbbp",              "B",            0x0000000e, 0xfc00003f, TRAP,                   0,              I37,            0,      0 },
+{"sdbbp",              "B",            0x7000003f, 0xfc00003f, TRAP,                   0,              I32,            0,      I37 },
 {"sdc1",               "T,o(b)",       0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D,      0,              I2,             0,      SF },
 {"sdc1",               "E,o(b)",       0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D,      0,              I2,             0,      SF },
 {"sdc1",               "T,A(b)",       0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,             0,      SF },
 {"sdc1",               "E,A(b)",       0,    (int) M_SDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,             0,      SF },
-{"sdc2",               "E,o(b)",       0xf8000000, 0xfc000000, RD_3|RD_C2|SM,          0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
+{"sdc2",               "E,+:(d)",      0x49e00000, 0xffe00000, RD_3|RD_C2|SM,          0,              I37,            0,      0 },
+{"sdc2",               "E,o(b)",       0xf8000000, 0xfc000000, RD_3|RD_C2|SM,          0,              I2,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
 {"sdc2",               "E,A(b)",       0,    (int) M_SDC2_AB,  INSN_MACRO,             0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
 {"sdc3",               "E,o(b)",       0xfc000000, 0xfc000000, RD_3|RD_C3|SM,          0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
 {"sdc3",               "E,A(b)",       0,    (int) M_SDC3_AB,  INSN_MACRO,             0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
 {"s.d",                        "T,o(b)",       0xf4000000, 0xfc000000, RD_1|RD_3|SM|FP_D,      0,              I2,             0,      SF },
 {"s.d",                        "T,A(b)",       0,    (int) M_S_DAB,    INSN_MACRO,             INSN2_M_FP_D,   I1,             0,      0 },
-{"sdl",                        "t,o(b)",       0xb0000000, 0xfc000000, RD_1|RD_3|SM,           0,              I3,             0,      0 },
-{"sdl",                        "t,A(b)",       0,    (int) M_SDL_AB,   INSN_MACRO,             0,              I3,             0,      0 },
-{"sdr",                        "t,o(b)",       0xb4000000, 0xfc000000, RD_1|RD_3|SM,           0,              I3,             0,      0 },
-{"sdr",                        "t,A(b)",       0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3,             0,      0 },
-{"sdxc1",              "S,t(b)",       0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0,              I4_33,          0,      0 },
+{"sdl",                        "t,o(b)",       0xb0000000, 0xfc000000, RD_1|RD_3|SM,           0,              I3,             0,      I69 },
+{"sdl",                        "t,A(b)",       0,    (int) M_SDL_AB,   INSN_MACRO,             0,              I3,             0,      I69 },
+{"sdr",                        "t,o(b)",       0xb4000000, 0xfc000000, RD_1|RD_3|SM,           0,              I3,             0,      I69 },
+{"sdr",                        "t,A(b)",       0,    (int) M_SDR_AB,   INSN_MACRO,             0,              I3,             0,      I69 },
+{"sdxc1",              "S,t(b)",       0x4c000009, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0,              I4_33,          0,      I37 },
 {"seb",                        "d,w",          0x7c000420, 0xffe007ff, WR_1|RD_2,              0,              I33,            0,      0 },
 {"seh",                        "d,w",          0x7c000620, 0xffe007ff, WR_1|RD_2,              0,              I33,            0,      0 },
 {"selsl",              "d,v,t",        0x00000005, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              L1,             0,      0 },
@@ -1820,14 +1908,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* ssnop is at the start of the table.  */
 {"standby",            "",             0x42000021, 0xffffffff, 0,                      0,              V1,             0,      0 },
 {"sub",                        "d,v,t",        0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
-{"sub",                        "d,v,I",        0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1,             0,      0 },
+{"sub",                        "d,v,I",        0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1,             0,      I37 },
 {"sub",                        "D,S,T",        0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
 {"sub",                        "D,S,T",        0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
 {"sub.d",              "D,V,T",        0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
 {"sub.s",              "D,V,T",        0x46000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"sub.ob",             "X,Y,Q",        0x7800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"sub.ob",             "D,S,Q",        0x4800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
-{"sub.ps",             "D,V,T",        0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33|IL2F,     0,      0 },
+{"sub.ps",             "D,V,T",        0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I5_33|IL2F,     0,      I37 },
 {"sub.ps",             "D,V,T",        0x45600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"sub.qh",             "X,Y,Q",        0x7820000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"suba.ob",            "Y,Q",          0x78000036, 0xfc2007ff, RD_1|RD_2|FP_D,         WR_MACC,        SB1,            MX,     0 },
@@ -1840,33 +1928,34 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"subu",               "D,S,T",        0x45800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
 {"subu",               "D,S,T",        0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
 {"suspend",            "",             0x42000022, 0xffffffff, 0,                      0,              V1,             0,      0 },
-{"suxc1",              "S,t(b)",       0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0,              I5_33|N55,      0,      0},
+{"suxc1",              "S,t(b)",       0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0,              I5_33|N55,      0,      I37},
 {"sw",                 "t,o(b)",       0xac000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      0 },
 {"sw",                 "t,A(b)",       0,    (int) M_SW_AB,    INSN_MACRO,             0,              I1,             0,      0 },
 {"swapw",              "t,b",          0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM,       0,              XLR,            0,      0 },
 {"swapwu",             "t,b",          0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM,       0,              XLR,            0,      0 },
 {"swapd",              "t,b",          0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM,       0,              XLR,            0,      0 },
-{"swc0",               "E,o(b)",       0xe0000000, 0xfc000000, RD_3|RD_C0|SM,          0,              I1,             0,      IOCT|IOCTP|IOCT2 },
-{"swc0",               "E,A(b)",       0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2 },
+{"swc0",               "E,o(b)",       0xe0000000, 0xfc000000, RD_3|RD_C0|SM,          0,              I1,             0,      IOCT|IOCTP|IOCT2|I37 },
+{"swc0",               "E,A(b)",       0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|I37 },
 {"swc1",               "T,o(b)",       0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S,      0,              I1,             0,      0 },
 {"swc1",               "E,o(b)",       0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S,      0,              I1,             0,      0 },
 {"swc1",               "T,A(b)",       0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      0 },
 {"swc1",               "E,A(b)",       0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      0 },
 {"s.s",                        "T,o(b)",       0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S,      0,              I1,             0,      0 }, /* swc1 */
 {"s.s",                        "T,A(b)",       0,    (int) M_SWC1_AB,  INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      0 },
-{"swc2",               "E,o(b)",       0xe8000000, 0xfc000000, RD_3|RD_C2|SM,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"swc2",               "E,+:(d)",      0x49600000, 0xffe00000, RD_3|RD_C2|SM,          0,              I37,            0,      0 },
+{"swc2",               "E,o(b)",       0xe8000000, 0xfc000000, RD_3|RD_C2|SM,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
 {"swc2",               "E,A(b)",       0,    (int) M_SWC2_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"swc3",               "E,o(b)",       0xec000000, 0xfc000000, RD_3|RD_C3|SM,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"swc3",               "E,A(b)",       0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"swl",                        "t,o(b)",       0xa8000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      0 },
-{"swl",                        "t,A(b)",       0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1,             0,      0 },
-{"scache",             "t,o(b)",       0xa8000000, 0xfc000000, RD_1|RD_3,              0,              I2,             0,      0 }, /* same */
-{"scache",             "t,A(b)",       0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I2,             0,      0 }, /* as swl */
-{"swr",                        "t,o(b)",       0xb8000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      0 },
-{"swr",                        "t,A(b)",       0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I1,             0,      0 },
-{"invalidate",         "t,o(b)",       0xb8000000, 0xfc000000, RD_1|RD_3,              0,              I2,             0,      0 }, /* same */
-{"invalidate",         "t,A(b)",       0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I2,             0,      0 }, /* as swr */
-{"swxc1",              "S,t(b)",       0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0,              I4_33,          0,      0 },
+{"swc3",               "E,o(b)",       0xec000000, 0xfc000000, RD_3|RD_C3|SM,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"swc3",               "E,A(b)",       0,    (int) M_SWC3_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"swl",                        "t,o(b)",       0xa8000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      I37 },
+{"swl",                        "t,A(b)",       0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"scache",             "t,o(b)",       0xa8000000, 0xfc000000, RD_1|RD_3,              0,              I2,             0,      I37 }, /* same */
+{"scache",             "t,A(b)",       0,    (int) M_SWL_AB,   INSN_MACRO,             0,              I2,             0,      I37 }, /* as swl */
+{"swr",                        "t,o(b)",       0xb8000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      I37 },
+{"swr",                        "t,A(b)",       0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"invalidate",         "t,o(b)",       0xb8000000, 0xfc000000, RD_1|RD_3,              0,              I2,             0,      I37 }, /* same */
+{"invalidate",         "t,A(b)",       0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I2,             0,      I37 }, /* as swr */
+{"swxc1",              "S,t(b)",       0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0,              I4_33,          0,      I37 },
 {"synciobdma",         "",             0x0000008f, 0xffffffff, NODS,                   0,              IOCT,           0,      0 },
 {"syncs",              "",             0x0000018f, 0xffffffff, NODS,                   0,              IOCT,           0,      0 },
 {"syncw",              "",             0x0000010f, 0xffffffff, NODS,                   0,              IOCT,           0,      0 },
@@ -1883,23 +1972,23 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"synci",              "o(b)",         0x041f0000, 0xfc1f0000, RD_2|SM,                0,              I33,            0,      0 },
 {"syscall",            "",             0x0000000c, 0xffffffff, TRAP,                   0,              I1,             0,      0 },
 {"syscall",            "B",            0x0000000c, 0xfc00003f, TRAP,                   0,              I1,             0,      0 },
-{"teqi",               "s,j",          0x040c0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 },
+{"teqi",               "s,j",          0x040c0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 },
 {"teq",                        "s,t",          0x00000034, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
 {"teq",                        "s,t,q",        0x00000034, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
-{"teq",                        "s,j",          0x040c0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 }, /* teqi */
+{"teq",                        "s,j",          0x040c0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 }, /* teqi */
 {"teq",                        "s,I",          0,    (int) M_TEQ_I,    INSN_MACRO,             0,              I2,             0,      0 },
-{"tgei",               "s,j",          0x04080000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 },
+{"tgei",               "s,j",          0x04080000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 },
 {"tge",                        "s,t",          0x00000030, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
 {"tge",                        "s,t,q",        0x00000030, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
-{"tge",                        "s,j",          0x04080000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 }, /* tgei */
+{"tge",                        "s,j",          0x04080000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 }, /* tgei */
 {"tge",                        "s,I",          0,    (int) M_TGE_I,    INSN_MACRO,             0,              I2,             0,      0 },
-{"tgeiu",              "s,j",          0x04090000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 },
+{"tgeiu",              "s,j",          0x04090000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 },
 {"tgeu",               "s,t",          0x00000031, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
 {"tgeu",               "s,t,q",        0x00000031, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
-{"tgeu",               "s,j",          0x04090000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 }, /* tgeiu */
+{"tgeu",               "s,j",          0x04090000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 }, /* tgeiu */
 {"tgeu",               "s,I",          0,    (int) M_TGEU_I,   INSN_MACRO,             0,              I2,             0,      0 },
-{"tlbinv",             "",             0x42000003, 0xffffffff, INSN_TLB,               0,              0,              TLBINV, 0 },
-{"tlbinvf",            "",             0x42000004, 0xffffffff, INSN_TLB,               0,              0,              TLBINV, 0 },
+{"tlbinv",             "",             0x42000003, 0xffffffff, INSN_TLB,               0,              I37,            TLBINV, 0 },
+{"tlbinvf",            "",             0x42000004, 0xffffffff, INSN_TLB,               0,              I37,            TLBINV, 0 },
 {"tlbp",               "",             0x42000008, 0xffffffff, INSN_TLB,               0,              I1,             0,      0 },
 {"tlbr",               "",             0x42000001, 0xffffffff, INSN_TLB,               0,              I1,             0,      0 },
 {"tlbwi",              "",             0x42000002, 0xffffffff, INSN_TLB,               0,              I1,             0,      0 },
@@ -1910,20 +1999,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"tlbginvf",           "",             0x4200000c, 0xffffffff, INSN_TLB,               0,              0,              IVIRT,  0 },
 {"tlbgwr",             "",             0x4200000e, 0xffffffff, INSN_TLB,               0,              0,              IVIRT,  0 },
 {"tlbgp",              "",             0x42000010, 0xffffffff, INSN_TLB,               0,              0,              IVIRT,  0 },
-{"tlti",               "s,j",          0x040a0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 },
+{"tlti",               "s,j",          0x040a0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 },
 {"tlt",                        "s,t",          0x00000032, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
 {"tlt",                        "s,t,q",        0x00000032, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
-{"tlt",                        "s,j",          0x040a0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 }, /* tlti */
+{"tlt",                        "s,j",          0x040a0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 }, /* tlti */
 {"tlt",                        "s,I",          0,    (int) M_TLT_I,    INSN_MACRO,             0,              I2,             0,      0 },
-{"tltiu",              "s,j",          0x040b0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 },
+{"tltiu",              "s,j",          0x040b0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 },
 {"tltu",               "s,t",          0x00000033, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
 {"tltu",               "s,t,q",        0x00000033, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
-{"tltu",               "s,j",          0x040b0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 }, /* tltiu */
+{"tltu",               "s,j",          0x040b0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 }, /* tltiu */
 {"tltu",               "s,I",          0,    (int) M_TLTU_I,   INSN_MACRO,             0,              I2,             0,      0 },
-{"tnei",               "s,j",          0x040e0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 },
+{"tnei",               "s,j",          0x040e0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 },
 {"tne",                        "s,t",          0x00000036, 0xfc00ffff, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
 {"tne",                        "s,t,q",        0x00000036, 0xfc00003f, RD_1|RD_2|TRAP,         0,              I2,             0,      0 },
-{"tne",                        "s,j",          0x040e0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      0 }, /* tnei */
+{"tne",                        "s,j",          0x040e0000, 0xfc1f0000, RD_1|TRAP,              0,              I2,             0,      I37 }, /* tnei */
 {"tne",                        "s,I",          0,    (int) M_TNE_I,    INSN_MACRO,             0,              I2,             0,      0 },
 {"trunc.l.d",          "D,S",          0x46200009, 0xffff003f, WR_1|RD_2|FP_D,         0,              I3_33,          0,      0 },
 {"trunc.l.s",          "D,S",          0x46000009, 0xffff003f, WR_1|RD_2|FP_S|FP_D,    0,              I3_33,          0,      0 },
@@ -1934,13 +2023,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"trunc.w.s",          "D,S",          0x4600000d, 0xffff003f, WR_1|RD_2|FP_S,         0,              I2,             0,      EE },
 {"trunc.w.s",          "D,S,x",        0x4600000d, 0xffff003f, WR_1|RD_2|FP_S,         0,              I2,             0,      EE },
 {"trunc.w.s",          "D,S,t",        0,    (int) M_TRUNCWS,  INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      EE },
-{"uld",                        "t,A(b)",       0,    (int) M_ULD_AB,   INSN_MACRO,             0,              I3,             0,      0 },
-{"ulh",                        "t,A(b)",       0,    (int) M_ULH_AB,   INSN_MACRO,             0,              I1,             0,      0 },
-{"ulhu",               "t,A(b)",       0,    (int) M_ULHU_AB,  INSN_MACRO,             0,              I1,             0,      0 },
-{"ulw",                        "t,A(b)",       0,    (int) M_ULW_AB,   INSN_MACRO,             0,              I1,             0,      0 },
-{"usd",                        "t,A(b)",       0,    (int) M_USD_AB,   INSN_MACRO,             0,              I3,             0,      0 },
-{"ush",                        "t,A(b)",       0,    (int) M_USH_AB,   INSN_MACRO,             0,              I1,             0,      0 },
-{"usw",                        "t,A(b)",       0,    (int) M_USW_AB,   INSN_MACRO,             0,              I1,             0,      0 },
+{"uld",                        "t,A(b)",       0,    (int) M_ULD_AB,   INSN_MACRO,             0,              I3,             0,      I69 },
+{"ulh",                        "t,A(b)",       0,    (int) M_ULH_AB,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"ulhu",               "t,A(b)",       0,    (int) M_ULHU_AB,  INSN_MACRO,             0,              I1,             0,      I37 },
+{"ulw",                        "t,A(b)",       0,    (int) M_ULW_AB,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"usd",                        "t,A(b)",       0,    (int) M_USD_AB,   INSN_MACRO,             0,              I3,             0,      I69 },
+{"ush",                        "t,A(b)",       0,    (int) M_USH_AB,   INSN_MACRO,             0,              I1,             0,      I37 },
+{"usw",                        "t,A(b)",       0,    (int) M_USW_AB,   INSN_MACRO,             0,              I1,             0,      I37 },
 {"v3mulu",             "d,v,t",        0x70000011, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IOCT,           0,      0 },
 {"vmm0",               "d,v,t",        0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IOCT,           0,      0 },
 {"vmulu",              "d,v,t",        0x7000000f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IOCT,           0,      0 },
@@ -1971,43 +2060,45 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* Coprocessor 0 move instructions cfc0 and ctc0 conflict with the 
    mfhc0 and mthc0 XPA instructions, so they have been placed here 
    to allow the XPA instructions to take precedence.  */
-{"ctc0",               "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
-{"cfc0",               "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
+{"ctc0",               "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      IOCT|IOCTP|IOCT2 },
+{"cfc0",               "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LC         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
 
 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
    instructions so they are here for the latters to take precedence.  */
-{"bc2f",               "p",            0x49000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2 },
-{"bc2f",               "N,p",          0x49000000, 0xffe30000, RD_CC|CBD,              0,              I32,            0,      IOCT|IOCTP|IOCT2 },
-{"bc2fl",              "p",            0x49020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2 },
-{"bc2fl",              "N,p",          0x49020000, 0xffe30000, RD_CC|CBL,              0,              I32,            0,      IOCT|IOCTP|IOCT2 },
-{"bc2t",               "p",            0x49010000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2 },
-{"bc2t",               "N,p",          0x49010000, 0xffe30000, RD_CC|CBD,              0,              I32,            0,      IOCT|IOCTP|IOCT2 },
-{"bc2tl",              "p",            0x49030000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2 },
-{"bc2tl",              "N,p",          0x49030000, 0xffe30000, RD_CC|CBL,              0,              I32,            0,      IOCT|IOCTP|IOCT2 },
-{"cfc2",               "t,G",          0x48400000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"cfc2",               "t,+9",         0x48400000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              EE,             0,      0 },
-{"cfc2.i",             "t,+9",         0x48400001, 0xffe007ff, WR_1|RD_C2|LCD,         0,              EE,             0,      0 },
-{"cfc2.ni",            "t,+9",         0x48400000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              EE,             0,      0 },
-{"ctc2",               "t,G",          0x48c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"ctc2",               "t,+9",         0x48c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              EE,             0,      0 },
-{"ctc2.i",             "t,+9",         0x48c00001, 0xffe007ff, RD_1|WR_CC|COD,         0,              EE,             0,      0 },
-{"ctc2.ni",            "t,+9",         0x48c00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              EE,             0,      0 },
-{"dmfc2",              "t,i",          0x48200000, 0xffe00000, WR_1|RD_C2|LCD,         0,              IOCT,           0,      0 },
-{"dmfc2",              "t,G",          0x48200000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
-{"dmfc2",              "t,G,H",        0x48200000, 0xffe007f8, WR_1|RD_C2|LCD,         0,              I64,            0,      IOCT|IOCTP|IOCT2 },
-{"dmtc2",              "t,i",          0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|COD,   0,              IOCT,           0,      0 },
-{"dmtc2",              "t,G",          0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|COD,   0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
-{"dmtc2",              "t,G,H",        0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|COD,   0,              I64,            0,      IOCT|IOCTP|IOCT2 },
-{"mfc2",               "t,G",          0x48000000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"mfc2",               "t,G,H",        0x48000000, 0xffe007f8, WR_1|RD_C2|LCD,         0,              I32,            0,      IOCT|IOCTP|IOCT2 },
-{"mfhc2",              "t,G",          0x48600000, 0xffe007ff, WR_1|RD_C2|LCD,         0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mfhc2",              "t,G,H",        0x48600000, 0xffe007f8, WR_1|RD_C2|LCD,         0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mfhc2",              "t,i",          0x48600000, 0xffe00000, WR_1|RD_C2|LCD,         0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mtc2",               "t,G",          0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|COD,   0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"mtc2",               "t,G,H",        0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|COD,   0,              I32,            0,      IOCT|IOCTP|IOCT2 },
-{"mthc2",              "t,G",          0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|COD,   0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mthc2",              "t,G,H",        0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|COD,   0,              I33,            0,      IOCT|IOCTP|IOCT2 },
-{"mthc2",              "t,i",          0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|COD,   0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"bc2eqz",             "E,p",          0x49200000, 0xffe00000, RD_C2|CBD,              0,              I37,            0,      0 },
+{"bc2f",               "p",            0x49000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|I37 },
+{"bc2f",               "N,p",          0x49000000, 0xffe30000, RD_CC|CBD,              0,              I32,            0,      IOCT|IOCTP|IOCT2|I37 },
+{"bc2fl",              "p",            0x49020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|I37 },
+{"bc2fl",              "N,p",          0x49020000, 0xffe30000, RD_CC|CBL,              0,              I32,            0,      IOCT|IOCTP|IOCT2|I37 },
+{"bc2nez",             "E,p",          0x49a00000, 0xffe00000, RD_C2|CBD,              0,              I37,            0,      0 },
+{"bc2t",               "p",            0x49010000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|I37 },
+{"bc2t",               "N,p",          0x49010000, 0xffe30000, RD_CC|CBD,              0,              I32,            0,      IOCT|IOCTP|IOCT2|I37 },
+{"bc2tl",              "p",            0x49030000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|I37 },
+{"bc2tl",              "N,p",          0x49030000, 0xffe30000, RD_CC|CBL,              0,              I32,            0,      IOCT|IOCTP|IOCT2|I37 },
+{"cfc2",               "t,G",          0x48400000, 0xffe007ff, WR_1|RD_C2|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"cfc2",               "t,+9",         0x48400000, 0xffe007ff, WR_1|RD_C2|LC,          0,              EE,             0,      0 },
+{"cfc2.i",             "t,+9",         0x48400001, 0xffe007ff, WR_1|RD_C2|LC,          0,              EE,             0,      0 },
+{"cfc2.ni",            "t,+9",         0x48400000, 0xffe007ff, WR_1|RD_C2|LC,          0,              EE,             0,      0 },
+{"ctc2",               "t,G",          0x48c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"ctc2",               "t,+9",         0x48c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              EE,             0,      0 },
+{"ctc2.i",             "t,+9",         0x48c00001, 0xffe007ff, RD_1|WR_CC|CM,          0,              EE,             0,      0 },
+{"ctc2.ni",            "t,+9",         0x48c00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              EE,             0,      0 },
+{"dmfc2",              "t,i",          0x48200000, 0xffe00000, WR_1|RD_C2|LC,          0,              IOCT,           0,      0 },
+{"dmfc2",              "t,G",          0x48200000, 0xffe007ff, WR_1|RD_C2|LC,          0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
+{"dmfc2",              "t,G,H",        0x48200000, 0xffe007f8, WR_1|RD_C2|LC,          0,              I64,            0,      IOCT|IOCTP|IOCT2 },
+{"dmtc2",              "t,i",          0x48a00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM,    0,              IOCT,           0,      0 },
+{"dmtc2",              "t,G",          0x48a00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM,    0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
+{"dmtc2",              "t,G,H",        0x48a00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM,    0,              I64,            0,      IOCT|IOCTP|IOCT2 },
+{"mfc2",               "t,G",          0x48000000, 0xffe007ff, WR_1|RD_C2|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"mfc2",               "t,G,H",        0x48000000, 0xffe007f8, WR_1|RD_C2|LC,          0,              I32,            0,      IOCT|IOCTP|IOCT2 },
+{"mfhc2",              "t,G",          0x48600000, 0xffe007ff, WR_1|RD_C2|LC,          0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"mfhc2",              "t,G,H",        0x48600000, 0xffe007f8, WR_1|RD_C2|LC,          0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"mfhc2",              "t,i",          0x48600000, 0xffe00000, WR_1|RD_C2|LC,          0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"mtc2",               "t,G",          0x48800000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM,    0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
+{"mtc2",               "t,G,H",        0x48800000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM,    0,              I32,            0,      IOCT|IOCTP|IOCT2 },
+{"mthc2",              "t,G",          0x48e00000, 0xffe007ff, RD_1|WR_C2|WR_CC|CM,    0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"mthc2",              "t,G,H",        0x48e00000, 0xffe007f8, RD_1|WR_C2|WR_CC|CM,    0,              I33,            0,      IOCT|IOCTP|IOCT2 },
+{"mthc2",              "t,i",          0x48e00000, 0xffe00000, RD_1|WR_C2|WR_CC|CM,    0,              I33,            0,      IOCT|IOCTP|IOCT2 },
 {"qmfc2",              "t,+6",         0x48200000, 0xffe007ff, WR_1|RD_C2,             0,              EE,             0,      0 },
 {"qmfc2.i",            "t,+6",         0x48200001, 0xffe007ff, WR_1|RD_C2,             0,              EE,             0,      0 },
 {"qmfc2.ni",           "t,+6",         0x48200000, 0xffe007ff, WR_1|RD_C2,             0,              EE,             0,      0 },
@@ -2016,18 +2107,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"qmtc2.ni",           "t,+6",         0x48a00000, 0xffe007ff, RD_1|WR_C2,             0,              EE,             0,      0 },
 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X 
    instructions, so they are here for the latters to take precedence.  */
-{"bc3f",               "p",            0x4d000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"bc3fl",              "p",            0x4d020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|EE },
-{"bc3t",               "p",            0x4d010000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"bc3tl",              "p",            0x4d030000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|EE },
-{"cfc3",               "t,G",          0x4c400000, 0xffe007ff, WR_1|RD_C3|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"ctc3",               "t,G",          0x4cc00000, 0xffe007ff, RD_1|WR_CC|COD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"dmfc3",              "t,G",          0x4c200000, 0xffe007ff, WR_1|RD_C3|LCD,         0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
-{"dmtc3",              "t,G",          0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|COD,   0,              I3,             0,      IOCT|IOCTP|IOCT2|EE },
-{"mfc3",               "t,G",          0x4c000000, 0xffe007ff, WR_1|RD_C3|LCD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"mfc3",               "t,G,H",        0x4c000000, 0xffe007f8, WR_1|RD_C3|LCD,         0,              I32,            0,      IOCT|IOCTP|IOCT2|EE },
-{"mtc3",               "t,G",          0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|COD,   0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"mtc3",               "t,G,H",        0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|COD,   0,              I32,            0,      IOCT|IOCTP|IOCT2|EE },
+{"bc3f",               "p",            0x4d000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"bc3fl",              "p",            0x4d020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"bc3t",               "p",            0x4d010000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"bc3tl",              "p",            0x4d030000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"cfc3",               "t,G",          0x4c400000, 0xffe007ff, WR_1|RD_C3|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"ctc3",               "t,G",          0x4cc00000, 0xffe007ff, RD_1|WR_CC|CM,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"dmfc3",              "t,G",          0x4c200000, 0xffe007ff, WR_1|RD_C3|LC,          0,              I3,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"dmtc3",              "t,G",          0x4ca00000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM,    0,              I3,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"mfc3",               "t,G",          0x4c000000, 0xffe007ff, WR_1|RD_C3|LC,          0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"mfc3",               "t,G,H",        0x4c000000, 0xffe007f8, WR_1|RD_C3|LC,          0,              I32,            0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"mtc3",               "t,G",          0x4c800000, 0xffe007ff, RD_1|WR_C3|WR_CC|CM,    0,              I1,             0,      IOCT|IOCTP|IOCT2|EE|I37 },
+{"mtc3",               "t,G,H",        0x4c800000, 0xffe007f8, RD_1|WR_C3|WR_CC|CM,    0,              I32,            0,      IOCT|IOCTP|IOCT2|EE|I37 },
 
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
      4010 any more, so move this insn out of the way.  If the object
@@ -2314,10 +2405,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dpsqx_s.w.ph",       "7,s,t",        0x7c000670, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,              D33,    0 },
 {"dpsqx_sa.w.ph",      "7,s,t",        0x7c0006f0, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,              D33,    0 },
 /* Move bc0* after mftr and mttr to avoid opcode collision.  */
-{"bc0f",               "p",            0x41000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2 },
-{"bc0fl",              "p",            0x41020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2 },
-{"bc0t",               "p",            0x41010000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2 },
-{"bc0tl",              "p",            0x41030000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2 },
+{"bc0f",               "p",            0x41000000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|I37 },
+{"bc0fl",              "p",            0x41020000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|I37 },
+{"bc0t",               "p",            0x41010000, 0xffff0000, RD_CC|CBD,              0,              I1,             0,      IOCT|IOCTP|IOCT2|I37 },
+{"bc0tl",              "p",            0x41030000, 0xffff0000, RD_CC|CBL,              0,              I2|T3,          0,      IOCT|IOCTP|IOCT2|I37 },
 /* ST Microelectronics Loongson-2E and -2F.  */
 {"mult.g",             "d,s,t",        0x7c000018, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2E,           0,      0 },
 {"mult.g",             "d,s,t",        0x70000010, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
@@ -2502,10 +2593,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lle",                        "t,A(b)",       0,    (int) M_LLE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"lwe",                        "t,+j(b)",      0x7c00002f, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lwe",                        "t,A(b)",       0,    (int) M_LWE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
-{"lwle",               "t,+j(b)",      0x7c000019, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
-{"lwle",               "t,A(b)",       0,    (int) M_LWLE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },
-{"lwre",               "t,+j(b)",      0x7c00001a, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
-{"lwre",               "t,A(b)",       0,    (int) M_LWRE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },
+{"lwle",               "t,+j(b)",      0x7c000019, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    I37 },
+{"lwle",               "t,A(b)",       0,    (int) M_LWLE_AB,  INSN_MACRO,             0,              0,              EVA,    I37 },
+{"lwre",               "t,+j(b)",      0x7c00001a, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    I37 },
+{"lwre",               "t,A(b)",       0,    (int) M_LWRE_AB,  INSN_MACRO,             0,              0,              EVA,    I37 },
 {"sbe",                        "t,+j(b)",      0x7c00001c, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    0 },
 {"sbe",                        "t,A(b)",       0,    (int) M_SBE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"sce",                        "t,+j(b)",      0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM,          0,              0,              EVA,    0 },
@@ -2514,10 +2605,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"she",                        "t,A(b)",       0,    (int) M_SHE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
 {"swe",                        "t,+j(b)",      0x7c00001f, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    0 },
 {"swe",                        "t,A(b)",       0,    (int) M_SWE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
-{"swle",               "t,+j(b)",      0x7c000021, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    0 },
-{"swle",               "t,A(b)",       0,    (int) M_SWLE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },
-{"swre",               "t,+j(b)",      0x7c000022, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    0 },
-{"swre",               "t,A(b)",       0,    (int) M_SWRE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },
+{"swle",               "t,+j(b)",      0x7c000021, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    I37 },
+{"swle",               "t,A(b)",       0,    (int) M_SWLE_AB,  INSN_MACRO,             0,              0,              EVA,    I37 },
+{"swre",               "t,+j(b)",      0x7c000022, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    I37 },
+{"swre",               "t,A(b)",       0,    (int) M_SWRE_AB,  INSN_MACRO,             0,              0,              EVA,    I37 },
 {"cachee",             "k,+j(b)",      0x7c00001b, 0xfc00007f, RD_3,                   0,              0,              EVA,    0 },
 {"cachee",             "k,A(b)",       0,    (int) M_CACHEE_AB,INSN_MACRO,             0,              0,              EVA,    0 },
 {"prefe",              "k,+j(b)",      0x7c000023, 0xfc00007f, RD_3|LM,                0,              0,              EVA,    0 },
@@ -3050,11 +3141,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ffint_s.d",          "+d,+e",        0x7b3d001e, 0xffff003f, WR_1|RD_2,              0,              0,              MSA,    0 },
 {"ffint_u.w",          "+d,+e",        0x7b3e001e, 0xffff003f, WR_1|RD_2,              0,              0,              MSA,    0 },
 {"ffint_u.d",          "+d,+e",        0x7b3f001e, 0xffff003f, WR_1|RD_2,              0,              0,              MSA,    0 },
-{"ctcmsa",             "+l,d",         0x783e0019, 0xffff003f, RD_2|COD,               0,              0,              MSA,    0 },
-{"cfcmsa",             "+k,+n",        0x787e0019, 0xffff003f, WR_1|COD,               0,              0,              MSA,    0 },
+{"ctcmsa",             "+l,d",         0x783e0019, 0xffff003f, RD_2|CM,                0,              0,              MSA,    0 },
+{"cfcmsa",             "+k,+n",        0x787e0019, 0xffff003f, WR_1|CM,                0,              0,              MSA,    0 },
 {"move.v",             "+d,+e",        0x78be0019, 0xffff003f, WR_1|RD_2,              0,              0,              MSA,    0 },
-{"lsa",                        "d,v,t,+~",     0x00000005, 0xfc00073f, WR_1|RD_2|RD_3,         0,              0,              MSA,    0 },
-{"dlsa",               "d,v,t,+~",     0x00000015, 0xfc00073f, WR_1|RD_2|RD_3,         0,              0,              MSA64,  0 },
 
 /* User Defined Instruction.  */
 {"udi0",               "s,t,d,+1",     0x70000010, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
@@ -3121,6 +3210,125 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"udi15",              "s,t,+2",       0x7000001f, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
 {"udi15",              "s,+3",         0x7000001f, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
 {"udi15",              "+4",           0x7000001f, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
+{"lsa",                        "d,v,t,+~",     0x00000005, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I37,            MSA,    0 },
+{"dlsa",               "d,v,t,+~",     0x00000015, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I69,            MSA64,  0 },
+/* MIPS r6.  */
+
+{"aui",                        "t,s,u",        0x3c000000, 0xfc000000, WR_1|RD_2,              0,              I37,            0,      0 },
+{"auipc",              "s,u",          0xec1e0000, 0xfc1f0000, WR_1,                   RD_pc,          I37,            0,      0 },
+{"daui",               "t,s,u",        0x74000000, 0xfc000000, WR_1|RD_2,              0,              I37,            0,      0 },
+{"dahi",               "s,-d,u",       0x04060000, 0xfc1f0000, MOD_1,                  0,              I69,            0,      0 },
+{"dati",               "s,-d,u",       0x041e0000, 0xfc1f0000, MOD_1,                  0,              I69,            0,      0 },
+
+{"align",              "d,s,t,+I",     0x7c000220, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I37,            0,      0 },
+{"dalign",             "d,s,t,+O",     0x7c000224, 0xfc00063f, WR_1|RD_2|RD_3,         0,              I69,            0,      0 },
+{"bitswap",            "d,t",          0x7c000020, 0xffe007ff, WR_1|RD_2,              0,              I37,            0,      0 },
+{"dbitswap",           "d,t",          0x7c000024, 0xffe007ff, WR_1|RD_2,              0,              I69,            0,      0 },
+
+{"bovc",               "s,-w,p",       0x20000000, 0xfc000000, RD_1|RD_2|NODS,         FS,             I37,            0,      0 },
+{"bovc",               "t,-x,p",       0x20000000, 0xfc000000, RD_1|RD_2|NODS,         FS|INSN2_ALIAS, I37,            0,      0 },
+{"beqzalc",            "-t,p",         0x20000000, 0xffe00000, RD_1|WR_31|NODS,        FS,             I37,            0,      0 },
+{"beqc",               "-s,-u,p",      0x20000000, 0xfc000000, RD_1|RD_2|NODS,         FS,             I37,            0,      0 },
+{"beqc",               "t,-y,p",       0x20000000, 0xfc000000, RD_1|RD_2|NODS,         FS|INSN2_ALIAS, I37,            0,      0 },
+{"bnvc",               "s,-w,p",       0x60000000, 0xfc000000, RD_1|RD_2|NODS,         FS,             I37,            0,      0 },
+{"bnvc",               "t,-x,p",       0x60000000, 0xfc000000, RD_1|RD_2|NODS,         FS|INSN2_ALIAS, I37,            0,      0 },
+{"bnezalc",            "-t,p",         0x60000000, 0xffe00000, RD_1|WR_31|NODS,        FS,             I37,            0,      0 },
+{"bnec",               "-s,-u,p",      0x60000000, 0xfc000000, RD_1|RD_2|NODS,         FS,             I37,            0,      0 },
+{"bnec",               "t,-y,p",       0x60000000, 0xfc000000, RD_1|RD_2|NODS,         FS|INSN2_ALIAS, I37,            0,      0 },
+
+{"blezc",              "-t,p",         0x58000000, 0xffe00000, RD_1|NODS,              FS,             I37,            0,      0 },
+{"bgezc",              "+;,p",         0x58000000, 0xfc000000, RD_1|NODS,              FS,             I37,            0,      0 },
+{"bgec",               "-s,-v,p",      0x58000000, 0xfc000000, RD_1|RD_2|NODS,         FS,             I37,            0,      0 },
+{"bgtzc",              "-t,p",         0x5c000000, 0xffe00000, RD_1|NODS,              FS,             I37,            0,      0 },
+{"bltzc",              "+;,p",         0x5c000000, 0xfc000000, RD_1|NODS,              FS,             I37,            0,      0 },
+{"bltc",               "-s,-v,p",      0x5c000000, 0xfc000000, RD_1|RD_2|NODS,         FS,             I37,            0,      0 },
+{"blezalc",            "-t,p",         0x18000000, 0xffe00000, RD_1|WR_31|NODS,        FS,             I37,            0,      0 },
+{"bgezalc",            "+;,p",         0x18000000, 0xfc000000, RD_1|WR_31|NODS,        FS,             I37,            0,      0 },
+{"bgeuc",              "-s,-v,p",      0x18000000, 0xfc000000, RD_1|RD_2|NODS,         FS,             I37,            0,      0 },
+{"bgtzalc",            "-t,p",         0x1c000000, 0xffe00000, RD_1|WR_31|NODS,        FS,             I37,            0,      0 },
+{"bltzalc",            "+;,p",         0x1c000000, 0xfc000000, RD_1|WR_31|NODS,        FS,             I37,            0,      0 },
+{"bltuc",              "-s,-v,p",      0x1c000000, 0xfc000000, RD_1|RD_2|NODS,         FS,             I37,            0,      0 },
+
+{"beqzc",              "-s,+\"",       0xd8000000, 0xfc000000, RD_1|NODS,              FS,             I37,            0,      0 },
+{"jrc",                        "t",            0xd8000000, 0xffe0ffff, RD_1|NODS,              INSN2_ALIAS,    I37,            0,      0 },
+{"jic",                        "t,j",          0xd8000000, 0xffe00000, RD_1|NODS,              0,              I37,            0,      0 },
+
+{"bnezc",              "-s,+\"",       0xf8000000, 0xfc000000, RD_1|NODS,              FS,             I37,            0,      0 },
+{"jalrc",              "t",            0xf8000000, 0xffe0ffff, RD_1|NODS,              0,              I37,            0,      0 },
+{"jialc",              "t,j",          0xf8000000, 0xffe00000, RD_1|NODS,              0,              I37,            0,      0 },
+
+{"cmp.af.s",           "D,S,T",        0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.af.d",           "D,S,T",        0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.eq.s",           "D,S,T",        0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.eq.d",           "D,S,T",        0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.le.s",           "D,S,T",        0x46800006, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.le.d",           "D,S,T",        0x46a00006, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.lt.s",           "D,S,T",        0x46800004, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.lt.d",           "D,S,T",        0x46a00004, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.ne.s",           "D,S,T",        0x46800013, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.ne.d",           "D,S,T",        0x46a00013, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.or.s",           "D,S,T",        0x46800011, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.or.d",           "D,S,T",        0x46a00011, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.ueq.s",          "D,S,T",        0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.ueq.d",          "D,S,T",        0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.ule.s",          "D,S,T",        0x46800007, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.ule.d",          "D,S,T",        0x46a00007, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.ult.s",          "D,S,T",        0x46800005, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.ult.d",          "D,S,T",        0x46a00005, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.un.s",           "D,S,T",        0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.un.d",           "D,S,T",        0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.une.s",          "D,S,T",        0x46800012, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.une.d",          "D,S,T",        0x46a00012, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.saf.s",          "D,S,T",        0x46800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.saf.d",          "D,S,T",        0x46a00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.seq.s",          "D,S,T",        0x4680000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.seq.d",          "D,S,T",        0x46a0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.sle.s",          "D,S,T",        0x4680000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.sle.d",          "D,S,T",        0x46a0000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.slt.s",          "D,S,T",        0x4680000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.slt.d",          "D,S,T",        0x46a0000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.sne.s",          "D,S,T",        0x4680001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.sne.d",          "D,S,T",        0x46a0001b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.sor.s",          "D,S,T",        0x46800019, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.sor.d",          "D,S,T",        0x46a00019, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.sueq.s",         "D,S,T",        0x4680000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.sueq.d",         "D,S,T",        0x46a0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.sule.s",         "D,S,T",        0x4680000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.sule.d",         "D,S,T",        0x46a0000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.sult.s",         "D,S,T",        0x4680000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.sult.d",         "D,S,T",        0x46a0000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"cmp.sun.s",          "D,S,T",        0x46800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.sun.d",          "D,S,T",        0x46a00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.sune.s",         "D,S,T",        0x4680001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"cmp.sune.d",         "D,S,T",        0x46a0001a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+
+{"maddf.s",            "D,S,T",        0x46000018, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S,   0,              I37,            0,      0 },
+{"msubf.s",            "D,S,T",        0x46000019, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S,   0,              I37,            0,      0 },
+{"maddf.d",            "D,S,T",        0x46200018, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D,   0,              I37,            0,      0 },
+{"msubf.d",            "D,S,T",        0x46200019, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D,   0,              I37,            0,      0 },
+
+{"rint.s",             "D,S",          0x4600001a, 0xffff003f, WR_1|RD_2|FP_S,         0,              I37,            0,      0 },
+{"rint.d",             "D,S",          0x4620001a, 0xffff003f, WR_1|RD_2|FP_D,         0,              I37,            0,      0 },
+{"class.s",            "D,S",          0x4600001b, 0xffff003f, WR_1|RD_2|FP_S,         0,              I37,            0,      0 },
+{"class.d",            "D,S",          0x4620001b, 0xffff003f, WR_1|RD_2|FP_D,         0,              I37,            0,      0 },
+{"min.d",              "D,S,T",        0x4620001c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"max.d",              "D,S,T",        0x4620001e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"mina.s",             "D,S,T",        0x4600001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"mina.d",             "D,S,T",        0x4620001d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"maxa.s",             "D,S,T",        0x4600001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"maxa.d",             "D,S,T",        0x4620001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+
+{"sel.s",              "D,S,T",        0x46000010, 0xffe0003f, MOD_1|RD_2|RD_3|FP_S,   0,              I37,            0,      0 },
+{"sel.d",              "D,S,T",        0x46200010, 0xffe0003f, MOD_1|RD_2|RD_3|FP_D,   0,              I37,            0,      0 },
+{"selnez",             "d,s,t",        0x00000037, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I37,            0,      0 },
+{"selnez.s",           "D,S,T",        0x46000017, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"selnez.d",           "D,S,T",        0x46200017, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+{"seleqz",             "d,s,t",        0x00000035, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I37,            0,      0 },
+{"seleqz.s",           "D,S,T",        0x46000014, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I37,            0,      0 },
+{"seleqz.d",           "D,S,T",        0x46200014, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I37,            0,      0 },
+
+{"aluipc",             "s,u",          0xec1f0000, 0xfc1f0000, WR_1,                   RD_pc,          I37,            0,      0 },
+
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the