Test local workgroup size

[platform/upstream/VK-GL-CTS.git] / android / cts / nyc / vk-master.txt

diff --git a/android/cts/nyc/vk-master.txt b/android/cts/nyc/vk-master.txt
index af3ec73..7d55cd5 100644 (file)
--- a/android/cts/nyc/vk-master.txt
+++ b/android/cts/nyc/vk-master.txt
@@ -7498,16390 +7498,16390 @@ dEQP-VK.memory.pipeline_barrier.all_device.1024
 dEQP-VK.memory.pipeline_barrier.all_device.8192
 dEQP-VK.memory.pipeline_barrier.all_device.65536
 dEQP-VK.memory.pipeline_barrier.all_device.1048576
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_repl_dfail_inv_comp_not_equal_back_fail_decc_pass_repl_dfail_keep_comp_less
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_keep_dfail_inv_comp_not_equal_back_fail_decc_pass_repl_dfail_inv_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_decw_dfail_wrap_comp_less_back_fail_incc_pass_keep_dfail_inv_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_incc_dfail_keep_comp_greater_or_equal_back_fail_wrap_pass_decw_dfail_wrap_comp_less
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_keep_dfail_wrap_comp_equal_back_fail_inv_pass_incc_dfail_keep_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_repl_pass_inv_dfail_repl_comp_always_back_fail_incc_pass_keep_dfail_wrap_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_incc_dfail_decc_comp_not_equal_back_fail_repl_pass_inv_dfail_repl_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_keep_dfail_incc_comp_greater_or_equal_back_fail_zero_pass_incc_dfail_decc_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_zero_dfail_keep_comp_equal_back_fail_incc_pass_keep_dfail_incc_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_wrap_dfail_decw_comp_less_or_equal_back_fail_decc_pass_zero_dfail_keep_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_zero_dfail_zero_comp_greater_back_fail_keep_pass_wrap_dfail_decw_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_wrap_dfail_decw_comp_less_or_equal_back_fail_inv_pass_zero_dfail_zero_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_incc_dfail_decc_comp_equal_back_fail_incc_pass_wrap_dfail_decw_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_decc_dfail_decc_comp_less_or_equal_back_fail_wrap_pass_incc_dfail_decc_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_wrap_dfail_decc_comp_never_back_fail_decc_pass_decc_dfail_decc_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_decw_dfail_decw_comp_greater_or_equal_back_fail_decc_pass_wrap_dfail_decc_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decw_pass_decw_dfail_incc_comp_greater_or_equal_back_fail_wrap_pass_decw_dfail_decw_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_decw_dfail_decw_comp_always_back_fail_decw_pass_decw_dfail_incc_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_repl_pass_keep_dfail_incc_comp_less_back_fail_keep_pass_decw_dfail_decw_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_zero_dfail_inv_comp_always_back_fail_repl_pass_keep_dfail_incc_comp_less
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decw_pass_wrap_dfail_repl_comp_never_back_fail_inv_pass_zero_dfail_inv_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_incc_dfail_inv_comp_less_back_fail_decw_pass_wrap_dfail_repl_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_incc_dfail_decc_comp_equal_back_fail_decc_pass_incc_dfail_inv_comp_less
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decw_pass_wrap_dfail_wrap_comp_less_back_fail_decc_pass_incc_dfail_decc_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_wrap_dfail_decc_comp_equal_back_fail_decw_pass_wrap_dfail_wrap_comp_less
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_inv_dfail_wrap_comp_less_back_fail_inv_pass_wrap_dfail_decc_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_decc_dfail_incc_comp_greater_back_fail_zero_pass_inv_dfail_wrap_comp_less
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_keep_dfail_inv_comp_greater_back_fail_wrap_pass_decc_dfail_incc_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_decc_dfail_wrap_comp_greater_or_equal_back_fail_keep_pass_keep_dfail_inv_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_inv_dfail_decc_comp_less_or_equal_back_fail_inv_pass_decc_dfail_wrap_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_inv_dfail_repl_comp_greater_or_equal_back_fail_zero_pass_inv_dfail_decc_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_keep_dfail_keep_comp_always_back_fail_decc_pass_inv_dfail_repl_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_zero_dfail_decc_comp_never_back_fail_wrap_pass_keep_dfail_keep_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_incc_dfail_zero_comp_never_back_fail_wrap_pass_zero_dfail_decc_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_incc_dfail_decw_comp_never_back_fail_keep_pass_incc_dfail_zero_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_keep_dfail_inv_comp_never_back_fail_incc_pass_incc_dfail_decw_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_repl_dfail_wrap_comp_less_back_fail_incc_pass_keep_dfail_inv_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_decc_dfail_zero_comp_greater_or_equal_back_fail_keep_pass_repl_dfail_wrap_comp_less
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_zero_dfail_decw_comp_equal_back_fail_decc_pass_decc_dfail_zero_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_wrap_dfail_zero_comp_not_equal_back_fail_wrap_pass_zero_dfail_decw_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_decc_dfail_zero_comp_not_equal_back_fail_keep_pass_wrap_dfail_zero_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_decc_dfail_repl_comp_never_back_fail_keep_pass_decc_dfail_zero_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_inv_dfail_inv_comp_greater_back_fail_inv_pass_decc_dfail_repl_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decw_pass_decw_dfail_inv_comp_always_back_fail_wrap_pass_inv_dfail_inv_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_keep_dfail_repl_comp_greater_back_fail_decw_pass_decw_dfail_inv_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_decc_dfail_decw_comp_equal_back_fail_incc_pass_keep_dfail_repl_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_repl_dfail_keep_comp_less_or_equal_back_fail_zero_pass_decc_dfail_decw_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_decw_dfail_wrap_comp_always_back_fail_decc_pass_repl_dfail_keep_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_incc_dfail_incc_comp_less_or_equal_back_fail_zero_pass_decw_dfail_wrap_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_incc_dfail_decc_comp_never_back_fail_incc_pass_incc_dfail_incc_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_incc_dfail_inv_comp_greater_or_equal_back_fail_incc_pass_incc_dfail_decc_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_decc_dfail_decw_comp_greater_back_fail_incc_pass_incc_dfail_inv_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_keep_dfail_repl_comp_never_back_fail_wrap_pass_decc_dfail_decw_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_wrap_dfail_decc_comp_equal_back_fail_wrap_pass_keep_dfail_repl_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_decc_dfail_incc_comp_not_equal_back_fail_keep_pass_wrap_dfail_decc_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_decw_dfail_repl_comp_greater_back_fail_decc_pass_decc_dfail_incc_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_zero_dfail_zero_comp_not_equal_back_fail_decc_pass_decw_dfail_repl_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_keep_dfail_incc_comp_not_equal_back_fail_zero_pass_zero_dfail_zero_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_decc_dfail_incc_comp_always_back_fail_inv_pass_keep_dfail_incc_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_decc_dfail_incc_comp_greater_back_fail_keep_pass_decc_dfail_incc_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_incc_dfail_wrap_comp_greater_back_fail_zero_pass_decc_dfail_incc_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_repl_pass_keep_dfail_wrap_comp_less_or_equal_back_fail_zero_pass_incc_dfail_wrap_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_wrap_dfail_decw_comp_not_equal_back_fail_repl_pass_keep_dfail_wrap_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_repl_pass_incc_dfail_inv_comp_less_back_fail_wrap_pass_wrap_dfail_decw_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_incc_dfail_keep_comp_less_back_fail_repl_pass_incc_dfail_inv_comp_less
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_inv_dfail_zero_comp_not_equal_back_fail_inv_pass_incc_dfail_keep_comp_less
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_wrap_dfail_wrap_comp_less_or_equal_back_fail_incc_pass_inv_dfail_zero_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_zero_dfail_wrap_comp_greater_or_equal_back_fail_wrap_pass_wrap_dfail_wrap_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_repl_pass_decc_dfail_repl_comp_equal_back_fail_inv_pass_zero_dfail_wrap_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_keep_dfail_repl_comp_always_back_fail_repl_pass_decc_dfail_repl_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_inv_dfail_decw_comp_never_back_fail_zero_pass_keep_dfail_repl_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decw_pass_incc_dfail_incc_comp_equal_back_fail_incc_pass_inv_dfail_decw_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_decw_dfail_inv_comp_equal_back_fail_decw_pass_incc_dfail_incc_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_wrap_dfail_zero_comp_greater_or_equal_back_fail_zero_pass_decw_dfail_inv_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_repl_dfail_inv_comp_less_back_fail_decc_pass_wrap_dfail_zero_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_zero_dfail_zero_comp_greater_or_equal_back_fail_wrap_pass_repl_dfail_inv_comp_less
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decw_pass_keep_dfail_wrap_comp_always_back_fail_incc_pass_zero_dfail_zero_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_zero_dfail_keep_comp_never_back_fail_decw_pass_keep_dfail_wrap_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_decc_dfail_keep_comp_less_or_equal_back_fail_inv_pass_zero_dfail_keep_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_wrap_dfail_keep_comp_never_back_fail_decc_pass_decc_dfail_keep_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_keep_dfail_wrap_comp_greater_back_fail_keep_pass_wrap_dfail_keep_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_decw_dfail_wrap_comp_equal_back_fail_inv_pass_keep_dfail_wrap_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_repl_dfail_inv_comp_never_back_fail_zero_pass_decw_dfail_wrap_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_repl_dfail_decw_comp_greater_or_equal_back_fail_wrap_pass_repl_dfail_inv_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_inv_dfail_keep_comp_greater_or_equal_back_fail_inv_pass_repl_dfail_decw_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_wrap_dfail_repl_comp_never_back_fail_wrap_pass_inv_dfail_keep_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_decw_dfail_repl_comp_greater_or_equal_back_fail_wrap_pass_wrap_dfail_repl_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decw_pass_wrap_dfail_decw_comp_greater_back_fail_decc_pass_decw_dfail_repl_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_repl_dfail_incc_comp_never_back_fail_decw_pass_wrap_dfail_decw_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_zero_dfail_inv_comp_always_back_fail_keep_pass_repl_dfail_incc_comp_never
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_decw_dfail_repl_comp_equal_back_fail_keep_pass_zero_dfail_inv_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_repl_dfail_decc_comp_greater_back_fail_decc_pass_decw_dfail_repl_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_incc_dfail_keep_comp_not_equal_back_fail_inv_pass_repl_dfail_decc_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_wrap_dfail_inv_comp_always_back_fail_decc_pass_incc_dfail_keep_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_inv_dfail_inv_comp_greater_or_equal_back_fail_keep_pass_wrap_dfail_inv_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_decc_dfail_zero_comp_always_back_fail_wrap_pass_inv_dfail_inv_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_keep_dfail_wrap_comp_greater_or_equal_back_fail_zero_pass_decc_dfail_zero_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_decw_dfail_decc_comp_always_back_fail_decc_pass_keep_dfail_wrap_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_wrap_dfail_repl_comp_not_equal_back_fail_keep_pass_decw_dfail_decc_comp_always
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_decc_dfail_wrap_comp_equal_back_fail_decc_pass_wrap_dfail_repl_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_repl_pass_zero_dfail_keep_comp_less_or_equal_back_fail_zero_pass_decc_dfail_wrap_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_wrap_pass_decc_dfail_decw_comp_equal_back_fail_repl_pass_zero_dfail_keep_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decc_pass_zero_dfail_wrap_comp_greater_or_equal_back_fail_wrap_pass_decc_dfail_decw_comp_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decw_pass_zero_dfail_incc_comp_greater_or_equal_back_fail_decc_pass_zero_dfail_wrap_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decw_pass_wrap_dfail_repl_comp_not_equal_back_fail_decw_pass_zero_dfail_incc_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_keep_pass_keep_dfail_keep_comp_greater_or_equal_back_fail_decw_pass_wrap_dfail_repl_comp_not_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_repl_pass_decc_dfail_incc_comp_less_or_equal_back_fail_keep_pass_keep_dfail_keep_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_repl_pass_decc_dfail_inv_comp_greater_or_equal_back_fail_repl_pass_decc_dfail_incc_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_keep_dfail_incc_comp_greater_or_equal_back_fail_repl_pass_decc_dfail_inv_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_repl_pass_zero_dfail_inv_comp_greater_or_equal_back_fail_inv_pass_keep_dfail_incc_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_incc_pass_decw_dfail_repl_comp_less_or_equal_back_fail_repl_pass_zero_dfail_inv_comp_greater_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_inv_pass_incc_dfail_wrap_comp_greater_back_fail_incc_pass_decw_dfail_repl_comp_less_or_equal
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_decw_pass_repl_dfail_keep_comp_greater_back_fail_inv_pass_incc_dfail_wrap_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_zero_pass_decw_dfail_repl_comp_equal_back_fail_decw_pass_repl_dfail_keep_comp_greater
-dEQP-VK.pipeline.stencil.format.s8_uint.states.front_fail_repl_pass_decw_dfail_keep_comp_less_back_fail_zero_pass_decw_dfail_repl_comp_equal
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+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_incc.comp_not_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_incc.comp_greater_or_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_incc.comp_always
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decc.comp_never
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decc.comp_less
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decc.comp_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decc.comp_less_or_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decc.comp_greater
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decc.comp_not_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decc.comp_greater_or_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decc.comp_always
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_inv.comp_never
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_inv.comp_less
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_inv.comp_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_inv.comp_less_or_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_inv.comp_greater
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_inv.comp_not_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_inv.comp_greater_or_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_inv.comp_always
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_wrap.comp_never
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_wrap.comp_less
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_wrap.comp_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_wrap.comp_less_or_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_wrap.comp_greater
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_wrap.comp_not_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_wrap.comp_greater_or_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_wrap.comp_always
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decw.comp_never
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decw.comp_less
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decw.comp_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decw.comp_less_or_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decw.comp_greater
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decw.comp_not_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decw.comp_greater_or_equal
+dEQP-VK.pipeline.stencil.format.d32_sfloat_s8_uint.states.fail_decw.pass_decw.dfail_decw.comp_always
 dEQP-VK.pipeline.blend.format.r4g4_unorm_pack8.states.color_dc_sas_rsub_alpha_1mdc_1msc_sub-color_1msa_1msc_add_alpha_ca_da_min-color_1msc_da_sub_alpha_1mca_ca_sub-color_o_1mda_max_alpha_sa_dc_min
 dEQP-VK.pipeline.blend.format.r4g4_unorm_pack8.states.color_sas_1mda_rsub_alpha_1mda_1mcc_sub-color_1mda_1mca_min_alpha_o_cc_min-color_1mdc_da_min_alpha_1mda_da_min-color_sas_1msa_max_alpha_sas_o_min
 dEQP-VK.pipeline.blend.format.r4g4_unorm_pack8.states.color_ca_1mcc_rsub_alpha_sa_1msc_rsub-color_1mca_ca_rsub_alpha_1msc_da_rsub-color_1mcc_1mdc_sub_alpha_z_da_sub-color_sc_dc_add_alpha_1mdc_1msa_min
@@ -65650,7 +65650,6 @@ dEQP-VK.binding_model.shader_access.secondary_cmd_buf.storage_buffer_dynamic.ver
 dEQP-VK.binding_model.shader_access.secondary_cmd_buf.storage_buffer_dynamic.vertex_fragment.descriptor_array.offset_view_zero_dynamic_nonzero
 dEQP-VK.binding_model.shader_access.secondary_cmd_buf.storage_buffer_dynamic.vertex_fragment.descriptor_array.offset_view_nonzero_dynamic_zero
 dEQP-VK.binding_model.shader_access.secondary_cmd_buf.storage_buffer_dynamic.vertex_fragment.descriptor_array.offset_view_nonzero_dynamic_nonzero
-dEQP-VK.spirv_assembly.instruction.compute.opnop.all
 dEQP-VK.spirv_assembly.instruction.compute.opline.all
 dEQP-VK.spirv_assembly.instruction.compute.opnoline.all
 dEQP-VK.spirv_assembly.instruction.compute.opconstantnull.bool