platform/kernel/u-boot.git
9 years agoPrepare v2015.01-rc4 v2015.01-rc4
Tom Rini [Tue, 30 Dec 2014 02:22:38 +0000 (21:22 -0500)]
Prepare v2015.01-rc4

Signed-off-by: Tom Rini <trini@ti.com>
9 years agobuildman: Fix some typos in README
Dirk Behme [Tue, 23 Dec 2014 06:41:26 +0000 (07:41 +0100)]
buildman: Fix some typos in README

Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agoFix hash verification
Nikolay Dimitrov [Fri, 12 Dec 2014 18:01:23 +0000 (20:01 +0200)]
Fix hash verification

Fix issue in parse_verify_sum() which swaps handling of env-var and *address.
Move hash_command() argc check earlier.
Cosmetic change on do_hash() variable declaration.
Improved help message for "hash" command.

Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Reviewed-by: Simon Glass <sjg@chromium.org>
9 years agocommon/board_f.c: fix compile error when tracing disabled
Kevin Hilman [Tue, 9 Dec 2014 23:03:58 +0000 (15:03 -0800)]
common/board_f.c: fix compile error when tracing disabled

When CONFIG_TRACE is disabled, linking fails with:

common/built-in.o:(.data.init_sequence_f+0x8): undefined reference to `trace_early_init'

To fix, wrap the call to trace_early_init() with #ifdef CONFIG_TRACE.

Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@ti.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
9 years agobcm281xx: add support for "USB OTG clock"
Steve Rae [Tue, 9 Dec 2014 19:40:11 +0000 (11:40 -0800)]
bcm281xx: add support for "USB OTG clock"

enable this clock with the following:
  clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)

Signed-off-by: Steve Rae <srae@broadcom.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
9 years agoinitcall: add explicit hint if initcall was relocated
Alexey Brodkin [Sat, 27 Dec 2014 22:35:57 +0000 (01:35 +0300)]
initcall: add explicit hint if initcall was relocated

Commit "initcall: Improve debugging support" makes sense and indeed
simplifies process of matching initcalls executed with static
disassembly.

Until you are debugging relocation functionality.

Existign output may make you think that at some point execution somehow
returned back to non-relocated area. And there're many reasons/problems
that may provoke this behavior.

In order to make things clear let's add explicit mention in case initall
was actually relocated like this:
--->---
initcall: 810015f8
Relocation Offset is: 0efcf000
Relocating to 8ffcf000, new gd at 8fdced3c, sp at 8fdced20
initcall: 810015b8
initcall: 8ffd093c
initcall: 8ffd0a14
initcall: 81001940 (relocated to 8ffd0940)
initcall: 81001958 (relocated to 8ffd0958)
--->---

Note "unexpected" jump from 0x8f... area to 0x81... area.
Without explanation this raises many questions: execution jumped in
relocated area right as expected and then for some reason returned back?

But I hope comment in brackets will save some time for those curious
developers who are careful enough to catch "unexpected jump to pre-reloc
area" or those unlucky ones who'll have to deal with relocation
debugging.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Minkyu Kang <mk7.kang@samsung.com>
9 years agoscripts: fix binutils-version.sh
Masahiro Yamada [Thu, 25 Dec 2014 02:09:44 +0000 (11:09 +0900)]
scripts: fix binutils-version.sh

The current binutils-version.sh expects the version string at the end
of the first line.  It turned out to not work with Linaro toolchain:
It has "Linaro 2014.09" at the back.

To fix this issue, let's parse the word right after the close
parenthesis.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Reported-by: York Sun <yorksun@freescale.com>
Acked-by: Dirk Behme <dirk.behme@gmail.com>
9 years agoARM: rpi: consolidate board rev error checking
Stephen Warren [Wed, 24 Dec 2014 03:01:44 +0000 (20:01 -0700)]
ARM: rpi: consolidate board rev error checking

Create a fake model table entry with default values, so we can error
check the board rev value once when querying it from the firmware, rather
than error-checking for invalid board rev values every time the model
table is used.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
9 years agoARM: rpi: support model A+
Stephen Warren [Wed, 24 Dec 2014 03:01:43 +0000 (20:01 -0700)]
ARM: rpi: support model A+

Add a board rev entry for the new model A+, and augment the board
rev error handling code to be a bit more verbose.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
9 years agoARM: rpi: only set usbethaddr on relevant systems
Stephen Warren [Sat, 6 Dec 2014 03:56:46 +0000 (20:56 -0700)]
ARM: rpi: only set usbethaddr on relevant systems

Model A and CM RPis don't have an on-board USB Ethernet device. Hence,
there's no point setting $usbethaddr based on the device fuses. Use the
model detection code to gate this. Note that the fuses are actually
programmed even on those devices though.

Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
9 years agovexpress64: switch to generic board
Linus Walleij [Wed, 24 Dec 2014 01:02:46 +0000 (02:02 +0100)]
vexpress64: switch to generic board

The few Versatile Express ARMv8 platforms we have may just as
well be switched to generic board from the beginning.

Tested on the ARM foundation model and the in progress support
for the ARMv8 Juno board.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Steve Rae <srae@broadcom.com>
9 years agovexpress64: take over maintenance of the semi vexpress64
Linus Walleij [Wed, 24 Dec 2014 01:02:19 +0000 (02:02 +0100)]
vexpress64: take over maintenance of the semi vexpress64

As agreed with Steve Rae I'm taking over maintenance of the
semihosted, emulated FVP/foundation model Versatile Express
64 bit board variant.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Steve Rae <srae@broadcom.com>
9 years agoarm: semihosting: get rid of forward declarations
Linus Walleij [Mon, 15 Dec 2014 10:06:05 +0000 (11:06 +0100)]
arm: semihosting: get rid of forward declarations

By rearranging the functions in the semihosting code we can
avoid forward-declaration of the internal static functions.
This puts the stuff in a logical order: read/open/close/len
and then higher-order functions follow at the end.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agoarm: semihosting: fix up compile bugs
Linus Walleij [Mon, 15 Dec 2014 10:05:56 +0000 (11:05 +0100)]
arm: semihosting: fix up compile bugs

There is currently a regression when using newer ARM64 compilers
for semihosting: the way long types are inferred from context
is no longer the same.

The semihosting runtime uses long and size_t, so use this
explicitly in the semihosting code and interface, and voila:
the code now works again.

Tested with aarch64-linux-gnu-gcc: Linaro GCC 4.9-2014.09.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Suggested-by: Mark Hambleton <mark.hambleton@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agoarm: semihosting: staticize internal functions
Linus Walleij [Mon, 15 Dec 2014 10:05:43 +0000 (11:05 +0100)]
arm: semihosting: staticize internal functions

The semihosting code exposes internal file handle handling
functions to read(), open(), close() and get the length of
a certain file handle.

However the code using it is only interested in either
reading and entire named file into memory or getting the
file length of a file referred by name. No file handles
are used.

Thus make the file handle code internal to this file by
removing these functions from the semihosting header file
and staticize them.

This gives us some freedom to rearrange the semihosting
code without affecting the external interface.

Cc: Darwin Rambo <drambo@broadcom.com>
Cc: AKASHI Takahiro <takahiro.akashi@linaro.org>
Cc: Mark Hambleton <mark.hambleton@arm.com>
Cc: Tom Rini <trini@ti.com>
Acked-by: Steve Rae <srae@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
9 years agoMerge branch 'rmobile' of git://git.denx.de/u-boot-sh
Tom Rini [Mon, 29 Dec 2014 03:09:27 +0000 (22:09 -0500)]
Merge branch 'rmobile' of git://git.denx.de/u-boot-sh

9 years agoarm: rmobile: kconfig: Remove '+S:' prefix from defconfig files
Nobuhiro Iwamatsu [Mon, 10 Nov 2014 00:23:46 +0000 (09:23 +0900)]
arm: rmobile: kconfig: Remove '+S:' prefix from defconfig files

'+S' is unnecessary because boards of rmobile do not use SPL.
This removes from armadillo-800eva and kzm9g.

Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
9 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Fri, 19 Dec 2014 22:09:26 +0000 (17:09 -0500)]
Merge git://git.denx.de/u-boot-x86

9 years agox86: Add a script to process Intel microcode files
Simon Glass [Wed, 17 Dec 2014 03:21:02 +0000 (20:21 -0700)]
x86: Add a script to process Intel microcode files

Intel delivers microcode updates in a microcode.dat file which must be
split up into individual files for each CPU. Add a tool which performs
this task. It can list available microcode updates for each model and
produce a new microcode update in U-Boot's .dtsi format.

Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: Clean up the FSP support codes
Bin Meng [Wed, 17 Dec 2014 07:50:49 +0000 (15:50 +0800)]
x86: Clean up the FSP support codes

This is the follow-on patch to clean up the FSP support codes:

- Remove the _t suffix on the structures defines
- Use __packed for structure defines
- Use U-Boot's assert()
- Use standard bool true/false
- Remove read_unaligned64()
- Use memcmp() in the compare_guid()
- Remove the cast in the memset() call
- Replace some magic numbers with macros
- Use panic() when no valid FSP image header is found
- Change some FSP utility routines to use an fsp_ prefix
- Add comment blocks for asm_continuation and fsp_init_done
- Remove some casts in find_fsp_header()
- Change HOB access macros to static inline routines
- Add comments to mention find_fsp_header() may be called in a
  stackless environment
- Add comments to mention init(&params) in fsp_init() cannot
  be removed

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add a README.x86 for U-Boot on x86 support
Bin Meng [Wed, 17 Dec 2014 07:50:48 +0000 (15:50 +0800)]
x86: Add a README.x86 for U-Boot on x86 support

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Use 'Link' as the name for the Chromebook Pixel consistently)

Change-Id: I158c88653978ff212334f6d4ffeaf49fa81baefe

9 years agox86: Rename coreboot-serial to x86-serial
Bin Meng [Wed, 17 Dec 2014 07:50:47 +0000 (15:50 +0800)]
x86: Rename coreboot-serial to x86-serial

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: crownbay: Add SDHCI support
Bin Meng [Wed, 17 Dec 2014 07:50:46 +0000 (15:50 +0800)]
x86: crownbay: Add SDHCI support

There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: crownbay: Enable Intel E1000 NIC support
Bin Meng [Wed, 17 Dec 2014 07:50:45 +0000 (15:50 +0800)]
x86: crownbay: Enable Intel E1000 NIC support

We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: crownbay: Add SPI flash support
Bin Meng [Wed, 17 Dec 2014 07:50:44 +0000 (15:50 +0800)]
x86: crownbay: Add SPI flash support

The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Include FSP and CMC binary in the u-boot.rom build rules
Bin Meng [Wed, 17 Dec 2014 07:50:43 +0000 (15:50 +0800)]
x86: Include FSP and CMC binary in the u-boot.rom build rules

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Use consistent name XXX_ADDR for binary blob flash address
Bin Meng [Wed, 17 Dec 2014 07:50:42 +0000 (15:50 +0800)]
x86: Use consistent name XXX_ADDR for binary blob flash address

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add crownbay defconfig and config.h
Bin Meng [Wed, 17 Dec 2014 07:50:41 +0000 (15:50 +0800)]
x86: Add crownbay defconfig and config.h

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add queensbay and crownbay Kconfig files
Bin Meng [Wed, 17 Dec 2014 07:50:40 +0000 (15:50 +0800)]
x86: Add queensbay and crownbay Kconfig files

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Enable the queensbay cpu directory build
Bin Meng [Wed, 17 Dec 2014 07:50:39 +0000 (15:50 +0800)]
x86: Enable the queensbay cpu directory build

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: ich6-gpio: Add Intel Tunnel Creek GPIO support
Bin Meng [Wed, 17 Dec 2014 07:50:38 +0000 (15:50 +0800)]
x86: ich6-gpio: Add Intel Tunnel Creek GPIO support

Intel Tunnel Creek GPIO register block is compatible with current
ich6-gpio driver, except the offset and content of GPIO block base
address register in the LPC PCI configuration space are different.

Use u16 instead of u32 to store the 16-bit I/O address of the GPIO
registers so that it could support both Ivybridge and Tunnel Creek.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Convert microcode format to device-tree-only
Simon Glass [Wed, 17 Dec 2014 07:50:37 +0000 (15:50 +0800)]
x86: Convert microcode format to device-tree-only

To avoid having two microcode formats, adjust the build system to support
obtaining the microcode from the device tree, even in the case where it
must be made available before the device tree can be accessed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: Add basic support to queensbay platform and crownbay board
Bin Meng [Wed, 17 Dec 2014 07:50:36 +0000 (15:50 +0800)]
x86: Add basic support to queensbay platform and crownbay board

Implement minimum required functions for the basic support to
queensbay platform and crownbay board.

Currently the implementation is to call fsp_init() in the car_init().
We may move that call to cpu_init_f() in the future.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Integrate Tunnel Creek processor microcode
Bin Meng [Wed, 17 Dec 2014 07:50:35 +0000 (15:50 +0800)]
x86: Integrate Tunnel Creek processor microcode

Integrate the processor microcode version 1.05 for Tunnel Creek,
CPUID device 20661h.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Correct problems in the microcode loading
Simon Glass [Tue, 16 Dec 2014 05:02:41 +0000 (22:02 -0700)]
x86: Correct problems in the microcode loading

There are several problems in the code. The device tree decode is incorrect
in ways that are masked due to a matching bug. Both are fixed. Also
microcode_read_rev() should be inline and called before the microcode is
written.

Note: microcode writing does not work correctly on ivybridge for me. Further
work is needed to resolve this. But this patch tidies up the existing code
so that will be easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: ivybridge: Update the microcode
Simon Glass [Tue, 16 Dec 2014 05:02:40 +0000 (22:02 -0700)]
x86: ivybridge: Update the microcode

There are new microcode revisions available. Update them. Also change
the format so that the first 48 bytes are not omitted from the device tree
data.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agox86: Move microcode updates into a separate directory
Simon Glass [Tue, 16 Dec 2014 05:02:39 +0000 (22:02 -0700)]
x86: Move microcode updates into a separate directory

We might end up with a few of these, so put them in their own directory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: ifdtool: Add support for early microcode access
Simon Glass [Tue, 16 Dec 2014 05:02:38 +0000 (22:02 -0700)]
x86: ifdtool: Add support for early microcode access

Some Intel CPUs use an 'FSP' binary blob which provides an inflexible
means of starting up the CPU. One result is that microcode updates can only
be done before RAM is available and therefore parsing of the device tree
is impracticle.

Worse, the addess of the microcode update must be stored in ROM since a
pointer to its start address and size is passed to the 'FSP' blob. It is
not possible to perform any calculations to obtain the address and size.

To work around this, ifdtool is enhanced to work out the address and size of
the first microcode update it finds in the supplied device tree. It then
writes these into the correct place in the ROM. U-Boot can then start up
the FSP correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: ifdtool: Use a structure for the file/address list
Simon Glass [Mon, 15 Dec 2014 00:15:37 +0000 (17:15 -0700)]
x86: ifdtool: Use a structure for the file/address list

Rather than two independent arrays, use a single array of a suitable
structure. Also add a 'type' member since we will shortly add additional
types.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: ifdtool: Display filename when file errors are reported
Simon Glass [Mon, 15 Dec 2014 00:15:36 +0000 (17:15 -0700)]
x86: ifdtool: Display filename when file errors are reported

When a file is missing it helps to know which file. Update the error message
to print this information.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: ifdtool: Correct a debug() missing parameter
Simon Glass [Mon, 15 Dec 2014 00:15:35 +0000 (17:15 -0700)]
x86: ifdtool: Correct a debug() missing parameter

This is missing a parameter. Fix it to avoid a warning when debug is
enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Thu, 18 Dec 2014 17:37:18 +0000 (12:37 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

9 years agoARM: UniPhier: enable CONFIG_CMD_DM
Masahiro Yamada [Thu, 18 Dec 2014 10:11:04 +0000 (19:11 +0900)]
ARM: UniPhier: enable CONFIG_CMD_DM

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: select CONFIG_SPL
Masahiro Yamada [Thu, 18 Dec 2014 10:11:03 +0000 (19:11 +0900)]
ARM: UniPhier: select CONFIG_SPL

Now UniPhier platform is only supported with SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: use DRAM area for init stack of normal image
Masahiro Yamada [Thu, 18 Dec 2014 10:11:02 +0000 (19:11 +0900)]
ARM: UniPhier: use DRAM area for init stack of normal image

The normal image is working on DRAM.  It is better to use DRAM also
for init stack than L2 cache.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: remove unnecessary ifdef conditional
Masahiro Yamada [Thu, 18 Dec 2014 10:11:01 +0000 (19:11 +0900)]
ARM: UniPhier: remove unnecessary ifdef conditional

init_page_table is only set on SPL.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agoARM: UniPhier: fix property names of aliases nodes of device trees
Masahiro Yamada [Thu, 18 Dec 2014 10:11:00 +0000 (19:11 +0900)]
ARM: UniPhier: fix property names of aliases nodes of device trees

The property name of the "aliases" node should be "serial*"
to assign a desired number for the device sequence number.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
9 years agofastboot: handle flash write to GPT partitions
Steve Rae [Fri, 12 Dec 2014 23:51:54 +0000 (15:51 -0800)]
fastboot: handle flash write to GPT partitions

Implement a feature to allow fastboot to write the downloaded image
to the space reserved for the Protective MBR and the Primary GUID
Partition Table.
Additionally, prepare and write the Backup GUID Partition Table.

Signed-off-by: Steve Rae <srae@broadcom.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[Test HW: Exynos4412 - Trats2]

9 years agodisk: part_efi: move code to static functions
Steve Rae [Thu, 18 Dec 2014 11:13:42 +0000 (12:13 +0100)]
disk: part_efi: move code to static functions

Signed-off-by: Steve Rae <srae@broadcom.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[Test HW: Exynos4412 - Trats2]

9 years agodfu: dfu_get_buf: check the value of env dfu_bufsiz before use
Przemyslaw Marczak [Mon, 15 Dec 2014 09:34:11 +0000 (10:34 +0100)]
dfu: dfu_get_buf: check the value of env dfu_bufsiz before use

In function dfu_get_buf(), the size of allocated buffer could
be defined by the env variable. The size from this variable
was passed for memalign() without checking its value.
And the the memalign will return non null pointer for size 0.

This could possibly cause data abort, so now the value of var
is checked before use. And if this variable is set to 0 then
the default size will be used.

This commit also changes the base passed to simple_strtoul()
to 0. Now decimal and hex values can be used for the variable
dfu_bufsiz.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]

9 years agogadget: f_thor: check pointers before use in download_tail()
Przemyslaw Marczak [Mon, 15 Dec 2014 09:34:10 +0000 (10:34 +0100)]
gadget: f_thor: check pointers before use in download_tail()

Some pointers in function download_tail() were not checked
before the use. This could possibly cause the data abort.
To avoid this, check if the pointers are not null is added.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]

9 years agodfu: mmc: check if mmc device exists in mmc_block_op()
Przemyslaw Marczak [Mon, 15 Dec 2014 09:34:09 +0000 (10:34 +0100)]
dfu: mmc: check if mmc device exists in mmc_block_op()

The function mmc_block_op() is the last function before
the physicall data write, but the mmc device pointer is not
checked. If mmc device not exists, then data abort will occur.
To avoid this, first the mmc device pointer is checked.

Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]

9 years agofastboot: add support for continue command
Rob Herring [Wed, 10 Dec 2014 20:43:04 +0000 (14:43 -0600)]
fastboot: add support for continue command

The fastboot continue command is defined to exit fastboot and continue
autoboot. This commit implements the continue command and the exiting of
fastboot only. Subsequent u-boot commands can be processed after exiting
fastboot. Autoboot should implement a boot script such as "fastboot; mmc
read <...>; bootm" to fully implement the fastboot continue function.

Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]

9 years agousb, g_dnl: generalize DFU detach functions
Rob Herring [Wed, 10 Dec 2014 20:43:03 +0000 (14:43 -0600)]
usb, g_dnl: generalize DFU detach functions

In order to add detach functions for fastboot, make the DFU detach related
functions common so they can be shared.

Signed-off-by: Rob Herring <robh@kernel.org>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
[TestHW: Exynos4412-Trats2]

9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Tom Rini [Tue, 16 Dec 2014 20:20:02 +0000 (15:20 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

9 years agoUSB: gadget: atmel_usba_udc: fix transfer hang issue
Bo Shen [Mon, 15 Dec 2014 10:12:47 +0000 (18:12 +0800)]
USB: gadget: atmel_usba_udc: fix transfer hang issue

When receive data, the RXRDY in status register set by hardware
after a new packet has been stored in the endpoint FIFO. After,
we copy from FIFO, we clear it, make the FIFO can be accessed
again.
In the receive_data() function, this bit RXRDY has been cleared.
So, after the receive_data() function return, this bit should
not be cleared again, or else it will cause the accessing FIFO
corrupt, which will make the data loss.

Signed-off-by: Bo Shen <voice.shen@atmel.com>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Tue, 16 Dec 2014 14:41:00 +0000 (09:41 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

9 years agoarm: socfpga: board: Repair Micrel PHY tuning
Pavel Machek [Thu, 11 Dec 2014 17:06:31 +0000 (18:06 +0100)]
arm: socfpga: board: Repair Micrel PHY tuning

Add proper error checking into the PHY tuning patch. Make the PHY tunning only
happen in case the KSZ9021 PHY is enabled in config. Call the config callback
after the tuning finished.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@opensource.altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Tom Rini <trini@ti.com>
Cc: Pavel Machek <pavel@denx.de>
9 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Mon, 15 Dec 2014 22:13:47 +0000 (17:13 -0500)]
Merge git://git.denx.de/u-boot-x86

9 years agompc85xx/t104xrdb: convert deep sleep to generic board interface
Tang Yuantian [Fri, 21 Nov 2014 03:17:16 +0000 (11:17 +0800)]
mpc85xx/t104xrdb: convert deep sleep to generic board interface

A new interface is introduced to support generic board structure.
Converts it to use new interface.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoqe/deep-sleep: modify qe deep-sleep for generic board
Zhao Qiang [Mon, 15 Dec 2014 07:50:49 +0000 (15:50 +0800)]
qe/deep-sleep: modify qe deep-sleep for generic board

Deep sleep for generic board is supported now, modify qe
deep-sleep code to adapt it.

Signed-off-by: Zhao Qiang <B45475@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agop5040ds: changed liodn offsets
Tudor Laurentiu [Tue, 9 Dec 2014 09:00:19 +0000 (11:00 +0200)]
p5040ds: changed liodn offsets

Offsets were overlaping, causing pamu access violations in
hypervised scenarios.

Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com>
Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agocrypto/fsl: Fix RNG instantiation failure.
gaurav rana [Thu, 4 Dec 2014 07:30:41 +0000 (13:00 +0530)]
crypto/fsl: Fix RNG instantiation failure.

Corrected the order of arguments in memset in run_descriptor
function. Wrong order of argumnets led to improper initialization
of members of struct type result. This resulted in RNG instantiation
error.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/T10xx: Fix number of portals
Jeffrey Ladouceur [Wed, 3 Dec 2014 23:08:43 +0000 (18:08 -0500)]
powerpc/T10xx: Fix number of portals

Following boards has incorrect number of portals defined.
powerpc/T102xQDS
powerpc/T102xRDB
powerpc/T1040QDS
powerpc/T104xRDB

Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agompc85xx: inhibit qman and bman portals by default
Jeffrey Ladouceur [Mon, 8 Dec 2014 19:54:01 +0000 (14:54 -0500)]
mpc85xx: inhibit qman and bman portals by default

Not all portals might be managed and therefore visible.
Set the isdr register so that the corresponding isr register
won't be set. This is required when supporting power management.

Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agonet/fm: update ft_fixup_port to differentiate dual-role mac
Shengzhou Liu [Wed, 3 Dec 2014 07:27:03 +0000 (15:27 +0800)]
net/fm: update ft_fixup_port to differentiate dual-role mac

we need to differentiate dual-role MACs into two types: MACs with
10GEC enumeration consistent with DTSEC enumeration(defined by
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION) and other MACs without
CONFIG_FSL_FM_10GEC_REGULAR_NOTATION defined.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/mpc85xx: Fix DDR TLB mapping leftover
York Sun [Tue, 2 Dec 2014 19:21:09 +0000 (11:21 -0800)]
powerpc/mpc85xx: Fix DDR TLB mapping leftover

Commit f29f804a93e87c17670607641d120f431a3b0633 generalized the TLB
mapping function, but made the DDR mapping leftover size to zero,
causing the message not printed.

Signed-off-by: York Sun <yorksun@freescale.com>
CC: Alexander Graf <agraf@suse.de>
CC: Scott Wood <scottwood@freescale.com>
9 years agodriver/ddr/fsl: Fix MRC_CYC calculation for DDR3
York Sun [Tue, 2 Dec 2014 19:18:09 +0000 (11:18 -0800)]
driver/ddr/fsl: Fix MRC_CYC calculation for DDR3

For DDR controller version 4.7 or newer, MRC_CYC (mode register set
cycle time) is max(tMRD, tMOD). tMRD is 4nCK, or 8nCK (RDIMM). tMOD
is max(12nCK, 15ns) according to JEDEC spec.

DDR4 is not affected by this change.

Signed-off-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/p2041rdb: enable generic board configs
Shaohui Xie [Mon, 1 Dec 2014 07:39:23 +0000 (15:39 +0800)]
powerpc/p2041rdb: enable generic board configs

Add following configs in header file:
CONFIG_SYS_GENERIC_BOARD
CONFIG_DISPLAY_BOARDINFO

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/t4240rdb: Convert to use generic board code
Chunhe Lan [Mon, 1 Dec 2014 08:21:01 +0000 (16:21 +0800)]
powerpc/t4240rdb: Convert to use generic board code

Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agopowerpc/bsc913x: Convert to use generic board code
harninder rai [Tue, 2 Dec 2014 10:25:47 +0000 (15:55 +0530)]
powerpc/bsc913x: Convert to use generic board code

Signed-off-by: Harninder Rai <harninder.rai@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
9 years agoARM: remove redundant asmlinkage define
Masahiro Yamada [Wed, 3 Dec 2014 08:36:58 +0000 (17:36 +0900)]
ARM: remove redundant asmlinkage define

Use asmlinkage defined in include/linux/linkage.h if necessary.
Actually no ARM board uses asmlinkage, so this commit has no impact.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
9 years agox86: move arch-specific asmlinkage to <asm/linkage.h>
Masahiro Yamada [Wed, 3 Dec 2014 08:36:57 +0000 (17:36 +0900)]
x86: move arch-specific asmlinkage to <asm/linkage.h>

Commit 65dd74a674d6 (x86: ivybridge: Implement SDRAM init) introduced
x86-specific asmlinkage into arch/x86/include/asm/config.h.

Commit ed0a2fbf14f7 (x86: Add a definition of asmlinkage) added the
same macro define again, this time, into include/common.h.
(Please do not add arch-specific stuff to include/common.h any more;
it is already too cluttered.)

The generic asmlinkage is defined in <linux/linkage.h>.  If you want
to override it with an arch-specific one, the best way is to add it
to <asm/linkage.h> like Linux Kernel.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add a simple command to show FSP HOB information
Bin Meng [Fri, 12 Dec 2014 13:05:32 +0000 (21:05 +0800)]
x86: Add a simple command to show FSP HOB information

FSP builds a series of data structures called the Hand-Off-Blocks
(HOBs) as it progresses through initializing the silicon. These data
structures conform to the HOB format as described in the Platform
Initialization (PI) specification Volume 3 Shared Architectual
Elements specification, which is part of the UEFI specification.

Create a simple command to parse the HOB list to display the HOB
address, type and length in bytes.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Support Intel FSP initialization path in start.S
Bin Meng [Fri, 12 Dec 2014 13:05:31 +0000 (21:05 +0800)]
x86: Support Intel FSP initialization path in start.S

Per Intel FSP architecture specification, FSP provides 3 routines
for bootloader to call. The first one is the TempRamInit (aka
Cache-As-Ram initialization) and the second one is the FspInit
which does the memory bring up (like MRC for other x86 targets)
and chipset initialization. Those two routines have to be called
before U-Boot jumping to board_init_f in start.S.

The FspInit() will return several memory blocks called Hand Off
Blocks (HOBs) whose format is described in Platform Initialization
(PI) specification (part of the UEFI specication) to the bootloader.
Save this HOB address to the U-Boot global data for later use.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add post failure codes for bist and car
Bin Meng [Fri, 12 Dec 2014 13:05:30 +0000 (21:05 +0800)]
x86: Add post failure codes for bist and car

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: queensbay: Adapt FSP support codes
Bin Meng [Fri, 12 Dec 2014 13:05:29 +0000 (21:05 +0800)]
x86: queensbay: Adapt FSP support codes

Use inline assembly codes to call FspNotify() to make sure parameters
are passed on the stack as required by the FSP calling convention.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: Initial import from Intel FSP release for Queensbay platform
Bin Meng [Fri, 12 Dec 2014 13:05:28 +0000 (21:05 +0800)]
x86: Initial import from Intel FSP release for Queensbay platform

This is the initial import from Intel FSP release for Queensbay
platform (Tunnel Creek processor and Topcliff Platform Controller
Hub), which can be downloaded from Intel website.

For more details, check http://www.intel.com/fsp.

Note: U-Boot coding convention was applied to these codes, so it
looks completely different from the original Intel release.
Also update FSP support codes license header to use SPDX ID.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
9 years agox86: ich-spi: Add Intel Tunnel Creek SPI controller support
Bin Meng [Fri, 12 Dec 2014 13:05:27 +0000 (21:05 +0800)]
x86: ich-spi: Add Intel Tunnel Creek SPI controller support

Add Intel Tunnel Creek SPI controller support which is an ICH7
compatible device.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add Intel Topcliff PCH device IDs
Bin Meng [Fri, 12 Dec 2014 13:05:26 +0000 (21:05 +0800)]
x86: Add Intel Topcliff PCH device IDs

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add a simple superio driver for SMSC LPC47M
Bin Meng [Fri, 12 Dec 2014 13:05:25 +0000 (21:05 +0800)]
x86: Add a simple superio driver for SMSC LPC47M

On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8)
are provided by a superio chip connected to the LPC bus. We must
program the superio chip so that serial ports are available for us.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Add Intel Crown Bay board dts file
Bin Meng [Fri, 12 Dec 2014 13:05:24 +0000 (21:05 +0800)]
x86: Add Intel Crown Bay board dts file

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: ich6-gpio: Move setup_pch_gpios() to board support codes
Bin Meng [Fri, 12 Dec 2014 13:05:23 +0000 (21:05 +0800)]
x86: ich6-gpio: Move setup_pch_gpios() to board support codes

Movie setup_pch_gpios() in the ich6-gpio driver to the board support
codes, so that the driver does not need to know any platform specific
stuff (ie: include the platform specifc chipset header file).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Clean up asm-offsets
Bin Meng [Fri, 12 Dec 2014 13:05:22 +0000 (21:05 +0800)]
x86: Clean up asm-offsets

Move GD_BIST from lib/asm-offsets.c to arch/x86/lib/asm-offsets.c
as it is x86 arch specific stuff. Also remove GENERATED_GD_RELOC_OFF
which is not referenced anymore.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Refactor u-boot.rom build rules
Bin Meng [Fri, 12 Dec 2014 13:05:21 +0000 (21:05 +0800)]
x86: Refactor u-boot.rom build rules

Refactor u-boot.rom build rules by utilizing quiet_cmd_ and cmd_
macros. Also make writing mrc.bin and pci option rom to u-boot.rom
optional and remove mrc.bin from its dependent file list as not
every x86 board port needs mrc binary blob.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: ifdtool: Separate out filenames for -D and -i
Simon Glass [Sun, 14 Dec 2014 05:25:46 +0000 (22:25 -0700)]
x86: ifdtool: Separate out filenames for -D and -i

To allow these options to be specified together, separate them out.

Change-Id: Ib93f11cd51eb3302127f4c82936ff2b44c88d5a2
Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agotools/ifdtool: Support writing multiple files (-w) simultaneously
Bin Meng [Fri, 12 Dec 2014 13:05:20 +0000 (21:05 +0800)]
tools/ifdtool: Support writing multiple files (-w) simultaneously

Currently ifdtool only supports writing one file (-w) at a time.
This looks verbose when generating u-boot.rom for x86 targets.
This change allows at most 16 files to be written simultaneously.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: Make ROM_SIZE configurable in Kconfig
Bin Meng [Fri, 12 Dec 2014 13:05:19 +0000 (21:05 +0800)]
x86: Make ROM_SIZE configurable in Kconfig

Currently the ROM_SIZE is hardcoded to 8MB in arch/x86/Kconfig. This
will not be the case when adding additional board support. Hence we
make ROM_SIZE configurable (512KB/1MB/2MB/4MB/8MB/16MB) and have the
board Kconfig file select the default ROM_SIZE.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: ich-spi: Set the tx operation mode for ich 7
Bin Meng [Fri, 12 Dec 2014 14:06:16 +0000 (19:36 +0530)]
x86: ich-spi: Set the tx operation mode for ich 7

ICH 7 SPI controller only supports byte program (02h) for SST flash.
Word program (ADh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
9 years agox86: ich-spi: Set the rx operation mode for ich 7
Bin Meng [Fri, 12 Dec 2014 14:06:15 +0000 (19:36 +0530)]
x86: ich-spi: Set the rx operation mode for ich 7

ICH 7 SPI controller only supports array read command (03h).
Fast array read command (0Bh) is not supported.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
9 years agosf: Enable byte program support
Jagannadha Sutradharudu Teki [Fri, 12 Dec 2014 14:06:14 +0000 (19:36 +0530)]
sf: Enable byte program support

Enabled byte program support for sst flashes in sf.

Few controllers will only support BP, so this patch gives
a tx transfer flag to set the BP so-that sf will operate
on byte program transfer.

A new TX operation mode SPI_OPM_TX_BP is introduced for such SPI
controller to use byte program op for SST flash.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
9 years agospi: sf: Support byte program for sst spi flash
Bin Meng [Fri, 12 Dec 2014 14:06:13 +0000 (19:36 +0530)]
spi: sf: Support byte program for sst spi flash

Currently if SST flash advertises SST_WP flag in the params table
the word program command (ADh) with auto address increment will be
used for the flash write op. However some SPI controllers do not
support the word program command (like the Intel ICH 7), the byte
programm command (02h) has to be used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
9 years agospi: Fix flag collision for SST_WP
Simon Glass [Fri, 12 Dec 2014 14:06:12 +0000 (19:36 +0530)]
spi: Fix flag collision for SST_WP

At present SECT_4K is the same as SST_WP so we cannot tell these apart. Fix
this so that the table in sf_params.c can be used correctly.

Reported-by: Jens Rottmann <Jens.Rottmann@adlinktech.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
9 years agosf: Fix look for the fastest read command
Jagannadha Sutradharudu Teki [Fri, 12 Dec 2014 14:06:11 +0000 (19:36 +0530)]
sf: Fix look for the fastest read command

Few of the spi controllers are only supports array slow
read which is quite different behaviour compared to others.

So this fix on sf will correctly handle the slow read supported
controllers.

Signed-off-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
9 years agobios_emulator: Correct ordering of includes
Simon Glass [Thu, 11 Dec 2014 03:12:01 +0000 (20:12 -0700)]
bios_emulator: Correct ordering of includes

We should include common.h before other includes. This actually causes
a build error on chromebook_link.

Signed-off-by: Simon Glass <sjg@chromium.org>
9 years agogpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()
Axel Lin [Sun, 7 Dec 2014 04:48:27 +0000 (12:48 +0800)]
gpio: intel_ich6: Set correct gpio output value in ich6_gpio_direction_output()

Current code does not set gpio output value in ich6_gpio_direction_output(),
fix it.

Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Simon Glass <sjg@chromium.org>
9 years agox86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address
Bin Meng [Wed, 10 Dec 2014 08:35:50 +0000 (16:35 +0800)]
x86: ich-spi: Fix a bug of reading from a non-64 bytes aligned address

The ich spi controller driver spi_xfer() tries to align reading
address to 64 bytes when doing spi data in, which causes a bug of
either infinite loop or a huge size memcpy().

Actually the ich spi controller does not have such requirement of
64 bytes alignment when reading data from spi slave devices.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
9 years agoMerge branch 'master' of git://git.denx.de/u-boot-mmc
Tom Rini [Fri, 12 Dec 2014 20:02:00 +0000 (15:02 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-mmc

9 years agommc: dw_mmc: Use active DDR mode flag
Andrew Gabbasov [Mon, 1 Dec 2014 12:59:12 +0000 (06:59 -0600)]
mmc: dw_mmc: Use active DDR mode flag

The card_caps bit should denote the card capability to use DDR mode,
but we need the flag indicating that the DDR mode is active.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>
9 years agommc: Fix block length for DDR mode
Andrew Gabbasov [Mon, 1 Dec 2014 12:59:11 +0000 (06:59 -0600)]
mmc: Fix block length for DDR mode

Block length for write and read commands is fixed to 512 bytes
when the card is in Dual Data Rate mode. If block length read from CSD
is different, make sure the driver will use correct length
in all further calculations and settings.

Signed-off-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>