nand: lpc32xx: add SLC NAND controller support
authorVladimir Zapolskiy <vz@mleia.com>
Sat, 18 Jul 2015 00:07:52 +0000 (03:07 +0300)
committerTom Rini <trini@konsulko.com>
Thu, 13 Aug 2015 00:47:33 +0000 (20:47 -0400)
commitdcfd37e5ef17a3beec212fc4088f14f3fdcba5d1
treea3364f0f66a09564f1aeaafea0a5262fca7675ff
parent8d1809a966996fdbcddb441c0ff8080d78a89c59
nand: lpc32xx: add SLC NAND controller support

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
arch/arm/cpu/arm926ejs/lpc32xx/devices.c
arch/arm/include/asm/arch-lpc32xx/clk.h
arch/arm/include/asm/arch-lpc32xx/sys_proto.h
drivers/mtd/nand/Makefile
drivers/mtd/nand/lpc32xx_nand_slc.c [new file with mode: 0644]