MIPS: start{, 64}.S: fill branch delay slots with NOP instructions
authorGabor Juhos <juhosg@openwrt.org>
Wed, 16 Jan 2013 03:05:01 +0000 (03:05 +0000)
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>
Tue, 22 Jan 2013 20:09:34 +0000 (21:09 +0100)
commit14fdd1a8bfd97de46042cda6086347b0d66461d4
tree6fac1fbe6edbeef3aeda7e874b28ca30829118d6
parent0ef48d4c89788056982772d32d6e97d2b6457abc
MIPS: start{, 64}.S: fill branch delay slots with NOP instructions

The romReserved and romExcHandle handlers are
accessed by a branch instruction however the
delay slots of those instructions are not filled.

Because the start.S uses the 'noreorder' directive,
the assembler will not fill the delay slots either,
and leads to the following assembly code:

  0000056c <romReserved>:
   56c:   1000ffff        b       56c <romReserved>

  00000570 <romExcHandle>:
   570:   1000ffff        b       570 <romExcHandle>

In the resulting code, the second branch instruction
is placed into the delay slot of the first branch
instruction, which is not allowed on the MIPS
architecture.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
arch/mips/cpu/mips32/start.S
arch/mips/cpu/mips64/start.S