X-Git-Url: http://review.tizen.org/git/?p=platform%2Fkernel%2Fu-boot.git;a=blobdiff_plain;f=include%2Fconfigs%2Ftegra20-common.h;h=21bf9771742424dcf4da509e8550a2964b585b0a;hp=098cdb4460d76e8a04ad0af478d0705b4be1c170;hb=HEAD;hpb=d193c1b6eb05041c94ad9aacd8c94189d1dbc5f8 diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h index 098cdb4..a313ac2 100644 --- a/include/configs/tegra20-common.h +++ b/include/configs/tegra20-common.h @@ -1,206 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2010-2012 * NVIDIA Corporation - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA */ -#ifndef __TEGRA20_COMMON_H -#define __TEGRA20_COMMON_H -#include +#ifndef _TEGRA20_COMMON_H_ +#define _TEGRA20_COMMON_H_ +#include "tegra-common.h" /* - * QUOTE(m) will evaluate to a string version of the value of the macro m - * passed in. The extra level of indirection here is to first evaluate the - * macro m before applying the quoting operator. + * NS16550 Configuration */ -#define QUOTE_(m) #m -#define QUOTE(m) QUOTE_(m) +#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ /* - * High Level Configuration Options + * Miscellaneous configurable options */ -#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ -#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ -#define CONFIG_TEGRA /* which is a Tegra generic machine */ -#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ +#define CFG_STACKBASE 0x03800000 /* 56MB */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -#include /* get chip and board defs */ +/*----------------------------------------------------------------------- + * Physical Memory Map + */ /* - * Display CPU and Board information + * Memory layout for where various images get loaded by boot scripts: + * + * scriptaddr can be pretty much anywhere that doesn't conflict with something + * else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with + * something else. Put it above BOOTMAPSZ to eliminate conflicts. + * + * kernel_addr_r must be within the first 128M of RAM in order for the + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r + * should not overlap that area, or the kernel will have to copy itself + * somewhere else before decompression. Similarly, the address of any other + * data passed to the kernel shouldn't overlap the start of RAM. Pushing + * this up to 32M allows for a sizable kernel to be decompressed below the + * compressed load address. + * + * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for + * the compressed kernel to be up to 32M too. + * + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows + * for the FDT/DTB to be up to 1M, which is hopefully plenty. */ -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ +#define MEM_LAYOUT_ENV_SETTINGS \ + "scriptaddr=0x10000000\0" \ + "pxefile_addr_r=0x10100000\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "fdtfile=" FDTFILE "\0" \ + "fdt_addr_r=0x03000000\0" \ + "ramdisk_addr_r=0x03100000\0" #ifdef CONFIG_TEGRA_LP0 #define TEGRA_LP0_ADDR 0x1C406000 #define TEGRA_LP0_SIZE 0x2000 #define TEGRA_LP0_VEC \ - "lp0_vec=" QUOTE(TEGRA_LP0_SIZE) "@" QUOTE(TEGRA_LP0_ADDR) " " + "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ + "@" __stringify(TEGRA_LP0_ADDR) " " #else #define TEGRA_LP0_VEC #endif -/* Environment */ -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ - -/* - * PllX Configuration - */ -#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */ - -/* - * NS16550 Configuration - */ -#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ - -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK - -/* - * select serial console configuration - */ -#define CONFIG_CONS_INDEX 1 - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* - * This parameter affects a TXFILLTUNING field that controls how much data is - * sent to the latency fifo before it is sent to the wire. Without this - * parameter, the default (2) causes occasional Data Buffer Errors in OUT - * packets depending on the buffer address and size. - */ -#define CONFIG_USB_EHCI_TXFIFO_THRESH 10 -#define CONFIG_EHCI_IS_TDI -#define CONFIG_EHCI_DCACHE - -/* Total I2C ports on Tegra20 */ -#define TEGRA_I2C_NUM_CONTROLLERS 4 - -/* include default commands */ -#include - -/* remove unused commands */ -#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ -#undef CONFIG_CMD_FPGA /* FPGA configuration support */ -#undef CONFIG_CMD_IMI -#undef CONFIG_CMD_IMLS -#undef CONFIG_CMD_NFS /* NFS support */ -#undef CONFIG_CMD_NET /* network support */ - -/* turn on command-line edit/hist/auto */ -#define CONFIG_CMDLINE_EDITING -#define CONFIG_COMMAND_HISTORY -#define CONFIG_AUTO_COMPLETE - -#define CONFIG_SYS_NO_FLASH - -/* Environment information, boards can override if required */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define TEGRA_DEVICE_SETTINGS "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */ -#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT V_PROMPT -/* - * Increasing the size of the IO buffer as default nfsargs size is more - * than 256 and so it is not possible to edit it - */ -#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) - -#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */ -#define CONFIG_SYS_HZ 1000 - -#define CONFIG_STACKBASE 0x2800000 /* 40MB */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 NV_PA_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ - -#define CONFIG_SYS_TEXT_BASE 0x0010c000 -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 - -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE -#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ - CONFIG_SYS_INIT_RAM_SIZE - \ - GENERATED_GBL_DATA_SIZE) - -#define CONFIG_TEGRA_GPIO -#define CONFIG_CMD_GPIO -#define CONFIG_CMD_ENTERRCM -#define CONFIG_CMD_BOOTZ - -/* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_NAND_SIMPLE -#define CONFIG_SPL_TEXT_BASE 0x00108000 -#define CONFIG_SPL_MAX_SIZE 0x00004000 -#define CONFIG_SYS_SPL_MALLOC_START 0x00090000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 -#define CONFIG_SPL_STACK 0x000ffffc - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds" - -#define CONFIG_SYS_NAND_SELF_INIT - -#endif /* __TEGRA20_COMMON_H */ +#endif /* _TEGRA20_COMMON_H_ */