X-Git-Url: http://review.tizen.org/git/?p=platform%2Fkernel%2Fu-boot.git;a=blobdiff_plain;f=include%2Fconfigs%2Fcorvus.h;h=6171060e9cd41ae9396a657e03508d1df166e0ed;hp=5347115a14c3056c9ad95a2201708f1c39ace36d;hb=HEAD;hpb=2abf048ab7b835787d6627423559832f2b18f253

diff --git a/include/configs/corvus.h b/include/configs/corvus.h
index 5347115..f2675e0 100644
--- a/include/configs/corvus.h
+++ b/include/configs/corvus.h
@@ -17,88 +17,56 @@
 #include <linux/sizes.h>
 
 /*
- * Warning: changing CONFIG_SYS_TEXT_BASE requires
+ * Warning: changing CONFIG_TEXT_BASE requires
  * adapting the initial boot program.
  * Since the linker has to swallow that define, we must use a pure
  * hex number here!
  */
 
-#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
-
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
-#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
-
-/* general purpose I/O */
-#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
-#define CONFIG_AT91_GPIO_PULLUP	1	/* keep pullups on peripheral pins */
+#define CFG_SYS_AT91_SLOW_CLOCK      32768
+#define CFG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */
 
 /* serial console */
-#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
-#define CONFIG_USART_ID			ATMEL_ID_SYS
-
-/* LED */
-#define CONFIG_AT91_LED
-#define CONFIG_RED_LED		AT91_PIN_PD31	/* this is the user1 led */
-#define CONFIG_GREEN_LED	AT91_PIN_PD0	/* this is the user2 led */
+#define CFG_USART_BASE		ATMEL_BASE_DBGU
+#define CFG_USART_ID			ATMEL_ID_SYS
 
 /* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
-#define CONFIG_SYS_SDRAM_SIZE		0x08000000
-
-#define CONFIG_SYS_INIT_SP_ADDR \
-	(CONFIG_SYS_SDRAM_BASE + SZ_32K - GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_SDRAM_BASE           ATMEL_BASE_CS6
+#define CFG_SYS_SDRAM_SIZE		0x08000000
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE		1
-#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
-#define CONFIG_SYS_NAND_DBW_8
+#define CFG_SYS_NAND_BASE			ATMEL_BASE_CS3
 /* our ALE is AD21 */
-#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+#define CFG_SYS_NAND_MASK_ALE		(1 << 21)
 /* our CLE is AD22 */
-#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8
+#define CFG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CFG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
+#define CFG_SYS_NAND_READY_PIN		AT91_PIN_PC8
 #endif
 
-/* Ethernet */
-#define CONFIG_RMII
-#define CONFIG_NET_RETRY_COUNT		20
-#define CONFIG_AT91_WANTS_COMMON_PHY
-
 /* DFU class support */
 #define DFU_MANIFEST_POLL_TIMEOUT	25000
 
 /* bootstrap + u-boot + env in nandflash */
 
 /* Defines for SPL */
-#define CONFIG_SPL_MAX_SIZE		(12 * SZ_1K)
-#define CONFIG_SPL_STACK		(SZ_16K)
-
-#define CONFIG_SPL_BSS_START_ADDR	CONFIG_SPL_MAX_SIZE
-#define CONFIG_SPL_BSS_MAX_SIZE		(SZ_2K)
 
-#define CONFIG_SPL_NAND_RAW_ONLY
-#define CONFIG_SPL_NAND_SOFTECC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
-#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define	CFG_SYS_NAND_U_BOOT_START	CONFIG_TEXT_BASE
+#define CFG_SYS_NAND_U_BOOT_DST	CONFIG_TEXT_BASE
 
-#define CONFIG_SYS_NAND_ECCSIZE		256
-#define CONFIG_SYS_NAND_ECCBYTES	3
-#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+#define CFG_SYS_NAND_ECCSIZE		256
+#define CFG_SYS_NAND_ECCBYTES	3
+#define CFG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
 					  48, 49, 50, 51, 52, 53, 54, 55, \
 					  56, 57, 58, 59, 60, 61, 62, 63, }
 
-#define CONFIG_SPL_ATMEL_SIZE
-#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CFG_SYS_MASTER_CLOCK		132096000
 #define AT91_PLL_LOCK_TIMEOUT		1000000
-#define CONFIG_SYS_AT91_PLLA		0x20c73f03
-#define CONFIG_SYS_MCKR			0x1301
-#define CONFIG_SYS_MCKR_CSS		0x1302
-
-#define CONFIG_SPL_PAD_TO		CONFIG_SYS_NAND_U_BOOT_OFFS
-#define CONFIG_SYS_SPL_LEN		CONFIG_SPL_PAD_TO
+#define CFG_SYS_AT91_PLLA		0x20c73f03
+#define CFG_SYS_MCKR			0x1301
+#define CFG_SYS_MCKR_CSS		0x1302
 
 #endif