X-Git-Url: http://review.tizen.org/git/?p=platform%2Fkernel%2Fu-boot.git;a=blobdiff_plain;f=include%2Fconfigs%2Fbf537-pnav.h;h=ba74a695f88b03d8ab6c06481e8702e452de97b7;hp=6627a04f59ca4a9b9f1e6adcf851fea94533002a;hb=HEAD;hpb=3e3989619f5ed3ee28002d985f3da28540586ab9 diff --git a/include/configs/bf537-pnav.h b/include/configs/bf537-pnav.h deleted file mode 100644 index 6627a04..0000000 --- a/include/configs/bf537-pnav.h +++ /dev/null @@ -1,185 +0,0 @@ -/* - * U-boot - Configuration file for BF537 PNAV board - */ - -#ifndef __CONFIG_BF537_PNAV_H__ -#define __CONFIG_BF537_PNAV_H__ - -#include - - -/* - * Processor Settings - */ -#define CONFIG_BFIN_CPU bf537-0.2 -#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER - - -/* - * Clock Settings - * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV - * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV - */ -/* CONFIG_CLKIN_HZ is any value in Hz */ -#define CONFIG_CLKIN_HZ 24576000 -/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ -/* 1 = CLKIN / 2 */ -#define CONFIG_CLKIN_HALF 0 -/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ -/* 1 = bypass PLL */ -#define CONFIG_PLL_BYPASS 0 -/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ -/* Values can range from 0-63 (where 0 means 64) */ -#define CONFIG_VCO_MULT 20 -/* CCLK_DIV controls the core clock divider */ -/* Values can be 1, 2, 4, or 8 ONLY */ -#define CONFIG_CCLK_DIV 1 -/* SCLK_DIV controls the system clock divider */ -/* Values can range from 1-15 */ -#define CONFIG_SCLK_DIV 4 - - -/* - * Memory Settings - */ -#define CONFIG_MEM_ADD_WDTH 10 -#define CONFIG_MEM_SIZE 64 - -#define CONFIG_EBIU_SDRRC_VAL 0x3b7 -#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd - -#define CONFIG_EBIU_AMGCTL_VAL 0xFF -#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB033B0 -#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0 - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) - - -/* - * Network Settings - */ -#ifndef __ADSPBF534__ -#define ADI_CMDS_NETWORK 1 -#define CONFIG_BFIN_MAC -#define CONFIG_RMII -#define CONFIG_NET_MULTI 1 -#endif -#define CONFIG_HOSTNAME bf537-pnav -/* Uncomment next line to use fixed MAC address */ -/* #define CONFIG_ETHADDR 02:80:ad:24:21:18 */ - - -/* - * Flash Settings - */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_BASE 0x20000000 -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 71 - - -/* - * SPI Settings - */ -#define CONFIG_BFIN_SPI -#define CONFIG_ENV_SPI_MAX_HZ 30000000 -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO - - -/* - * Env Storage Settings - */ -#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) -#define CONFIG_ENV_IS_EMBEDDED_IN_LDR -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x4000 -#else -#define ENV_IS_EMBEDDED -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR 0x20004000 -#define CONFIG_ENV_OFFSET 0x4000 -#endif -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x2000 -#ifdef ENV_IS_EMBEDDED -/* WARNING - the following is hand-optimized to fit within - * the sector before the environment sector. If it throws - * an error during compilation remove an object here to get - * it linked after the configuration sector. - */ -# define LDS_BOARD_TEXT \ - cpu/blackfin/traps.o (.text .text.*); \ - cpu/blackfin/interrupt.o (.text .text.*); \ - cpu/blackfin/serial.o (.text .text.*); \ - common/dlmalloc.o (.text .text.*); \ - lib_generic/crc32.o (.text .text.*); \ - . = DEFINED(env_offset) ? env_offset : .; \ - common/env_embedded.o (.text .text.*); -#endif - - -/* - * NAND Settings - */ -#define CONFIG_NAND_PLAT - -#define CONFIG_SYS_NAND_BASE 0x20100000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 - -#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2)) -#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1)) -#define BFIN_NAND_READY PF12 -#define BFIN_NAND_WRITE(addr, cmd) \ - do { \ - bfin_write8(addr, cmd); \ - SSYNC(); \ - } while (0) - -#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd) -#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd) -#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTHIO() & BFIN_NAND_READY) -#define NAND_PLAT_INIT() \ - do { \ - bfin_write_PORTH_FER(bfin_read_PORTH_FER() & ~BFIN_NAND_READY); \ - bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() & ~BFIN_NAND_READY); \ - bfin_write_PORTHIO_INEN(bfin_read_PORTHIO_INEN() | BFIN_NAND_READY); \ - } while (0) - - -/* - * I2C settings - */ -#define CONFIG_BFIN_TWI_I2C 1 -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 50000 -#define CONFIG_SYS_I2C_SLAVE 0 - - -/* - * Misc Settings - */ -#define CONFIG_BAUDRATE 115200 -#define CONFIG_MISC_INIT_R -#define CONFIG_RTC_BFIN -#define CONFIG_UART_CONSOLE 0 - -/* JFFS Partition offset set */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 -/* 512k reserved for u-boot */ -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 15 - -#define CONFIG_BOOTCOMMAND "run nandboot" -#define CONFIG_BOOTARGS_ROOT "/dev/mtdblock1 rw rootfstype=yaffs" - - -/* - * Pull in common ADI header for remaining command/environment setup - */ -#include - -#endif