dm: i2c: tegra: Convert to driver model

[platform/kernel/u-boot.git] / include / configs / tegra30-common.h

diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index b5550d7..bfdbeb7 100644 (file)
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -23,11 +23,6 @@
  */
 #define V_NS16550_CLK          408000000       /* 408MHz (pllp_out0) */
 
-/*
- * High Level Configuration Options
- */
-#define CONFIG_TEGRA30                 /* in a NVidia Tegra30 core */
-
 /* Environment information, boards can override if required */
 #define CONFIG_LOADADDR                0x80408000      /* def. location for kernel */
 
@@ -48,6 +43,9 @@
  * scriptaddr can be pretty much anywhere that doesn't conflict with something
  *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  *
+ * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
+ *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
+ *
  * kernel_addr_r must be within the first 128M of RAM in order for the
  *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
@@ -65,6 +63,7 @@
  */
 #define MEM_LAYOUT_ENV_SETTINGS \
        "scriptaddr=0x90000000\0" \
+       "pxefile_addr_r=0x90100000\0" \
        "kernel_addr_r=0x81000000\0" \
        "fdt_addr_r=0x82000000\0" \
        "ramdisk_addr_r=0x82100000\0"
@@ -74,11 +73,9 @@
 #define CONFIG_SYS_SPL_MALLOC_START    0x80090000
 #define CONFIG_SPL_STACK               0x800ffffc
 
-/* Total I2C ports on Tegra30 */
-#define TEGRA_I2C_NUM_CONTROLLERS      5
-
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
 #define CONFIG_USB_EHCI_TXFIFO_THRESH  0x10
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA30_COMMON_H_ */