Prepare v2023.10

[platform/kernel/u-boot.git] / include / configs / tegra20-common.h

diff --git a/include/configs/tegra20-common.h b/include/configs/tegra20-common.h
index d61962a..a313ac2 100644 (file)
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra20-common.h
@@ -16,7 +16,7 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_STACKBASE       0x03800000      /* 56MB */
+#define CFG_STACKBASE  0x03800000      /* 56MB */
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
@@ -46,7 +46,6 @@
  * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
-#define CONFIG_SYS_LOAD_ADDR 0x01000000
 #define MEM_LAYOUT_ENV_SETTINGS \
        "scriptaddr=0x10000000\0" \
        "pxefile_addr_r=0x10100000\0" \
@@ -55,13 +54,6 @@
        "fdt_addr_r=0x03000000\0" \
        "ramdisk_addr_r=0x03100000\0"
 
-/* Defines for SPL */
-#define CONFIG_SYS_SPL_MALLOC_START    0x00090000
-#define CONFIG_SPL_STACK               0x000ffffc
-
-/* Align LCD to 1MB boundary */
-#define CONFIG_LCD_ALIGNMENT   MMU_SECTION_SIZE
-
 #ifdef CONFIG_TEGRA_LP0
 #define TEGRA_LP0_ADDR                 0x1C406000
 #define TEGRA_LP0_SIZE                 0x2000
@@ -72,16 +64,4 @@
 #define TEGRA_LP0_VEC
 #endif
 
-/*
- * This parameter affects a TXFILLTUNING field that controls how much data is
- * sent to the latency fifo before it is sent to the wire. Without this
- * parameter, the default (2) causes occasional Data Buffer Errors in OUT
- * packets depending on the buffer address and size.
- */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH  0x10
-#define CONFIG_EHCI_IS_TDI
-
-#define CONFIG_SYS_NAND_SELF_INIT
-#define CONFIG_SYS_NAND_ONFI_DETECTION
-
 #endif /* _TEGRA20_COMMON_H_ */