Prepare v2023.10

[platform/kernel/u-boot.git] / include / configs / tegra114-common.h

diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index 21454d4..ab4fa55 100644 (file)
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -1,16 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #ifndef _TEGRA114_COMMON_H_
 #define _TEGRA114_COMMON_H_
 #include "tegra-common.h"
 
-/* Cortex-A15 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE      64
-
 /*
  * NS16550 Configuration
  */
@@ -19,12 +15,11 @@
 /*
  * Miscellaneous configurable options
  */
-#define CONFIG_STACKBASE       0x82800000      /* 40MB */
+#define CFG_STACKBASE  0x83800000      /* 56MB */
 
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
-#define CONFIG_SYS_TEXT_BASE   0x80110000
 
 /*
  * Memory layout for where various images get loaded by boot scripts:
@@ -41,31 +36,23 @@
  *   should not overlap that area, or the kernel will have to copy itself
  *   somewhere else before decompression. Similarly, the address of any other
  *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
- *   this up to 16M allows for a sizable kernel to be decompressed below the
+ *   this up to 32M allows for a sizable kernel to be decompressed below the
  *   compressed load address.
  *
- * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
- *   the compressed kernel to be up to 16M too.
+ * fdt_addr_r simply shouldn't overlap anything else. Choosing 48M allows for
+ *   the compressed kernel to be up to 32M too.
  *
- * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
+ * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 49M allows
  *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  */
-#define CONFIG_LOADADDR 0x81000000
 #define MEM_LAYOUT_ENV_SETTINGS \
        "scriptaddr=0x90000000\0" \
        "pxefile_addr_r=0x90100000\0" \
-       "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
-       "fdt_addr_r=0x82000000\0" \
-       "ramdisk_addr_r=0x82100000\0"
+       "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+       "fdtfile=" FDTFILE "\0" \
+       "fdt_addr_r=0x83000000\0" \
+       "ramdisk_addr_r=0x83100000\0"
 
 /* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE           0x80108000
-#define CONFIG_SYS_SPL_MALLOC_START    0x80090000
-#define CONFIG_SPL_STACK               0x800ffffc
-
-/* For USB EHCI controller */
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_USB_EHCI_TXFIFO_THRESH  0x10
-#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
 
 #endif /* _TEGRA114_COMMON_H_ */