Big white-space cleanup.

[platform/kernel/u-boot.git] / include / configs / stxxtc.h

diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h
index be6c36c..97a1032 100644 (file)
--- a/include/configs/stxxtc.h
+++ b/include/configs/stxxtc.h
@@ -63,9 +63,9 @@
 
 #undef CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND                                                     \
-       "tftpboot; "                                                            \
-       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
-       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
+       "tftpboot; "                                                            \
+       "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
+       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
        "bootm"
 
 #define CONFIG_AUTOSCRIPT
@@ -77,21 +77,31 @@
 #define        CONFIG_STATUS_LED       1       /* Status LED enabled           */
 #define CONFIG_BOARD_SPECIFIC_LED      /* version has board specific leds */
 
-#define CONFIG_BOOTP_MASK              (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_NISDOMAIN
+
 
 #undef CONFIG_MAC_PARTITION
 #undef CONFIG_DOS_PARTITION
 
 #define        CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 
-#define        CONFIG_NET_MULTI        1       /* the only way to get the FEC in */
+#define        CONFIG_NET_MULTI        1       /* the only way to get the FEC in */
 #define        FEC_ENET                1       /* eth.c needs it that way... */
 #undef CFG_DISCOVER_PHY
 #define CONFIG_MII             1
+#define CONFIG_MII_INIT                1
 #undef CONFIG_RMII
 
 #define CONFIG_ETHER_ON_FEC1   1
-#define CONFIG_FEC1_PHY                1       /* phy address of FEC */
+#define CONFIG_FEC1_PHY                1       /* phy address of FEC */
 #undef CONFIG_FEC1_PHY_NORXERR
 
 #define CONFIG_ETHER_ON_FEC2   1
@@ -100,19 +110,22 @@
 
 #define CONFIG_ENV_OVERWRITE   1       /* allow modification of vendor params */
 
-#define CONFIG_COMMANDS       ( CONFIG_CMD_DFL | \
-                               CFG_CMD_NAND    | \
-                               CFG_CMD_DHCP    | \
-                               CFG_CMD_PING    | \
-                               CFG_CMD_MII     | \
-                               CFG_CMD_NFS)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PING
+
 
 #define CONFIG_BOARD_EARLY_INIT_F      1
 #define CONFIG_MISC_INIT_R
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
 /*
  * Miscellaneous configurable options
  */
@@ -122,7 +135,7 @@
 #define CFG_HUSH_PARSER        1
 #define CFG_PROMPT_HUSH_PS2    "> "
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define        CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 #else
 #define        CFG_CBSIZE      256             /* Console I/O Buffer Size      */
@@ -201,7 +214,7 @@
 
 #define CFG_FLASH_CFI          1
 #define CFG_FLASH_CFI_DRIVER   1
-#undef CFG_FLASH_USE_BUFFER_WRITE      /* use buffered writes (20x faster) */
+#undef CFG_FLASH_USE_BUFFER_WRITE      /* use buffered writes (20x faster) */
 #define CFG_MAX_FLASH_SECT     128     /* max number of sectors on one chip */
 #define CFG_MAX_FLASH_BANKS    2       /* max number of memory banks   */
 
@@ -213,7 +226,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE     16      /* For all MPC8xx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT    4       /* log base 2 of the above value */
 #endif
 
@@ -270,11 +283,11 @@
 #if MPC8XX_HZ == 50000000
 #define CFG_PLPRCR     ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
                         (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 66666666
 #define CFG_PLPRCR     ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
                         (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-                        PLPRCR_TEXPS)
+                        PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 10MHz
 #endif
@@ -436,6 +449,7 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE          NAND_BASE
 #define CONFIG_MTD_NAND_ECC_JFFS2
 #define CONFIG_MTD_NAND_VERIFY_WRITE
@@ -448,7 +462,7 @@
 #define ADDR_COLUMN            1
 #define ADDR_PAGE              2
 #define ADDR_COLUMN_PAGE       3
-#define NAND_ChipID_UNKNOWN    0x00
+#define NAND_ChipID_UNKNOWN    0x00
 #define NAND_MAX_FLOORS                1
 #define NAND_MAX_CHIPS         1
 
@@ -579,12 +593,7 @@ typedef unsigned int led_id_t;
 /* pass open firmware flat tree */
 #define CONFIG_OF_FLAT_TREE    1
 
-/* maximum size of the flat tree (8K) */
-#define OF_FLAT_TREE_MAX_SIZE  8192
-
 #define OF_CPU                 "PowerPC,MPC870@0"
 #define OF_TBCLK               (MPC8XX_HZ / 16)
-#define CONFIG_OF_HAS_BD_T     1
-#define CONFIG_OF_HAS_UBOOT_ENV        1
 
 #endif /* __CONFIG_H */