Convert CONFIG_SYS_MMC_ENV_DEV et al to Kconfig

[platform/kernel/u-boot.git] / include / configs / socfpga_common.h

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 05bfef7..3d71759 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -5,6 +5,8 @@
 #ifndef __CONFIG_SOCFPGA_COMMON_H__
 #define __CONFIG_SOCFPGA_COMMON_H__
 
+#include <linux/stringify.h>
+
 /*
  * High level configuration
  */
@@ -17,18 +19,17 @@
  */
 #define PHYS_SDRAM_1                   0x0
 #define CONFIG_SYS_MALLOC_LEN          (64 * 1024 * 1024)
-#define CONFIG_SYS_MEMTEST_START       PHYS_SDRAM_1
-#define CONFIG_SYS_MEMTEST_END         PHYS_SDRAM_1_SIZE
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFFFF0000
-#define CONFIG_SYS_INIT_RAM_SIZE       0x10000
+#define CONFIG_SYS_INIT_RAM_SIZE       SOCFPGA_PHYS_OCRAM_SIZE
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #define CONFIG_SYS_INIT_RAM_ADDR       0xFFE00000
 /* SPL memory allocation configuration, this is for FAT implementation */
 #ifndef CONFIG_SYS_SPL_MALLOC_SIZE
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x10000
 #endif
-#define CONFIG_SYS_INIT_RAM_SIZE       (0x40000 - CONFIG_SYS_SPL_MALLOC_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE       (SOCFPGA_PHYS_OCRAM_SIZE - \
+                                        CONFIG_SYS_SPL_MALLOC_SIZE)
 #define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SYS_INIT_RAM_ADDR + \
                                         CONFIG_SYS_INIT_RAM_SIZE)
 #endif
@@ -94,21 +95,19 @@
  * L4 OSC1 Timer 0
  */
 #ifndef CONFIG_TIMER
-/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
 #define CONFIG_SYS_TIMERBASE           SOCFPGA_OSC1TIMER0_ADDRESS
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMERBASE + 0x4)
+#ifndef CONFIG_SYS_TIMER_RATE
 #define CONFIG_SYS_TIMER_RATE          25000000
 #endif
+#endif
 
 /*
  * L4 Watchdog
  */
-#ifdef CONFIG_HW_WATCHDOG
-#define CONFIG_DESIGNWARE_WATCHDOG
 #define CONFIG_DW_WDT_BASE             SOCFPGA_L4WD0_ADDRESS
 #define CONFIG_DW_WDT_CLOCK_KHZ                25000
-#endif
 
 /*
  * MMC Driver
@@ -123,6 +122,7 @@
  * NAND Support
  */
 #ifdef CONFIG_NAND_DENALI
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS  0
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 #define CONFIG_SYS_NAND_REGS_BASE      SOCFPGA_NANDREGS_ADDRESS
@@ -159,9 +159,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
  */
 
 /* Environment for SDMMC boot */
-#if defined(CONFIG_ENV_IS_IN_MMC)
-#define CONFIG_SYS_MMC_ENV_DEV         0 /* device 0 */
-#endif
 
 /* Environment for QSPI boot */
 
@@ -191,7 +188,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #ifdef CONFIG_SPL_MMC_SUPPORT
 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-boot.img"
-#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
 #endif
 #else
 #ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION