#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* NAND flash */
-#define CONFIG_SYS_NAND_BASE 0x40000000
+#define CFG_SYS_NAND_BASE 0x40000000
/* our ALE is AD22 */
-#define CONFIG_SYS_NAND_MASK_ALE (1 << 22)
+#define CFG_SYS_NAND_MASK_ALE (1 << 22)
/* our CLE is AD21 */
-#define CONFIG_SYS_NAND_MASK_CLE (1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
-#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
+#define CFG_SYS_NAND_MASK_CLE (1 << 21)
+#define CFG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
+#define CFG_SYS_NAND_READY_PIN GPIO_PIN_PA(16)
/* NOR flash */
#define PHYS_FLASH_1 0x10000000