#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE
*/
/* controller 2, direct to uli, tgtid 2, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
-#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
#else
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
#endif
-#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2, tgtid 1, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
#else
-#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
-#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
#endif
+
+#if !defined(CONFIG_DM_PCI)
+#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE
+#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
+#else
+#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
+#endif
+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
+
+#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
+#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
+#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
/*
* Environment
*/
-#ifdef CONFIG_SPIFLASH
-#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
-#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#elif defined(CONFIG_SDCARD)
+#if defined(CONFIG_SDCARD)
#define CONFIG_FSL_FIXED_MMC_LOCATION
-#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#elif defined(CONFIG_NAND)
+#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#ifdef CONFIG_TPL_BUILD
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
-#else
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
+#define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
#endif
-#define CONFIG_ENV_OFFSET (1024 * 1024)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#elif defined(CONFIG_SYS_RAMBOOT)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE 0x2000
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#define SPL_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#endif
#define CONFIG_LOADS_ECHO /* echo on for serial download */