global: Move remaining CONFIG_SYS_SDRAM_* to CFG_SYS_SDRAM_*

[platform/kernel/u-boot.git] / include / configs / omapl138_lcdk.h

diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h
index 1036a05..5b0d87a 100644 (file)
--- a/include/configs/omapl138_lcdk.h
+++ b/include/configs/omapl138_lcdk.h
@@ -17,10 +17,6 @@
 /*
  * SoC Configuration
  */
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-#define CONFIG_SYS_CLK_FREQ            get_board_sys_clk()
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_HZ_CLOCK            clk_get(DAVINCI_AUXCLK_CLKID)
@@ -32,9 +28,6 @@ unsigned long get_board_sys_clk(void);
 #define PHYS_SDRAM_1_SIZE      (128 << 20) /* SDRAM size 128MB */
 #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
 
-#define CONFIG_SPL_BSS_START_ADDR DAVINCI_DDR_EMIF_DATA_BASE
-#define CONFIG_SPL_BSS_MAX_SIZE 0x1080000
-
 /* memtest start addr */
 
 /* memtest will be run on 16MB */
@@ -98,7 +91,7 @@ unsigned long get_board_sys_clk(void);
 /*
  * Serial Driver info
  */
-#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
+#define CFG_SYS_NS16550_CLK    clk_get(DAVINCI_UART2_CLKID)
 
 #define CONFIG_SYS_SPI_BASE            DAVINCI_SPI1_BASE
 #define CONFIG_SYS_SPI_CLK             clk_get(DAVINCI_SPI1_CLKID)
@@ -106,59 +99,32 @@ unsigned long get_board_sys_clk(void);
 /*
  * I2C Configuration
  */
-#define CONFIG_SYS_DAVINCI_I2C_SPEED   25000
-#define CONFIG_SYS_DAVINCI_I2C_SLAVE   10 /* Bogus, master-only in U-Boot */
 #define CONFIG_SYS_I2C_EXPANDER_ADDR   0x20
 
 /*
  * Flash & Environment
  */
 #ifdef CONFIG_MTD_RAW_NAND
-#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
-#define        CONFIG_SYS_NAND_PAGE_2K
-#define CONFIG_SYS_NAND_CS             3
-#define CONFIG_SYS_NAND_BASE           DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
-#define CONFIG_SYS_NAND_MASK_CLE       0x10
-#define CONFIG_SYS_NAND_MASK_ALE       0x8
-#undef CONFIG_SYS_NAND_HW_ECC
-#define CONFIG_SYS_MAX_NAND_DEVICE     1 /* Max number of NAND devices */
-#define CONFIG_SYS_NAND_HW_ECC_OOBFIRST
+#define CFG_SYS_NAND_CS                3
+#define CFG_SYS_NAND_BASE              DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
+#define CFG_SYS_NAND_MASK_CLE  0x10
+#define CFG_SYS_NAND_MASK_ALE  0x8
 #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
-#define CONFIG_SYS_NAND_U_BOOT_SIZE    SZ_512K
-#define CONFIG_SYS_NAND_U_BOOT_DST     0xc1080000
-#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_NAND_U_BOOT_DST
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP        (CONFIG_SYS_NAND_U_BOOT_DST - \
-                                       CONFIG_SYS_NAND_U_BOOT_SIZE - \
-                                       CONFIG_SYS_MALLOC_LEN -       \
-                                       GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_NAND_ECCPOS         {                               \
+#define CFG_SYS_NAND_U_BOOT_SIZE       SZ_512K
+#define CFG_SYS_NAND_U_BOOT_DST        0xc1080000
+#define CFG_SYS_NAND_U_BOOT_START      CFG_SYS_NAND_U_BOOT_DST
+#define CFG_SYS_NAND_ECCPOS            {                               \
                                6, 7, 8, 9, 10, 11, 12, 13, 14, 15,     \
                                22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
                                38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
                                54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
-#define CONFIG_SYS_NAND_ECCSIZE                512
-#define CONFIG_SYS_NAND_ECCBYTES       10
-#endif
-
-/*
- * Network & Ethernet Configuration
- */
-#ifdef CONFIG_DRIVER_TI_EMAC
-#define CONFIG_NET_RETRY_COUNT 10
+#define CFG_SYS_NAND_ECCSIZE           512
+#define CFG_SYS_NAND_ECCBYTES  10
 #endif
 
 /*
  * U-Boot general configuration
  */
-#define CONFIG_BOOTFILE                "zImage" /* Boot file name */
-#define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size */
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
-
-/*
- * USB Configs
- */
-#define CONFIG_USB_OHCI_NEW
-#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     15
 
 /*
  * Linux Information
@@ -183,24 +149,12 @@ unsigned long get_board_sys_clk(void);
        "boot_fit=0\0" \
        "console=ttyS2,115200n8\0"
 
-#ifdef CONFIG_CMD_BDI
-#define CONFIG_CLOCKS
-#endif
-
 /* SD/MMC */
 
 /* defines for SPL */
-#define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SYS_TEXT_BASE - \
-                                               CONFIG_SYS_MALLOC_LEN)
-#define CONFIG_SYS_SPL_MALLOC_SIZE     CONFIG_SYS_MALLOC_LEN
-#define CONFIG_SPL_STACK       0x8001ff00
-#define CONFIG_SPL_MAX_FOOTPRINT       32768
-#define CONFIG_SPL_PAD_TO      32768
 
 /* additions for new relocation code, must added to all boards */
-#define CONFIG_SYS_SDRAM_BASE          0xc0000000
-#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \
-                                       GENERATED_GBL_DATA_SIZE)
+#define CFG_SYS_SDRAM_BASE             0xc0000000
 
 #include <asm/arch/hardware.h>