Prepare v2023.10

[platform/kernel/u-boot.git] / include / configs / mxs.h

diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index 51624a2..6ebfee6 100644 (file)
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -43,27 +43,17 @@
 
 /* Startup hooks */
 
-/* SPL */
-#ifndef CONFIG_SPL_FRAMEWORK
-#define CONFIG_SPL_NO_CPU_SUPPORT
-#define CONFIG_SPL_START_S_PATH        "arch/arm/cpu/arm926ejs/mxs"
-#endif
-
 /* Memory sizes */
 
 /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
-#define CONFIG_SYS_INIT_RAM_ADDR       0x00000000
+#define CFG_SYS_INIT_RAM_ADDR  0x00000000
 #if defined(CONFIG_MX23)
-#define CONFIG_SYS_INIT_RAM_SIZE       (32 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE  (32 * 1024)
 #elif defined(CONFIG_MX28)
-#define CONFIG_SYS_INIT_RAM_SIZE       (128 * 1024)
+#define CFG_SYS_INIT_RAM_SIZE  (128 * 1024)
 #endif
 
 /* Point initial SP in SRAM so SPL can use it too. */
-#define CONFIG_SYS_INIT_SP_OFFSET \
-       (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR \
-       (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
 /*
  * We need to sacrifice first 4 bytes of RAM here to avoid triggering some
@@ -79,10 +69,6 @@
  */
 
 /* U-Boot general configuration */
-#define CONFIG_SYS_CBSIZE      1024            /* Console I/O buffer size */
-#define CONFIG_SYS_MAXARGS     32              /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE
-                                               /* Boot argument buffer size */
 
 /*
  * Drivers
@@ -91,34 +77,13 @@
  * DUART Serial Driver.
  * Conflicts with AUART driver which can be set by board.
  */
-#define CONFIG_PL011_CLOCK             24000000
-#define CONFIG_PL01x_PORTS             { (void *)MXS_UARTDBG_BASE }
+#define CFG_PL011_CLOCK                24000000
+#define CFG_PL01x_PORTS                { (void *)MXS_UARTDBG_BASE }
 /* Default baudrate can be overridden by board! */
 
-/* FEC Ethernet on SoC */
-#ifdef CONFIG_FEC_MXC
-#ifndef CONFIG_ETHPRIME
-#define CONFIG_ETHPRIME                        "FEC0"
-#endif
-#ifndef CONFIG_FEC_XCV_TYPE
-#define CONFIG_FEC_XCV_TYPE            RMII
-#endif
-#endif
-
 /* NAND */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE           0x60000000
-#endif
-
-/* OCOTP */
-#ifdef CONFIG_CMD_FUSE
-#define CONFIG_MXS_OCOTP
-#endif
-
-/* SPI */
-#ifdef CONFIG_CMD_SPI
-#define CONFIG_SPI_HALF_DUPLEX
+#define CFG_SYS_NAND_BASE              0x60000000
 #endif
 
 #endif /* __CONFIGS_MXS_H__ */