#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
#define CONFIG_MUCMC52 1 /* MUCMC52 board */
-#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
-#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_KGDB)
+# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
#endif
#define CONFIG_BOARD_EARLY_INIT_R
*/
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#define CONFIG_BAUDRATE 38400 /* ... at 38400 bps */
-#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
/* Partitions */
#define CONFIG_DOS_PARTITION
#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
#if (TEXT_BASE == 0xFFF00000) /* Boot low */
-# define CFG_LOWBOOT 1
+# define CONFIG_SYS_LOWBOOT 1
#endif
/*
/*
* IPB Bus clocking configuration.
*/
-#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
+#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
/*
* I2C configuration
*/
#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
-#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
-#define CFG_I2C_SPEED 100000 /* 100 kHz */
-#define CFG_I2C_SLAVE 0x7F
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
/*
* EEPROM configuration
*/
-#define CFG_I2C_EEPROM_ADDR 0x58
-#define CFG_I2C_EEPROM_ADDR_LEN 1
-#define CFG_EEPROM_PAGE_WRITE_BITS 4
-#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/*
* RTC configuration
*/
#define CONFIG_RTC_PCF8563
-#define CFG_I2C_RTC_ADDR 0x51
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
/* I2C SYSMON (LM75) */
#define CONFIG_DTT_LM81 1 /* ON Semi's LM75 */
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#define CFG_DTT_MAX_TEMP 70
-#define CFG_DTT_LOW_TEMP -30
-#define CFG_DTT_HYSTERESIS 3
+#define CONFIG_SYS_DTT_MAX_TEMP 70
+#define CONFIG_SYS_DTT_LOW_TEMP -30
+#define CONFIG_SYS_DTT_HYSTERESIS 3
/*
* Flash configuration
*/
-#define CFG_FLASH_BASE 0xFF800000
+#define CONFIG_SYS_FLASH_BASE 0xFF800000
-#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */
-#define CFG_MAX_FLASH_SECT 67 /* max num of sects on one chip */
+#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */
+#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max num of sects on one chip */
#define CONFIG_ENV_ADDR (TEXT_BASE+0x40000) /* second sector */
-#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
+#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks
(= chip selects) */
-#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
-#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
#define CONFIG_FLASH_CFI_DRIVER
-#define CFG_FLASH_CFI
-#define CFG_FLASH_EMPTY_INFO
-#define CFG_FLASH_CFI_AMD_RESET
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_AMD_RESET
/*
* Environment settings
/*
* Memory map
*/
-#define CFG_MBAR 0xF0000000
-#define CFG_SDRAM_BASE 0x00000000
-#define CFG_DEFAULT_MBAR 0x80000000
-#define CFG_DISPLAY_BASE 0x80600000
-#define CFG_STATUS1_BASE 0x80600200
-#define CFG_STATUS2_BASE 0x80600300
-#define CFG_PMI_UNI_BASE 0x80800000
-#define CFG_PMI_BROAD_BASE 0x80810000
+#define CONFIG_SYS_MBAR 0xF0000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
+#define CONFIG_SYS_DISPLAY_BASE 0x80600000
+#define CONFIG_SYS_STATUS1_BASE 0x80600200
+#define CONFIG_SYS_STATUS2_BASE 0x80600300
+#define CONFIG_SYS_PMI_UNI_BASE 0x80800000
+#define CONFIG_SYS_PMI_BROAD_BASE 0x80810000
/* Settings for XLB = 132 MHz */
#define SDRAM_DDR 1
#define SDRAM_TAPDELAY 0x10000000
/* Use ON-Chip SRAM until RAM will be available */
-#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
-#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
#else
-#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
#endif
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#define CFG_MONITOR_BASE TEXT_BASE
-#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
-# define CFG_RAMBOOT 1
+#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
+#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
+# define CONFIG_SYS_RAMBOOT 1
#endif
-#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CFG_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
-#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
+#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 128 kB for malloc() */
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
/*
* Ethernet configuration
/*
* GPIO configuration
*/
-#define CFG_GPS_PORT_CONFIG 0x8D550644
+#define CONFIG_SYS_GPS_PORT_CONFIG 0x8D550644
/*use Hardware WDT */
#define CONFIG_HW_WATCHDOG
/*
* Miscellaneous configurable options
*/
-#define CFG_LONGHELP /* undef to save memory */
-#define CFG_PROMPT "=> " /* Monitor Command Prompt */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
-#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CONFIG_SYS_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
#else
-#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif
-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
-#define CFG_MAXARGS 16 /* max number of command args */
-#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
/* Enable an alternate, more extensive memory test */
-#define CFG_ALT_MEMTEST
+#define CONFIG_SYS_ALT_MEMTEST
-#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
-#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
+#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-#define CFG_LOAD_ADDR 0x100000 /* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
/*
- * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * Enable loopw commando. This has only affect, if CONFIG_SYS_CMD_MEM is defined,
* which is normally part of the default commands (CFV_CMD_DFL)
*/
#define CONFIG_LOOPW
* Various low-level settings
*/
#if defined(CONFIG_MPC5200)
-#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
-#define CFG_HID0_FINAL HID0_ICE
+#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
+#define CONFIG_SYS_HID0_FINAL HID0_ICE
#else
-#define CFG_HID0_INIT 0
-#define CFG_HID0_FINAL 0
+#define CONFIG_SYS_HID0_INIT 0
+#define CONFIG_SYS_HID0_FINAL 0
#endif
-#define CFG_BOOTCS_START CFG_FLASH_BASE
-#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG 0x0004FB00
-#define CFG_CS0_START CFG_FLASH_BASE
-#define CFG_CS0_SIZE CFG_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_BOOTCS_CFG 0x0004FB00
+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
/* 8Mbit SRAM @0x80100000 */
-#define CFG_CS1_START 0x80100000
-#define CFG_CS1_SIZE 0x00100000
-#define CFG_CS1_CFG 0x00019B00
+#define CONFIG_SYS_CS1_START 0x80100000
+#define CONFIG_SYS_CS1_SIZE 0x00100000
+#define CONFIG_SYS_CS1_CFG 0x00019B00
/* FRAM 32Kbyte @0x80700000 */
-#define CFG_CS2_START 0x80700000
-#define CFG_CS2_SIZE 0x00008000
-#define CFG_CS2_CFG 0x00019800
+#define CONFIG_SYS_CS2_START 0x80700000
+#define CONFIG_SYS_CS2_SIZE 0x00008000
+#define CONFIG_SYS_CS2_CFG 0x00019800
/* Display H1, Status Inputs, EPLD @0x80600000 */
-#define CFG_CS3_START 0x80600000
-#define CFG_CS3_SIZE 0x00100000
-#define CFG_CS3_CFG 0x00019800
+#define CONFIG_SYS_CS3_START 0x80600000
+#define CONFIG_SYS_CS3_SIZE 0x00100000
+#define CONFIG_SYS_CS3_CFG 0x00019800
/* PMI Unicast 32Kbyte @0x80800000 */
-#define CFG_CS6_START CFG_PMI_UNI_BASE
-#define CFG_CS6_SIZE 0x00008000
-#define CFG_CS6_CFG 0xFFFFF930
+#define CONFIG_SYS_CS6_START CONFIG_SYS_PMI_UNI_BASE
+#define CONFIG_SYS_CS6_SIZE 0x00008000
+#define CONFIG_SYS_CS6_CFG 0xFFFFF930
/* PMI Broadcast 32Kbyte @0x80810000 */
-#define CFG_CS7_START CFG_PMI_BROAD_BASE
-#define CFG_CS7_SIZE 0x00008000
-#define CFG_CS7_CFG 0xFF00F930
+#define CONFIG_SYS_CS7_START CONFIG_SYS_PMI_BROAD_BASE
+#define CONFIG_SYS_CS7_SIZE 0x00008000
+#define CONFIG_SYS_CS7_CFG 0xFF00F930
-#define CFG_CS_BURST 0x00000000
-#define CFG_CS_DEADCYCLE 0x33333333
+#define CONFIG_SYS_CS_BURST 0x00000000
+#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
/*-----------------------------------------------------------------------
* IDE/ATA stuff Supports IDE harddisk
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
-#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CFG_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 2 drives per IDE bus */
#define CONFIG_IDE_PREINIT 1
-#define CFG_ATA_IDE0_OFFSET 0x0000
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
-#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
+#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
/* Offset for data I/O */
-#define CFG_ATA_DATA_OFFSET (0x0060)
+#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
/* Offset for normal register accesses */
-#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
+#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
/* Offset for alternate registers */
-#define CFG_ATA_ALT_OFFSET (0x005C)
+#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
/* Interval between registers */
-#define CFG_ATA_STRIDE 4
+#define CONFIG_SYS_ATA_STRIDE 4
#define CONFIG_ATAPI 1
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0x01000000
-#define CFG_ISA_IO CONFIG_PCI_IO_BUS
+#define CONFIG_SYS_ISA_IO CONFIG_PCI_IO_BUS
/*---------------------------------------------------------------------*/
/* Display addresses */
/*---------------------------------------------------------------------*/
-#define CFG_DISP_CHR_RAM (CFG_DISPLAY_BASE + 0x38)
-#define CFG_DISP_CWORD (CFG_DISPLAY_BASE + 0x30)
+#define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
+#define CONFIG_SYS_DISP_CWORD (CONFIG_SYS_DISPLAY_BASE + 0x30)
#endif /* __CONFIG_H */
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